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High-Speed Baud-Rate Clock and Data Recovery by Danny

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High-Speed Baud-Rate Clock and Data Recovery by Danny High-Speed Baud-Rate Clock and Data Recovery by Danny Yoo A thesis submitted in conformity with the requirements for the degree of Master of Applied Science The Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto c Copyright 2018 by Danny Yoo Abstract High-Speed Baud-Rate Clock and Data Recovery Danny Yoo Master of Applied Science The Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto 2018 This thesis presents an adaptive baud-rate CDR with CTLE and 1-tap DFE. The novelty in this design is the adaptation engine tailored for baud-rate clock and data recovery where the comparators for the DFE and the PD are shared to save power. A testchip was fabricated in TSMC 28nm CMOS. The adaptation engine is demonstrated for 34-36Gb/s operation with a Tyco 5" channel resulting in 15.05-18.25dB channel losses. At 35Gb/s, the total power consumption is measured to be 106.3mW or a FOM of 3.04pJ/bit. This thesis also presents a 2x half-baud-rate clock and data recovery technique with 2x oversampling at half-baud-rate (every other UI). A testchip was also fabricated in TSMC 28nm CMOS. A 30Gb/s 2x half-baud-rate CDR was tested with a Tyco 5" channel with 13.06dB of loss. The total power consumption is measured to be 79.2mW or a FOM of 2.64pJ/bit. ii Acknowledgements I would like to sincerely thank my supervisor, Professor Ali Sheikholeslami for providing me the opportunity to conduct research in the area of high-speed wireline circuits. Pro- fessor Sheikholeslami has supported me throughout every step of my tapeout, which is fabricated in a leading-edge advanced process technology. I thank Professor David Johns, Professor Tony Chan Carusone and Professor Joyce Poon for serving on my thesis examination committee. Their insightful comments and recommendations were invaluable addition to this thesis. I am thankful for the support and design review provided by Fujitsu's staff, espe- cially, Hirotaka Tamura, Takayuki Shibasaki and Junji Ogawa. Special thanks to Wahid Rahman and Joshua Liang for guidance throughout my MASc research and Mohammad Tabrizi for layout and measurement support. I would also like to thank Nikola Nedovic for his visit to help set up the digital synthesis flow back in 2015, which still had an impact on my 2017 tapeout. My gratitude goes out to Jaro Pristupa and MOSIS support team for CAD and tech- nical support. I would also like to acknowledge Professor Antonio Liscidini, Professor Sorin Voinigescu and CMC for test equipment rental as I could not have finished my testchip measurements without them. Finally, I would like send my deepest thanks to my parents and my brother for their unconditional love and support. iii Contents Acknowledgements iii Table of Contents iv List of Figures vii List of Abbreviations x 1 Introduction 1 1.1 Motivation............................................1 1.2 An Adaptive Baud-Rate CDR..................................1 1.3 A 2x Half-Baud-Rate CDR...................................2 1.4 Thesis Outline..........................................2 2 Background 3 2.1 Overview of Baud-Rate PD...................................3 2.2 Pattern-based Baud-Rate Scheme................................3 2.2.1 Pattern Detection....................................4 2.2.2 Optimal Sampling Point.................................4 2.3 Why Adaptation Engine?....................................7 2.3.1 Challenges........................................7 2.3.2 CTLE Adaptation....................................7 2.3.3 Comparator Level Adaptation..............................9 3 Proposed Adaptation Engine 11 3.1 Data Level Loop......................................... 12 3.2 Goals for On-Chip Adaptation................................. 13 3.3 Adaptation Flow......................................... 15 3.4 Part 1: CTLE Adaptation.................................... 17 3.5 Part 2: Comparator Level Adaptation............................. 20 3.6 Summary of Adaptation..................................... 24 3.7 System-level Behavioral Model................................. 26 3.7.1 Behavioral Model: Continuous-time Model...................... 26 3.7.2 Behavioral Model: Event-driven Model......................... 28 iv 4 Circuit Simulations and Measurement Results 32 4.1 Analog Design.......................................... 32 4.1.1 Closed-loop CDR Simulations.............................. 37 4.2 Digital Design........................................... 38 4.3 Lab Measurements........................................ 40 4.3.1 Testchip.......................................... 40 4.3.2 Test Setup........................................ 41 4.3.3 Measurement Results.................................. 46 5 Proposed 2x Half-Baud-Rate CDR 55 5.1 Background............................................ 55 5.1.1 Alexander 2x-oversampled Bang-Bang PD....................... 55 5.1.2 Mueller-Muller Baud-Rate PD............................. 57 5.1.3 Sub-Baud-Rate Clock and Data Recovery....................... 57 5.2 Proposed 2x half-baud-rate scheme............................... 58 5.2.1 System-level Behavioral Model............................. 63 5.3 Circuit Implementation & Simulations............................. 65 5.3.1 Analog Design...................................... 65 5.3.2 Closed-loop CDR Simulations.............................. 66 5.3.3 Digital Design...................................... 68 5.4 Lab Measurements........................................ 68 5.4.1 Testchip.......................................... 70 5.4.2 Test Setup........................................ 70 5.4.3 Measurement Results.................................. 71 6 Chip Design Methodology 80 6.1 Behaviour Model Methodology................................. 80 6.2 Schematic & Layout Design Methodology........................... 80 6.3 Advanced Layout Techniques & Considerations........................ 81 6.3.1 Matching......................................... 81 6.3.2 Design for Electromigration (EM) & IR drop..................... 83 6.3.3 Other Layout Considerations.............................. 84 6.4 Place & Route Digital Implementation Methodology..................... 84 7 Conclusion 86 7.1 Thesis Contribution....................................... 86 7.2 Future Works........................................... 87 7.2.1 Improvements for an Adaptive Baud-Rate CDR.................... 87 7.2.2 Improvements for a 2x Half-Baud-Rate CDR..................... 87 Bibliography 89 Appendices 94 v A Ancillary 95 A.1 Portlist for Synthesized Digital................................. 95 A.2 Output Pad MUX Selection................................... 96 vi List of Figures 2.1 ISSCC 2016 Shibasaki's Baud-Rate CDR...........................5 2.2 Shibasaki's proposed analog front-end (VLSI2014) [34]....................5 2.3 Pattern detection of Shibasaki's baud-rate PD.........................5 2.4 Eye opening of 1-tap speculative DFE for Shibasaki's baud-rate PD............6 2.5 VLSI2014 Shibasaki's proposed PD logic [34].........................6 2.6 Sub-optimal α levels illustrating reduced eye opening for noise and jitter margin.....8 2.7 Pulse response of Channel + CTLE..............................8 2.8 Eye diagram demonstrating (1+α) - (1-α) = 2α ........................9 2.9 LMS for adapting comparators for DFE............................ 10 3.1 Full-rate system level block diagram of CDR and the proposed adaptation engine..... 12 3.2 Block diagram of proposed data level loop........................... 13 3.3 Example of dLev converging................................... 13 3.4 Example of data level (dLev) filtered for 111 and 011 pattern................ 14 3.5 Diagram illustrating the goal of on-chip adaptation...................... 14 3.6 Diagram illustrating the optimal PD level........................... 15 3.7 Diagram of eye opening for comparator optimized for DFE and PD respectively...... 16 3.8 Flow Diagram of Proposed Adaptation Engine........................ 17 3.9 Schematic of a CTLE stage with tunable Cs.......................... 18 3.10 CTLE transfer function across Cs settings simulated in MATLAB Simulink........ 19 3.11 CTLE adaptation using line thickness............................. 21 3.12 Block diagram of spectrum balancing [17]........................... 22 3.13 CTLE transfer function showing 0011 pattern and its neighboring patterns for three dif- ferent CTLE settings....................................... 22 3.14 Visual Example of CTLE adaptation.............................. 23 3.15 Visual example of theory behind the proposed algorithm for finding optimal PD level... 24 3.16 Visual example of finding Vamp ................................. 25 3.17 Visual example of why Vamp = dLev(011)max ......................... 25 3.18 Adaptation where line thickness guides CTLE adaptation of Cs (top right) and optimal sampling phase deduced from the slew rate guides adaptation of comparator level.... 26 3.19 Proposed schematic of quarter-rate baud-rate receiver. Digital adaptation is completed in digital back-end and the rest of the CDR is done in analog front-end.......... 27 3.20 Plot of channel characteristic of various channels imported and converted to rational system model in MATLAB................................... 28 vii 3.21 Adaptation vs time where line thickness guides CTLE adaptation and optimal PD level guides α level adaptation. Tyco 5" channel at 36 Gb/s.................... 29 3.22 Step response and pulse response of channel + CTLE.................... 30 3.23
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