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Design and Simulation of a PCI Express Gen 3.0 Communication Channel

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Design and Simulation of a PCI Express Gen 3.0 Communication Channel Design and Simulation of a PCI Express Gen 3.0 Communication Channel By MASSACHUSETTS INSTITUTE OF TECHNOLOGY Dilini Warnakulasuriyarachchi AUG 2 4 2010 S.B. Electrical Science & Engineering LIBRARIES Massachusetts Institute of Technology, 2009 ARCHIVES SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF ENGINEERING IN ELECTRICAL ENGINEERING & COMPUTER SCIENCE AT THE MASSACHUSETTS INSTITUTE OF TECHNOLOGY MAY 2010 UNuvne Z010 I 0 2010 Massachusetts Institute of Technology. All rights reserved. Signature of Authoi Department of Electrical Engineering and Computer Science May 7, 2010 Certified by: Scott Westbrook Senior Member of the Technical Staff, NetApp VI-A Company Thesis Supervisor Certified by: _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ _ Vladimir Stojanovic Associate Professor, Department of Electrical Engineering and Computer Studies MIT Thesis Supervisor Accepted by: J1 Dr. Christopher J. Terman Chairman, Department Committee on Graduate Theses Dr. Christopher J. Terman Department of Electrical Engineering and Computer Science Room 3 8-476, M.I.T. Cambridge, MA 02139 Subject: Master of Engineering Thesis of Dilini Warnakulasuriyarachchi Dear Dr. Terman: I have reviewed the attached thesis of Dilini Warnakulasuriyarachchi on behalf of NetApp. The thesis is within the scope of the thesis proposal as previously approved and does not contain any material that is objectionable to NetApp. It is also approved for its technical content. It is understood that the actual thesis document will be the permanent property of M.I.T. and will be placed in the M.I.T. Library within one month after the date of submission. NetApp agrees that M.I.T. shall have the nonexclusive right to reproduce, publish, and distribute the thesis. ~ ~ ui company STL-VE MILLE[< &Er'KIoej T(-CH1NICAL. LiktrCiup& Design and Simulation of a PCI Express Gen 3.0 Communication Channel By Dilini Warnakulasuriyarachchi Submitted to the Department of Electrical Engineering and Computer Science May 21" 2010 In Partial Fulfillment of the Requirements of the Degree of Master of Engineering in Electrical Engineering ABSTRACT PCI Express (PCIe) is a serial interconnect technology, developed by the PCI-Sig organization, which provides high bandwidth data transmission with the added benefits of reduced board space requirements, smaller connectors and simplified PCB layouts. Since faster and faster data rates are more desirable, PCIe Gen 3.0 attempts to transmit data at 8GT/s. As part of the thesis work, an existing model of a PCIe channel which connects two controller boards over a backplane, was simulated and measured under PCIe Gen 2.0 speeds (5GT/s). The resulting data from these tests were used to provide the basis for improving the model to make it function under PCIe Gen 3.0 specifications. This was achieved by exploring new receiver equalization techniques and transmitter de-emphasis and board characteristics. An integrated circuit manufacturer's model was used as the base model for PCIe Gen 2.0. This model was further developed to simulate Gen 3.0 speeds. Simulation software tools such as HSPICE, Ansoft HFSS, Ansoft Via Wizard 3.0 and MATLAB were utilized. A simulation model of the system functioning under PCIe Gen 3.0 specifications was successfully developed by using CTLE equalization technique. MIT Thesis supervisor: Vladimir Stojanovic Associate Professor, Department of Electrical Engineering and Computer Studies Company Thesis Supervisor: Scott Westbrook Senior Member of the Technical Staff, NetApp Acknowledgement My sincere thanks to my faculty adviser at MIT, Prof. Vladimir Stojanovic for his willingness to supervise my thesis and for his willingness to answer my questions at all times regardless of the distance or time. Thank you for always being there for your students. I am grateful to Scott Westbrook, my VI-A company adviser who introduced me to the company and was always a great mentor. Your support and guidance were monumental in the completion of my thesis. Thanks to Mohammad Kermani at NetApp for sharing his knowledge with me and for patiently answering my questions. Many thanks to Steve Miller, Senior Technical Director at NetApp and my manager at NetApp Mr. Srikumar Chandran for their continuous support and guidance. I would like to thank Richard Ely and AdityaGiry Valluri at NetApp for encouraging me to build my own probes and their willingness to help me at all times. Last but not least, the friendship and alministrative support offered by Anne Hunter, Kathy Sullivan, Vera Sayzew, and Linda Sullivan are much appreciated. Table of Contents Page A bstract ................................................................................................. .. 02 A cknow ledgem ent...........................................................................................03 L ist of T ab les ................................................................................................ 06 L ist of F igures .......................................... ,.....................................................07 Chapters 1. Introduction ............................................................................................ 09 1.1. B ackground...................................................................................... 09 1.2. Motivation and Problem Statement .......................................................... 10 1.3 . O bjectiv es .......................................................................................... 1 1 2. Theoretical B asis ..................................................................................... 12 2.1. Differential Transmission Lines ............................................................. 13 2.2. Signal Integrity Issues ........................................................................... 14 2.3. Signal Quality Measurement ..................................................................... 16 2.4. Enhancement of Signal Quality ............................................................... 19 3. Technical Approach .................................................................................. 21 3.1. Integrated circuit manufacturer's HSPICE model ......................................... 21 3.2. Gen 2.0 trace and via models ................................................................. 23 3.3. Integration of HSPICE file with HFSS models ............................................. 26 3.4. Simulation of the new Gen 2.0 model .......................................................... 27 3.5. Identify changes to Gen 2.0 model for Gen 3.0 requirements ............................... 28 4 Page 3.6. Development of Gen 3.0 model ............................................................... 29 3.7. Simulation & evaluation of Gen 3.0 model .................................................... 32 4. R equired R esources .................................................................................. 34 4.1. Software Resources ............................................................................. 34 4.2. Hardware Resources ........................................................................... 35 4.3. Information Resources ......................................................................... 35 5. R esu lts ................................................................................................ 35 5.1. HFSS model analysis ........................................................................... 36 5.2. Gen 2.0 HSPICE simulation results .......................................................... 37 5.3. Gen 3.0 Transmitter De-emphasis and Receiver Equalization results ................... 39 6. D iscussion ............................................................................................ 45 7. Conclusion & Future Work ............................................................................ 48 8. R eferences .............................................................................................. 50 9. Appendix ............................................................................................. 52 List of Tables Page 1. Key features of PCIe Gen 2.0 and PCIe gen 3.0 ............................................ 11 2. Comparison of passive CTLE methods ...................................................... 20 3. V ia design specification ........................................................................... 24 4. Port impedance of HFSS simulation models................................................ 36 5. Values of the circuit elements of the CTLE filer ............................................ 41 6. Worst-case eye margin with the component tolerance ..................................... 41 List of Figures Page 1. PCIe channel via a backplane ..................................................................... 12 2. D ifferential Signaling .............................................................................. 13 3. Effect of cross-talk between channels ........................................................ 14 4. Insertion loss of a transmission line 100 mils in length .................................... 16 5. A sample eye diagram ........................................................................... 17 6. The eye template for Gen 2.0 PRBS analysis...................................................17 7. The eye template for Gen 3.0 .................................................................. 18 8. Decision Feedback
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