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Openrisc-Based System-On-Chip for Digital Signal Processing

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Openrisc-Based System-On-Chip for Digital Signal Processing OpenRISC-based System-on-Chip for Digital Signal Processing Alexander Lopez-Parrado´ Juan-Camilo Valderrama-Cuervo Electronics Engineering Program Envigado’s Traffic Light System Management Universidad del Quind´ıo Envigado, Antioquia, Colombia Armenia, Quind´ıo, Colombia e-mail: [email protected] e-mail: [email protected]. Abstract—This paper presents the design and implementation inspired from open source software models has been deployed of an OpenRISC-based System-on-Chip (SoC), which is composed since the last ten years. This model has been supported of hardware cores implementing the Digital Signal Processing by communities like OpenCores, which develops open (DSP) functions: Finite Impulse Response (FIR) filter, Infinite source hardware under the Lesser General Public License Impulse Response (IIR) filter and Fast Fourier Transform (FFT). (LGPL). OpenCores community has remarkable products The FIR-filter core is based on the transpose realization form, as the OpenRISC processor core [7] and the Wishbone bus the IIR-filter core is based on the Second Order Sections (SOS) architecture and the FFT core is based on the Radix specification [8], which jointly allow the development of SoC 22 Single Delay Feedback (R22SDF) architecture. The three hardware. However, OpenCores community lacks of fully cores are compatible with the Wishbone SoC bus, and they parameterizable DSP cores compatible with the Wishbone were described using generic and structural VHDL. In-system bus. By considering previous ideas, we developed cores FIR hardware verification was performed by using an OpenRisc-based filter, IIR filter and FFT under the LGPL license, which are SoC synthesized on an Altera FPGA. Tests showed that the compatible with the Wishbone bus and allow the development designed DSP cores are suitable for building SoC based on the of DSP-SoC based on the OpenRISC processor [9]. The OpenRisc processor and the Wishbone bus. FIR-filter core is based on the transpose architecture [1] [2], Keywords—Digital signal processing, digital filters, finite the IIR core is based on the SOS architecture [1] [2], and the impulse response filters, infinite impulse response filters, fast FFT core is based on the R22SDF architecture [10]. The three Fourier transforms, system-on-chip, open source hardware, open cores were described using generic and structural VHDL and RISC processor, Wishbone bus. targeted to an Altera FPGA device. This paper is organized as follows: First, section II describes some theoretical concepts I. INTRODUCTION about DSP and Wishbone bus, then section III presents the design of the DSP cores architecture and describes the ODAY’S technology uses heavily Digital Signal functional blocks, later the section IV shows the in-system T Processing (DSP) on its applications, and since the past hardware verification results, and finally the conclusion and 20 years [1] these applications have been growing up because the acknowledgements are presented. the performed improvements to digital integrated circuits in speed, integration capabilities and power consumption. II. THEORETICAL BACKGROUND The increased speed of integrated circuits allows real time processing of signals with higher bandwidths such as the This section presents some theoretical concepts about the ones used in communication systems [1]. Nowadays there are DSP functions that were implemented, and the SoC bus Digital Signal Processors (DSPs) devices specifically designed Wishbone. for DSP that perform real time filtering, Fourier transforms, Wavelet transforms, or encoding processes on audio and video A. FIR Filters signals. Nevertheless, the parallel nature of DSP algorithms FIR filters are discrete Linear Time Invariant (LTI) systems has motivated research interest to hardware solutions based that have a finite duration impulse response h[n]. Practical on reconfigurable targets such as the Field Programmable implementations of FIR filters are always stable because of Gate Arrays (FPGAs); these solutions have demonstrated their non-recursive nature. Eq. 1 shows the direct realization improvements in speed and power consumption compared of a FIR filter. with the DSPs-based ones [2]. There are several FPGA-based DSP solutions, which are developed by private corporations such as Altera and Xilinx. These solutions include FIR N−1 X filtering cores [3] [4], FFT cores [5] [6], among others; y[n] = h[k]x[n − k] (1) however these cores have expensive licenses for commercial k=0 use or they can be used for free only for academic purposes. Nonetheless, a new open source hardware development model Here, x[n] is the input signal, y[n] is the output signal and N is the length of the impulse response h[n]. There are several 978-1-4799-7666-9/14/$31.00 c 2014 IEEE 32 16 8 4 2 1 BF2 BF2I BF2 BF2I BF2 BF2I X[k] x[n] s t s s t s s t s I I I I I I . W2[n] W3[n] . clk . 5 4 3 2 1 0 . + + + Fig. 3. R22SDF architecture for 64-point FFT. Fig. 1. Transpose realization form for a FIR filter of length N. √ + N−1 X − i2πkn X[k] = x[n]e N (3) n=0 + According to the used radix, FFT algorithms can be radix-2, radix-4, radix-22, radix-8, mixed-radix, split-radix [2] 2 + [5] [6] [10], among others. The radix-2 algorithms have become popular for hardware implementations of the FFT Fig. 2. Transpose type II realization form for second order section. [5] [6] [10] due to their regularity, simple control, pipelined operation, and low hardware resources usage; the R22SDF architecture is based on a radix-22 algorithm and it is suitable realization forms for FIR filters [1]; in the case of hardware for FFT hardware [5] [6] [10] [11]. Fig. 3 shows the R22SDF implementations, the transpose form has the shortest critical architecture for a 64-point FFT. path and it is less sensitive to the round-off errors when fixed 2 point arithmetic is used [1] [2]. Fig. 1 shows the transpose The R2 SDF architecture uses two types of butterflies, which have a similar structure to the radix-2 butterfly, the realization form for a FIR filter with impulse response of length 2 N. R2 SDF architecture has a resource usage similar to the radix-4 algorithms [10]. From Fig. 3 it can be seen that control is performed by a log (N)-bit counter. B. IIR Filters 2 IIR filters are discrete Linear Time Invariant (LTI) systems D. OpenRISC processor and the Wishbone bus that have an infinite duration impulse response. Practical OpenRISC is a Reduced Instruction Set Computer (RISC) implementations of IIR filters can become unstable because 32-bit soft-core processor designed by OpenCores community, of their recursive nature [1]. Eq. 2 shows the direct realization its architecture is described in a standard document [7]; also of a (P − 1)-th order IIR filter. a synthesizable description in Verilog under the LGPL license is available through the OR1200 core [12]. OpenRISC allows P −1 P −1 the development of SOCs by using the interconnection bus X X Wishbone which is described in a standard document [8]. y[n] = bkx[n − k] − aky[n − k] (2) k=0 k=1 Before our project [9], the OpenCores community had not developed DSP cores with Wishbone connectivity, thus Here, bk is the coefficients set for the non-recursive part, the DSP cores proposed in this paper are the first ones ak is the coefficients set for the recursive part, x[n] is the Wishbone compatible, and they use the basic connection input signal, and y[n] is the output signal. There are several depicted in Fig. 4. The OpenCores community has developed realization forms for IIR filters [1]; the transpose type II form some reference SoCs based on the OpenRISC processor which has the shortest critical path and the SOS form is less sensitive are FPGA-synthesizable; one of the simplest is MinSoC to the round-off errors when fixed point arithmetic is used [13], which allows an easy and fast verification of the [1] [2]. In the case of hardware implementations the SOS OpenRISC-based SoC with custom slave modules such as the form has good stability for high order filters, and the critical DSP cores we designed. path is minimized by using the transpose type II form for each second-order section. Fig. 2 shows the transpose type II III. DSP CORES ARCHITECTURE realization form for a single second-order section. In this section we describe the designed DSP cores and Here, Nsect is the number of second-order sections and G the slave interfaces with the Wishbone bus. For all DSP cores is the total gain after the SOS decompositionp [1], thus each we used fixed point arithmetic, where the word length, guard N second-order section has a gain of sect G. The whole IIR bit, fractional part [2], filter order, and FFT length [1] are filter is composed by a cascade of Nsect second-order sections parameterizable features through VHDL generics. Each DSP as the shown in Fig. 2. core was designed using the two-unit structure shown in Fig. 4. C. Fast Fourier Transform The processing unit performs the DSP operation according The FFT is an algorithm that efficiently computes the to the specific core, and the slave interface unit is the Wishbone Discrete Fourier Transform (DFT) of a discrete time signal interface for the SoC connection. The interface lines are named [1] [2]. The DFT of a signal x[n] is shown in Eq. 3 according to the Wishbone bus standard [8]. DSP Core writes the number of used sections minus one from the Nsect sDATi[31:0] available sections; IIR GAIN is a write-p only register; in sDATo[31:0] N sADRi[31:0] sect sSTBi this address, the user writes the gain G for each SOS sWEi Slave Processing sACKo interface unit by using fixed- point representation with Q fractional bits.
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