View the Latest Agenda in the Mobile App

View the latest agenda in the mobile app

Monday, May 6

12:00 Registration Opens

12:00 - 13:30 Light Lunch Buffet and Designer Expo

Full-Flow Digital Design and Signoff Custom IC Design and Verification Mixed-Signal and Advanced Methodologies SoC Design and Verification Signal and Power Integrity Analysis Automotive and IP Solutions Academic Room Ammersee II Room Ammersee I Room Alpsee Room Chiemsee Room Bodensee I Room Schliersee Room Pilsensee

DSG01 CUS01 MS01 SVG01 ASIP01 AC01 The Challenge of Designing a “First-Time-Right” Wi-Fi PVS Voltage Aware DRC Using PVL Tcl DFM PROPERTY Experiences in OpenAccess Interoperability with Virtuoso Full-Chip System-on-Chip Emulation Using Palladium Z1 Automotive System Enablement Updated Cadence 2019 Portfolio Available for European HaLow Baseband in Less than Six Months Advance Commands and Innovus Solutions for Mixed-Signal Designs Emulation Ecosystem Cadence Academics via Europractice 13:30-14:00 Methods2Business TowerJazz Infineon Technologies Dream Chip Technologies GmbH Science and Technology Facilities Council

DSG02 CUS02 MS02 SVG02 ASIP02 AC02 I2C PAD Characterization Methodology Using Liberate A New Methodology for Active Substrate Parasitic Fast Implementation of Small Digital Blocks Within a Hybrid Virtual + Emulation SoC Platform for SW-Drivers Addressing the State of Safety and Security in Today’s Lead Institution for Analog Design Automation: New 14:00-14:30 Characterization Extraction in Automotive HV-CMOS Processes Custom Layout Environment Validation WKSH1 Autonomous Vehicles System Designs Thoughts in EDA for Analog Dialog Semiconductor X-FAB Semiconductor Foundries GmbH ams AG Intel-Mobileye How to Perform Power Integrity Analysis of a Motor Control Green Hills Software Reutlingen University - Robert Bosch Center for Unit by Combining Sigrity and PSpice Technology Power Electronics Cadence FlowCAD DSG03 CUS03 MS03 SVG03 ASIP03 AC03 Leveraging IJTAG for a Complex Mixed-Signal Design Precise Layout Area Estimation of Analog/Mixed-Signal Automated DfM Optimization Using Pattern Matching in Fast Processor Models for Software Bring Up and Hardware- A Configurable Fault-Tolerant Multicore System Based on IC Layout Automation with Self-Organized Wiring and 14:30-15:00 Kandou Bus S.A Circuits Virtuoso and Innovus Solutions Software Co-Verification Tensilica Fusion G3 DSPs Arrangement of Responsive Modules (SWARM) STMicroelectronics NXP Semiconductors Imperas Software IHP Reutlingen University

DSG04 CUS04 MS04 SVG04 ASIP04 AC04 RTL-Based Power Calculation with Joules RTL Power Interactive Resistance Measurement for Hierarchical Design Flow and Technology Demonstrator for 60GHz WiGig Dynamic Software Analysis in Virtual Platforms A Tool to Ease Design-Space-Exploration Using the SPAM - A SKILL Package Management System 15:00-15:30 Solution Layout Nets Antenna Array on Package Ericsson Tensilica LX7 ASIP Reutlingen University VSORA NXP Semiconductors GLOBALFOUNDRIES Ruhr-Universität Bochum

15:30-16:00 Coffee Break

DSG05 CUS05 MS05 SVG05 ASIP05 AC05 Conformal Smart LEC Results on ST ADG Devices Design Intent - A Path Towards Better Communication EM_ICT Enhancements for RF Qualification Modem Baseband SoC Architecture Exploration and Power-Efficient AI Processors for Perception and Decision- Lead Institution for Embedded Systems Design and Within IC Design Teams Validation in the SAVE Framework Making in Autonomous Vehicles Verification: Development of Adaptive Dependable and 16:00-16:30 STMicroelectronics GLOBALFOUNDRIES Robert Bosch GmbH Intel Cadence Robust Systems Brandenburg University of Technology (BTU) Cottbus – Senftenberg

DSG06 CUS06 MS06 SVG06 ASIP06 AC06 Improving Leakage and Dynamic Power of High- Fast Design and Reuse of Analog IP Using Intelligent IP Quality Assurance in the Verification of Power Grid of PSS - Automotive Case Study AI Inference at the Edge – The Realities of Hardware and PSS: Gearing Up for Large-Signal Simulation 16:30-17:00 Performance Arm Cortex-A76 Core Using Cadence Solutions Generators and Virtuoso Technology X-FAB’s Memory Compilers with Voltus-Fi Flow Infineon Technologies WKSH1 Cont’d Software Integration Ghent University - imec Arm Fraunhofer IIS/EAS X-FAB Semiconductor Foundries GmbH How to Perform Power Integrity Analysis of a Motor Control Cadence Unit by Combining Sigrity and PSpice Technology DSG07 CUS07 MS07 SVG07 Cadence FlowCAD ASIP07 AC07 Accelerating Timing Closure Using In-Design Track-Based RF Simulation Techniques for Analog Circuits Visualize and Prevent EM Effects in Automotive Designs Using Perspec System Verifier in the IP Verification of the Real-Time LED Flicker Mitigation on a Tensilica Vision DSP Application of Cell-Aware Test on an Advanced 3nm CMOS 17:00-17:30 Metal Fill with Innovus Implementation System Dialog Semiconductor Using Voltus-Fi Custom Power Integrity Solution Aurix2G RADAR Signal Processing Unit for Digital Side Mirror Systems Standard-Cell Library STMicroelectronics Melexis Infineon Technologies Leibniz University Hannover imec

DSG08 CUS08 MS08 SVG08 ASIP08 AC08 17:30-18:00 M1 vs Poly Pitch: Gear Ratio Change Optimizing Spectre APS Transient Speed and Convergence Printer Application IC - Analog on Top Flow with LVDS TOP-Level Verification Challenges for Interconnect and Mixed-Signal Analysis and Verification to Meet ISO 26262 MEMS-IC Yield Optimization with Electrical and Mechanical imec Texas Instruments Signal Balancing Through EAD Closing the Gap Using IWB/IVD Safety Requirements Process Parameters STMicroelectronics Ericsson Texas Instruments Technical University of Munich

18:00-20:00 Networking Buffet and Designer Expo

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Tuesday, May 7

07:30-08:45 Welcome Coffee and Registration Keynotes 8:45-10:00 Tom Beckley: Senior Vice President and General Manager, Custom IC & PCB Group, Cadence Hans Adlkofer, Vice President Automotive System Group, Infineon Technologies 10:00-10:30 Coffee Break

Mixed-Signal and Advanced PCB Design and Analysis Full-Flow Digital Design and Signoff Custom IC Design and Verification SoC Design and Verification Multi-Fabric Design and Analysis Automotive and IP Academic Methodologies (German/Deutsch) Special Sessions Room Ammersee II Room Ammersee I Room Chiemsee Room Bodensee I Room Schliersee Room Pilsensee Room Alpsee Room Bodensee II

CUS09 MS09 SVG09 SPB01 PCB01 ASIP09 AC09 Verification of High-Level Design Real-Number Modeling of Loading Effects in Formal Verification Signoff for Digital IP: A Cross-Fabric Design Planning and What’s New im PCB Flow (Front End) 112G SerDes for 400G/800G Networking Lead Institution for System-Level Design: 10:30-11:00 Requirements with Virtuoso ADE Verifier Power Regulation Using SV EEnet Comparison Between Classical UVM Versus Optimization, Taking into Account the FlowCAD TSMC and Cadence Heterogeneous Runtime Adaptive Multicore ams AG Texas Instruments Formal Based Package Routing Strategy Architectures for Autonomous Systems CL01 STMicroelectronics STMicroelectronics Technical University Dresden Cadence Cloud/The Future of Electronic Design Automation DSG09 CUS10 MS10 SVG10 SPB02 PCB02 AC10 Cadence New Technology Innovations in the Cadence Implementing a Grid-Based Design UVM ATE Tester Probe UVC for Top-Level A Comprehensive and Reusable Strategy Checking the Connectivity Between What’s New im PCB Flow (Back End) Formal Verification with Broad-Spectrum Room Eibsee 11:00-11:30 Digital Flow Methodology to “Design Out” the Impacts of Mixed-Signal Verification to Verify Cores Based on UVM and Formal Design Fabrics FlowCAD ANSI-C Reference Specifications Cadence Shrinking Nodes Texas Instruments Verification STMicroelectronics University of Oxford IC Mask Design STMicroelectronics

MS11 SVG11 SPB03 PCB03 ASIP11 AC11 Chip-Level Verification of RF-AMS SoCs Formal Verification in the Context of Highly Virtuoso Platform as a Common Layout System Design CNN Design Space Exploration on Tensilica Master Thesis Contest Winner: Automated 11:30-12:00 Innowicom System Solutions AB Configurable IPs Design Environment for Chip/Package/ FlowCAD Vision P6 DSP Design Space Exploration of Digital Audio Texas Instruments PCB Co-Design Leibniz University Hannover Processors for Hearing Aids CL02 CUS11 Infineon Technologies Leibniz University Hannover Cloud-Based Innovation for Semiconductor Technology Overview Design DSG10 Cadence MS12 SVG12 SPB04 PCB04 ASIP12 AC12 Amazon Web Services Mixed Placer: An Unconventional Paradigm Path-Based Timing Verification Flow for Accelerate DFT Simulations with Xcelium Applying Team Design and DFM Checking to Unternehmensweites PCB-Daten- Multiframe Imaging on Tensilica Vision Synthesis and Test of IP-Blocks with Fault Room Eibsee 12:00-12:30 for Hard Macro-Intensive Designs Full-Custom Circuits Multi-Core Technology IC Package and SiP Management P6 DSP Mitigation STMicroelectronics IBM STMicroelectronics Cadence FlowCAD Visidon Saint Petersburg State University of Aerospace Instrumentation (SUAI)

12:30-13:30 Lunch and Designer Expo

DSG11 CUS12 MS13 SVG13 SPB05 PCB05 ASIP13 AC13 WOM01 Designing a 7nm Multi-Core Arm Legato Reliability Fault Simulation - An Technology Overview High-Level Synthesis Models in Pre-Silicon Implementation of Complex Packaging Integrierte Neue Design Checks A Low-Power Tensilica Fusion F1 DSP and Lead Institution: University of Lübeck 12% Is Not Enough, Changing Industry to 13:30-14:00 Neoverse-N1 System on Chip Using Cadence Automotive Safety Case Study Cadence Verification Design Rules and Layout Optimization Using FlowCAD Low-Voltage SRAMs Achieving 400MHz University of Lübeck Support Women in Engineering Implementation Flow and IP Melexis Intel RAVEL Algorithms in Cadence SiP at 600mV Women’s Engineering Society Arm STMicroelectronics Xenergic Room Walchensee

DSG12 CUS13 MS14 SVG14 SPB06 PCB06 ASIP14 AC14 WOM02 How to Improve TAT and PPA by Using Reliability Analysis Results Parsing Flow Implementing Checks for Power Domain Accelerating Verification of RF Chips for 5G 25Gbps Simulations with Sigrity 2018 Integrierte Design Analyse Case Study: Design Methodology Reliability, Security and Quality in Interactive Session: Breaking the Mould 14:00-14:30 Design Metrics Xilinx Crossings on Schematic Level Infineon Technologies Release FlowCAD for Optimized GPS IP Solution Using Nanoelectronic Systems – Update from Women’s Engineering Society Socionext Europe GmbH RacyICs Grass Valley Tensilica DSP Cadence Early Stage Researchers Room Walchensee Nestwave Cadence

DSG13 CUS14 MS15 SVG15 SPB07 PCB07 ASIP15 AC15 Challenges in Digital Implementation of a Degradation Model Creation Flow DARE SET Simulation Flow Integrated in A Python Client Library for vManager API Electrical/Thermal Co-Simulation of SMPS Full Wave 3D Simulations Smart Hearing Aid Processor with Ultra-Low Master Thesis Contest Winner: Procedural Huge Sensor Array Design with High-Speed Fraunhofer IIS Virtuoso Analog Design Environment EXTOLL GmbH High Current Density PCB Design FlowCAD Power Consumption Capacitor Placement and Routing in Charge SerDes Interface Redistribution ADCs with Generalised 14:30-15:00 imec Infineon Technologies Dream Chip Technologies GmbH Fraunhofer IIS Capacitor Ratios by Nonlinearity Analysis Considering Parasitics Technical University of Munich/Infineon Technologies

15:00-15:30 Coffee Break

Tuesday, May 7

15:00-15:30 Coffee Break

PCB Design and Analysis Full-Flow Digital Design and Signoff Custom IC Design and Verification Mixed-Signal and Advanced Methodologies SoC Design and Verification Signal and Power Integrity Analysis Automotive and IP Academic (German/Deutsch) Room Ammersee II Room Ammersee I Room Alpsee Room Chiemsee Bodensee I Room Schliersee Room Pilsensee Room Bodensee II

DSG14 CUS-Demo I MS-Demo I SVG16 SPB08 PCB08 ASIP16 AC16 A Flow for Early Power Analysis Using Joules and Getting the Most Out of Virtuoso ADE in Virtuoso Best Companions: vManager Platform and Virtuoso Technology Overview SI/PI/EMC Full System Simulation of Complex Tester Starrflex (Rigid Flex) Technologie Advanced Memories: Design Decisions for Advanced Workshop: Rapid UVM-e Testbench Generation 15:30-16:00 Voltus Solutions 18.1 Release ADE Verifier - Leading-Edge Technology and Cadence PCB Boards (40 Layers) MLO, Contact Unit and IC Würth Elektronik GmbH & Co. KG Memory Interfaces Cadence Analog Devices Cadence Methodology for Mixed-Signal Verification Closure NXP Semiconductors Arm and Cadence Cadence

DSG15 CUS-Demo II SPB09 PCB09 ASIP17 Die/Package Co-Design in 28FDOI Technology Using Advanced Methodologies in Virtuoso 18.1 Release: Introducing a 5G Reference Design Starrflex (Rigid Flex) Technologie (Live Demo) Implementing LPDDR5 Controller and PHY for 16:00-16:30 Voltus-Sigrity Package Analysis Concurrent Layout Editing, Design Planner, Cadence FlowCAD Mobile, Automotive, and Computing Applications STMicroelectronics Simulation-Driven Routing Cadence Cadence

DSG-Demo I CUS-Demo III MS-Demo II SVG17 SPB10 PCB10 ASIP18 AC17 Smart Digital Implementation Using Innovus Addressing Complex Low-Power Design and Spectre AMS Designer Flex Use Model Reduces SoC Emulation Automation Workflow: Your Way True 3D Analysis on Large Geometries with Embedded Components Enabling High-Performance Computing Applications New Stars on the Horizon – Innovative Startups 16:30-17:00 Machine Learning Verification Challenges Using Virtuoso Power Manager Verification Time to Success Clarity 3D Solver AT&S Deutschland GmbH with Differentiated IP and Bleeding-Edge Showcase Their Vision Cadence Cadence Cadence Arm Cadence Semiconductor Processes Xenergic, MAGICS, and aiCTX Samsung

DSG-Demo II CUS-Demo IV MS-Demo III SPB11 PCB11 ASIP19 Bus Guides and Timing Closure with Innovus Legato Reliability Solution Analog and Mixed-Signal Functional Safety Flow Through vManager Metric-Driven Signoff Platform Avoid Unnecessary Iterations with Your Embedded Components (Live Demo) IP Portfolios for Automotive and High-Performance High-Frequency Router Manufacturing Partner – A New Approach to Computing Designs 17:00-17:30 Cadence Cadence FlowCAD Cadence Reducing or Eliminating TQs and Accelerating Your Cadence New Product Introduction Multek, A DSBJ Company

17:30-18:30 Designer Expo

18:30-20:00 Dinner and Best Presentation Awards

20:00-23:00 Evening Event

Wednesday, May 8

08:00-08:30 Welcome Coffee and Designer Expo

Full-Flow Digital Design and Signoff Custom IC Design and Verification Mixed-Signal and Advanced Methodologies MCAD-ECAD SoC Design and Verification Room Ammersee II Room Ammersee I Room Alpsee Room Bodensee I Room Chiemsee

CUS-Techtorial I MS-Techtorial I 08:30-09:00 High Performance Global Remote Access to Cadence EDA Software Managing AMS Designs for Successful Tapeouts OpenText ClioSoft DSG-Techtorial I IR Drop Analysis and Optimization in Innovus Implementation System 09:00-09:30 Cadence CUS-Techtorial II MS-Techtorial II Virtuoso RF Solution: A Comprehensive RF Flow for IC, Package, and Module Design WKSH2 SVG-Techtorial Using SystemVerilog EEnet to Model Complex Electrical Networks Cadence Library Part Creation Do More with Less – Optimizing Your Throughput Cadence 09:30-10:00 FlowCAD Cadence

CUS-Techtorial III MS-Techtorial III DSG-Techtorial II Design of a Photonic Lidar Module in a New Unified Electronics-Photonic Design Environment Advanced MS Verification of Multi-Disciplinary Systems with SV UDN-2-UDN/ 10:00-10:30 Genus and Modus Solutions: Deep Dive into Hierarchical Test Lumerical and Cadence Logic/Real Cadence Cadence

10:30-11:00 Coffee Break and Designer Expo

MS-Techtorial IV Using Quantus SmartView to Accelerate Post-Layout Analysis of Parasitics and 11:00-11:30 CUS-Techtorial IV Electromigration (EM) DSG-Techtorial III Writing Good SKILL Code Cadence Genus and Innovus Solutions: Physical Flows for Best PPA and Predictability Cadence Cadence MS-Techtorial V 11:30-12:00 Electrostatic Discharge (ESD) Analysis with Voltus-Fi Custom Power Integrity Solution Cadence WKSH2 Library Part Creation CUS-Techtorial V MS-Techtorial VI FlowCAD 12:00-12:30 Custom Silicon Design Automation with Cadence PCell Designer Accelerated Design, Migration, and Substrate Coupling for Analog Design Robert Bosch GmbH Intento Design DSG-Techtorial IV IP...The Challenge of the Deliverables Cadence CUS-Techtorial VI MS-Techtorial VII Cadence Cloud: A Secure and Flexible Solution to Enable Engineering Productivity Tame Your Analog Mixed-Signal Challenges Through Next-Generation Tools from 12:30-13:00 and Accelerate Time to Market MathWorks and Cadence Cadence MathWorks

13:00-14:30 Lunch and Designer Expo