UART Controller 21 2014.08.18

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The hard processor system (HPS) provides two UART controllers for asynchronous serial communication. The UART controllers are based on an industry standard 16550 UART controller. The UART controllers are instances of the Synopsys® DesignWare® APB Universal Asynchronous Receiver/Transmitter (DW_apb_uart) peripheral.(1)

UART Controller Features The UART controller provides the following functionality and features: • Programmable character properties, such as number of data bits per character, optional parity bits, and number of stop bits † • Line break generation and detection † • DMA controller handshaking interface • Prioritized interrupt identification † • Programmable baud rate • False start bit detection † • Automatic flow control mode per 16750 standard † • Internal loopback mode support • 128-byte transmit and receive FIFO buffers • FIFO buffer status registers † • FIFO buffer access mode (for FIFO buffer testing) enables write of receive FIFO buffer by master and read of transmit FIFO buffer by master † • Shadow registers reduce software overhead and provide programmable reset † • Transmitter holding register empty (THRE) interrupt mode † • Separate thresholds for DMA request and handshake signals to maximize throughput

(1) Portions © 2014 Synopsys, Inc. Used with permission. All rights reserved. Synopsys & DesignWare are registered trademarks of Synopsys, Inc. All documentation is provided "as is" and without any warranty. Synopsys expressly disclaims any and all warranties, express, implied, or otherwise, including the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, and any warranties arising out of a course of dealing or usage of trade. †Paragraphs marked with the dagger (†) symbol are Synopsys Proprietary. Used with permission.

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101 Innovation Drive, San Jose, CA 95134 a10_54021 21-2 UART Controller Block Diagram and System Integration 2014.08.18

UART Controller Block Diagram and System Integration Figure 21-1: UART Block Diagram

UART Controller Serial Transmitter/ Interrupt and System MPU Receiver Reset Control IRQ Baud Clock To I/O FIFO Buffer Pins RX Generator DMA TX DMA Controller RTS Interface CTS

Clock Register Block Manager

Reset Slave Interface Manager

L4 Peripheral Bus

Table 21-1: UART Controller Block Descriptions

Block Description

Slave interface Slave interface between the component and L4 peripheral bus.

Register block Provides main UART control, status, and interrupt generation functions.†

FIFO buffer Provides FIFO buffer control and storage. †

Baud clock generator Generates the transmitter and receiver baud clock. With a reference clock of 100 MHz, the UART controller supports transfer rates of 95 baud to 6.25 Mbaud. This supports communication with all known 16550 devices. The baud rate is controlled by programming the interrupt enable or divisor latch high (IER_DLH) and receive buffer, transmit holding, or divisor latch low (RBR_THR_DLL) registers.

Serial transmitter Converts parallel data written to the UART into serial data and adds all additional bits, as specified by the control register, for transmission. This makeup of serial data, referred to as a character, exits the block in serial UART. †

Serial receiver Converts the serial data character (as specified by the control register) received in the UART format to parallel form. Parity error detection, framing error detection and line break detection is carried out in this block. †

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Send Feedback a10_54021 2014.08.18 Functional Description of the UART Controller 21-3

Block Description

DMA interface The UART controller includes a DMA controller interface to indicate when received data is available or when the transmit FIFO buffer requires data. The DMA requires two channels, one for transmit and one for receive. The UART controller supports single and burst transfers. You can use DMA in FIFO buffer and non-FIFO buffer mode.

Related Information DMA Controller For more information, refer to the DMA Controller chapter in the Hard Processor System Technical Reference Manual.

Functional Description of the UART Controller The HPS UART is based on an industry-standard 16550 UART. The UART supports serial communication with a peripheral, modem (data carrier equipment), or data set. The master (CPU) writes data over the slave bus to the UART. The UART converts the data to serial format and transmits to the destination device. The UART also receives serial data and stores it for the master (CPU). † The UART’s registers control the character length, baud rate, parity generation and checking, and interrupt generation. The UART’s single interrupt output signal is supported by several prioritized interrupt types that trigger assertion. You can separately enable or disable each of the interrupt types with the control registers. † FIFO Buffer Support The UART controller includes 128-byte FIFO buffers to buffer transmit and receive data. FIFO buffer access mode allows the master to write the receive FIFO buffer and to read the transmit FIFO buffer for test purposes. FIFO buffer access mode is enabled with the FIFO access register (FAR). Once enabled, the control portions of the transmit and receive FIFO buffers are reset and the FIFO buffers are treated as empty. † When FIFO buffer access mode is enabled, you can write data to the transmit FIFO buffer as normal; however, no serial transmission occurs in this mode and no data leaves the FIFO buffer. You can read back the data that is written to the transmit FIFO buffer with the transmit FIFO read (TFR) register. The TFR register provides the current data at the top of the transmit FIFO buffer. † Similarly, you can also read data from the receive FIFO buffer in FIFO buffer access mode. Since the normal operation of the UART is halted in this mode, you must write data to the receive FIFO buffer to read it back. The receive FIFO write (RFW) register writes data to the receive FIFO buffer. The upper two bits of the 10- bit register write framing errors and parity error detection information to the receive FIFO buffer. Bit 9 of RFW indicates a framing error and bit 8 of RFW indicates a parity error. Although you cannot read these bits back from the receive buffer register, you can check the bits by reading the line status register (LSR), and by checking the corresponding bits when the data in question is at the top of the receive FIFO buffer. † UART(RS232) Serial Protocol Because the serial communication between the UART controller and the selected device is asynchronous, additional bits (start and stop) are added to the serial data to indicate the beginning and end. Utilizing these bits allows two devices to be synchronized. This structure of serial data accompanied by start and stop bits is referred to as a character, as shown in below.†

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Send Feedback a10_54021 21-4 Automatic Flow Control 2014.08.18 Figure 21-2: Serial Data Format

Bit Time

Serial Data Start Data Bits 5 - 8 Parity Stop Bits 1, 1.5, 2

One Character

An additional parity bit may be added to the serial character. This bit appears after the last data bit and before the stop bit(s) in the character structure to provide the UART controller with the ability to perform simple error checking on the received data.† The Control Register is used to control the serial character characteristics. The individual bits of the data word are sent after the start bit, starting with the least- significant bit (LSB). These are followed by the optional parity bit, followed by the stop bit(s), which can be 1, 1.5 or 2.† All the bits in the transmission (with exception to the half stop bit when 1.5 stop bits are used) are transmitted for exactly the same time duration. This is referred to as a Bit Period or Bit Time. One Bit Time equals 16 baud clocks. To ensure stability on the line, the receiver samples the serial input data at approximately the midpoint of the Bit Time once the start bit has been detected. Because the exact number of baud clocks that each bit transmission is known, calculating the midpoint for sampling is not difficult. That is, every 16 baud clocks after the midpoint sample of the start bit.† Together with serial input debouncing, this feature also contributes to avoid the detection of false start bits. Short glitches are filtered out by debouncing, and no transition is detected on the line. If a glitch is wide enough to avoid filtering by debouncing, a falling edge is detected. However, a start bit is detected only if the line is sampled low again after half a bit time has elapsed. † Figure 21-3: Receiver Serial Data Sample Points

Serial Data In Start Data Bit 0 (LSB) Data Bit 1

8 16 16

The baud rate of the UART controller is controlled by the serial clock and the Divisor Latch Register ( DLH and DLL ).† Automatic Flow Control The UART includes 16750-compatible request-to-send (RTS) and clear-to-send (CTS) serial data automatic flow control mode. You enable automatic flow control with the modem control register (MCR.AFCE). †

RTC Flow Control Trigger RTC is an RX FIFO Almost-Full Trigger, where "almost full" refer to two available slots in the FIFO The UART controller uses two separate trigger levels for a DMA request and handshake signal (rts_n) in order to maximize throughput on the interface.

Automatic RTS mode Automatic RTS mode becomes active when the following conditions occur: † • RTS (MCR.RTS bit and MCR.AFCE bit are both set)

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Send Feedback a10_54021 2014.08.18 Automatic CTS mode 21-5 • FIFO buffers are enabled (FCR.FIFOE bit is set) With automatic RTS enabled, the rts_n output pin is forced inactive (high) when the FIFO is almost full; where "almost full" refers to two available slots in the FIFO. When rts_n is connected to the cts_n input pin of another UART device, the other UART stops sending serial data until the receive FIFO buffer has available space (until it is completely empty). † The selectable receive FIFO buffer threshold values are 1, ¼, ½, and 2 less than full. Because one additional character may be transmitted to the UART after rts_n is inactive (due to data already having entered the transmitter block in the other UART), setting the threshold to 2 less than full allows maximum use of the FIFO buffer with a margin of one character. † Once the receive FIFO buffer is completely emptied by reading the receiver buffer register (RBR_THR_DLL), rts_n again becomes active (low), signaling the other UART to continue sending data.† Even when you set the correct MCR bits, if the FIFO buffers are disabled through FCR.FIFOE, automatic flow control is also disabled. When auto RTS is not implemented or disabled, rts_n is controlled solely by MCR.RTS. In the Automatic RTS Timing diagram, the character T is received because rts_n is not detected prior to the next character entering the sending UART transmitter. † Figure 21-4: Automatic RTS Timing

sin start character T stop start character T+1 stop

rts_n

1 2 3 T T+1 rx_fifo_read

Automatic CTS mode Automatic CTS mode becomes active when the following conditions occur: † • AFCE (MCR.AFCE bit is set) • FIFO buffers are enabled (through FIFO buffer control register IIR_FCR.FIFOE) bit When automatic CTS is enabled (active), the UART transmitter is disabled whenever the cts_n input becomes inactive (high). This prevents overflowing the FIFO buffer of the receiving UART. † If the cts_n input is not deactivated before the middle of the last stop bit, another character is transmitted before the transmitter is disabled. While the transmitter is disabled, you can continue to write and even overflow to the transmit FIFO buffer. † Automatic CTS mode requires the following sequence: 1. The UART status register are read to verify that the transmit FIFO buffer is full (UART status register USR.TFNF set to zero). † 2. The current FIFO buffer level is read via the transmit FIFO level (TFL) register. † 3. Programmable THRE interrupt mode must be enabled to access the FIFO buffer full status from the LSR. † When using the FIFO buffer full status, software can poll this before each write to the transmit FIFO buffer. When the cts_n input becomes active (low) again, transmission resumes. If the FIFO buffers are disabled with the FCR.FIFOE bit, automatic flow control is also disabled regardless of any other settings. When auto CTS is not implemented or disabled, the transmitter is unaffected by cts_n.†

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Send Feedback a10_54021 21-6 Interface Pins 2014.08.18 Figure 21-5: Automatic CTS Timing

sout start data bits stop start data bits stop start data bits stop

Disabled cts_n

Interface Pins

Table 21-2: Interface Pins

Pin Width Direction Description

RX 1 bit Input Serial Input

TX 1 bit Output Serial Output

CTS 1 bit Input Clear to send

RTS 1 bit Output Request to send

FPGA Routing

Table 21-3: Signals for FPGA Routing

Signal Width Direction Description

uart_rxd 1 bit Input Serial input

uart_txd 1 bit Output Serial output

uart_cts 1 bit Input Clear to send

uart_rts 1 bit Output Request to send

uart_dsr 1 bit Input Data set ready

uart_dcd 1 bit Input Data carrier detect

uart_ri 1 bit Input Ring indicator

uart_dtr 1 bit Output Data terminal ready

uart_out1_n 1 bit Output User defined output 1

uart_out2_n 1 bit Output User defined output 2

Clocks The UART controller is connected to the l4_sp_clk clock. The clock input is driven by the clock manager.

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Send Feedback a10_54021 2014.08.18 Resets 21-7 Related Information Clock Manager For more information, refer to the Clock Manager chapter in the Hard Processor System Technical Reference Manual.

Resets The UART controller is connected to the uart_rst_n reset signal. The reset manager drives the signal on a cold or warm reset.

Related Information Reset Manager For more information, refer to the Reset Manager chapter in the Hard Processor System Technical Reference Manual.

Interrupts The assertion of the UART interrupt output signal occurs when one of the following interrupt types are enabled and active: † Table 21-4: Interrupt Types and Priority †

Interrupt Type Priority Source Interrupt Reset Control

Receiver line Highest Overrun, parity and framing errors, break Reading the line status status condition. Register.

Received data Second Receiver data available (FIFOs disabled) Reading the receiver buffer available or RCVR FIFO trigger level reached register (FIFOs disabled) (FIFOs enabled). or the FIFO drops below the trigger level (FIFOs enabled)

Character Second No characters in or out of the Receive Reading the receiver buffer timeout FIFO during the last 4 character times Register. indication and there is at least 1 character in it during this Time.

Transmit Third Transmitter holding register empty Reading the IIR register holding register (Programmable THRE Mode disabled) (if source of interrupt); or, empty or Transmit FIFO at or below threshold writing into THR (FIFOs or (Programmable THRE Mode enabled). Programmable THRE Mode not enabled) or Transmit FIFO above threshold (FIFOs and Programmable THRE Mode enabled).

Modem Status Fourth Clear to send or data set ready or ring Reading the Modem status indicator or data carrier detect. If auto Register. flow control mode is enabled, a change in CTS (that is, DCTS set) does not cause an interrupt.

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Send Feedback a10_54021 21-8 Programmable THRE Interrupt 2014.08.18 You can enable the interrupt types with the interrupt enable register (IER_DLH). Note: Received Data Available" and "Character Timeout Indication" are enabled by a single bit in the IER_DLH register, because they have the same priority.

Once an interrupt is signaled, you can determine the interrupt source by reading the Interrupt Identity Register (IIR).

Programmable THRE Interrupt The UART has a programmable THRE interrupt mode to increase system performance. You enable the programmable THRE interrupt mode with the interrupt enable register (IER_DLH.PTIME). When the THRE mode is enabled, THRE interrupts and the dma_tx_req signal are active at and below a programmed transmit FIFO buffer empty threshold level, as shown in the flowchart. † Figure 21-6: Programmable THRE Interrupt

Clear INTR

FIFO Level > TX yes Empty Trigger?

no

THRE Interrupt no Enabled?

yes

Set INTR

FIFO Level > TX no Empty Trigger?

yes

The threshold level is programmed into FCR.TET. The available empty thresholds are empty, 2, ¼, and ½. The optimum threshold value depends on the system's ability to begin a new transmission sequence in a timely manner. However, one of these thresholds should prove optimum in increasing system performance by preventing the transmit FIFO buffer from running empty. In addition to the interrupt change, line status register (LSR.THRE) also switches from indicating that the transmit FIFO buffer is empty, to indicating that the FIFO buffer is full. This change allows software to fill the FIFO buffer for each transmit sequence by polling LSR.THRE before writing another character. This directs the UART to fill the transmit FIFO buffer whenever an interrupt occurs and there is data to transmit, instead of waiting until the FIFO buffer is completely empty. Waiting until the FIFO buffer is empty reduces

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Send Feedback a10_54021 2014.08.18 DMA Controller Operation 21-9 performance whenever the system is too busy to respond immediately. You can increase system efficiency when this mode is enabled in combination with automatic flow control. When not selected or disabled, THRE interrupts and LSR.THRE function normally, reflecting an empty THR or FIFO buffer. Figure 21-7: Interrupt Generation without Programmable THRE Interrupt Mode

Clear INTR

TX FIFO no Empty?

yes

THRE no Interrupt Enabled?

yes

Set INTR (INTR Is Asserted If There Are No Interrupts)

TX FIFO Not no Empty?

yes

DMA Controller Operation The UART controller includes a DMA controller interface to indicate when the receive FIFO buffer data is available or when the transmit FIFO buffer requires data. The DMA requires two channels, one for transmit and one for receive. The UART controller supports both single and burst transfers. The FIFO buffer depth (FIFO_DEPTH) for both the RX and TX buffers in the UART controller is 128 entries.

Related Information DMA Controller For more information, refer to the DMA Controller chapter in the Hard Processor System Technical Reference Manual.

Transmit FIFO Underflow During UART serial transfers, transmit FIFO requests are made to the DMA controller whenever the number of entries in the transmit FIFO is less than or equal to the decoded level of the Transmit Empty Trigger (TET)

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Send Feedback a10_54021 21-10 Transmit Watermark Level 2014.08.18 field in the FIFO Control Register (FCR), also known as the watermark level. The DMA controller responds by writing a burst of data to the transmit FIFO buffer, of length specified as DMA burst length. † Data should be fetched from the DMA often enough for the transmit FIFO to perform serial transfers continuously, that is, when the FIFO begins to empty, another DMA request should be triggered. Otherwise, the FIFO will run out of data (underflow) causing a STOP to be inserted on the UART bus. To prevent this condition, you must set the watermark level correctly. †

Related Information DMA Controller For more information, refer to the DMA Controller chapter in the Hard Processor System Technical Reference Manual.

Transmit Watermark Level Consider the example where the following assumption is made: † DMA burst length = FIFO_DEPTH - decoded watermark level of IIR_FCR.TET † Here the number of data items to be transferred in a DMA burst is equal to the empty space in the transmit FIFO. Consider the following two different watermark level settings: †

IIR_FCR.TET = 1 IIR_FCR.TET = 1 decodes to a watermark level of 16. • Transmit FIFO watermark level = decoded watermark level of IIR_FCR.TET = 16 † • DMA burst length = FIFO_DEPTH - decoded watermark level of IIR_FCR.TET = 112 † • UART transmit FIFO_DEPTH = 128 † • Block transaction size =R** 448† Figure 21-8: Transmit FIFO Watermark Level = 16

Transmit FIFO Buffer

FIFO_DEPTH = 128 FIFO_DEPTH - IIR_FCR.TET = 112 Empty DMA Transmit FIFO Data In Controller Watermark Level Decoded watermark Data Out Full level of IIR_FCR.TET = 16

The number of burst transactions needed equals the block size divided by the number of data items per burst: Block transaction size/DMA burst length = 448/112 = 4 The number of burst transactions in the DMA block transfer is 4. But the watermark level, decoded level of IIR_FCR.TET, is quite low. Therefore, the probability of transmit underflow is high where the UART serial transmit line needs to transmit data, but there is no data left in the transmit FIFO. This occurs because the DMA has not had time to service the DMA request before the FIFO becomes empty.

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Send Feedback a10_54021 2014.08.18 IIR_FCR.TET = 3 21-11 IIR_FCR.TET = 3 IIR_FCR.TET = 3 decodes to a watermark level of 64. • Transmit FIFO watermark level = decoded watermark level of IIR_FCR.TET = 64 † • DMA burst length = FIFO_DEPTH - decoded watermark level of IIR_FCR.TET = 64† • UART transmit FIFO_DEPTH = 128 † • Block transaction size = 448 † Figure 21-9: Transmit FIFO Watermark Level = 64

Transmit FIFO Buffer

FIFO_DEPTH = 128 Empty FIFO_DEPTH - IIR_FCR.TET = 64

Transmit FIFO Decoded watermark DMA Watermark Level Full level of IIR_FCR.TET = 64 Data In Controller Data Out

Number of burst transactions in block: † Block transaction size/DMA burst length = 448/64 = 7 † In this block transfer, there are 15 destination burst transactions in a DMA block transfer. But the watermark level, decoded level of IIR_FCR.TET, is high. Therefore, the probability of UART transmit underflow is low because the DMA controller has plenty of time to service the destination burst transaction request before the UART transmit FIFO becomes empty. † Thus, the second case has a lower probability of underflow at the expense of more burst transactions per block. This provides a potentially greater amount of bursts per block and worse bus utilization than the former case. † Therefore, the goal in choosing a watermark level is to minimize the number of transactions per block, while at the same time keeping the probability of an underflow condition to an acceptable level. In practice, this is a function of the ratio of the rate at which the UART transmits data to the rate at which the DMA can respond to destination burst requests. † Transmit FIFO Overflow Setting the DMA burst length to a value greater than the watermark level that triggers the DMA request might cause overflow when there is not enough space in the transmit FIFO to service the destination burst request. Therefore, the following equation must be adhered to in order to avoid overflow: † DMA burst length <= FIFO_DEPTH - decoded watermark level of IIR_FCR.TET In case 2: decoded watermark level of IIR_FCR.TET = 64, the amount of space in the transmit FIFO at the time of the burst request is made is equal to the DMA burst length. Thus, the transmit FIFO may be full, but not overflowed, at the completion of the burst transaction. † Therefore, for optimal operation, DMA burst length must be set at the FIFO level that triggers a transmit DMA request; that is: † DMA burst length = FIFO_DEPTH - decoded watermark level of IIR_FCR.TET

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Send Feedback a10_54021 21-12 Receive FIFO Overflow 2014.08.18 Adhering to this equation reduces the number of DMA bursts needed for block transfer, and this in turn improves bus utilization. † The transmit FIFO will not be full at the end of a DMA burst transfer if the UART controller has successfully transmitted one data item or more on the UART serial transmit line during the transfer. † Receive FIFO Overflow During UART serial transfers, receive FIFO requests are made to the DMA whenever the number of entries in the receive FIFO is at or above the decoded level of Receive Trigger (RT) field in the FIFO Control Register (IIR_FCR). This is known as the watermark level. The DMA responds by fetching a burst of data from the receive FIFO. † Data should be fetched by the DMA often enough for the receive FIFO to accept serial transfers continuously, that is, when the FIFO begins to fill, another DMA transfer is requested. Otherwise the FIFO will fill with data (overflow). To prevent this condition, the user must set the watermark level correctly. † Receive Watermark Level Similar to choosing the transmit watermark level described earlier, the receive watermark level, decoded watermark level of IIR_FCR.RT, should be set to minimize the probability of overflow, as shown in the Receive FIFO Buffer diagram. It is a tradeoff between the number of DMA burst transactions required per block versus the probability of an overflow occurring. † Receive FIFO Underflow Setting the source transaction burst length greater than the watermark level can cause underflow where there is not enough data to service the source burst request. Therefore, the following equation must be adhered to avoid underflow: † DMA burst length = decoded watermark level of IIR_FCR.RT + 1 If the number of data items in the receive FIFO is equal to the source burst length at the time of the burst request is made, the receive FIFO may be emptied, but not underflowed, at the completion of the burst transaction. For optimal operation, DMA burst length should be set at the watermark level, decoded watermark level of IIR_FCR.RT. † Adhering to this equation reduces the number of DMA bursts in a block transfer, which in turn can avoid underflow and improve bus utilization. † The receive FIFO will not be empty at the end of the source burst transaction if the UART controller has successfully received one data item or more on the UART serial receive line during the burst. † Figure 21-10: Receive FIFO Buffer

Receive FIFO Buffer

Empty

Receive FIFO DMA Watermark Level Data Out Controller Decoded watermark Full Data In level of IIR_FCR.RT

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Send Feedback a10_54021 2014.08.18 Address Map and Register Definitions 21-13

Address Map and Register Definitions The address map and register definitions for this module will be available in a future document revision.

Document Revision History

Table 21-5: Document Revision History

Date Version Changes August 2014 2014.08.18 Initial release.

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