DOCSLIB.ORG

UART Controller 21 2014.08.18

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
UART Controller 21 2014.08.18 UART Controller 21 2014.08.18 a10_54021 Subscribe Send Feedback The hard processor system (HPS) provides two UART controllers for asynchronous serial communication. The UART controllers are based on an industry standard 16550 UART controller. The UART controllers are instances of the Synopsys® DesignWare® APB Universal Asynchronous Receiver/Transmitter (DW_apb_uart) peripheral.(1) UART Controller Features The UART controller provides the following functionality and features: • Programmable character properties, such as number of data bits per character, optional parity bits, and number of stop bits † • Line break generation and detection † • DMA controller handshaking interface • Prioritized interrupt identification † • Programmable baud rate • False start bit detection † • Automatic flow control mode per 16750 standard † • Internal loopback mode support • 128-byte transmit and receive FIFO buffers • FIFO buffer status registers † • FIFO buffer access mode (for FIFO buffer testing) enables write of receive FIFO buffer by master and read of transmit FIFO buffer by master † • Shadow registers reduce software overhead and provide programmable reset † • Transmitter holding register empty (THRE) interrupt mode † • Separate thresholds for DMA request and handshake signals to maximize throughput (1) Portions © 2014 Synopsys, Inc. Used with permission. All rights reserved. Synopsys & DesignWare are registered trademarks of Synopsys, Inc. All documentation is provided "as is" and without any warranty. Synopsys expressly disclaims any and all warranties, express, implied, or otherwise, including the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, and any warranties arising out of a course of dealing or usage of trade. †Paragraphs marked with the dagger (†) symbol are Synopsys Proprietary. Used with permission. © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with 9001:2008 Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes Registered no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 a10_54021 21-2 UART Controller Block Diagram and System Integration 2014.08.18 UART Controller Block Diagram and System Integration Figure 21-1: UART Block Diagram UART Controller Serial Transmitter/ Interrupt and System MPU Receiver Reset Control IRQ Baud Clock To I/O FIFO Buffer Pins RX Generator DMA TX DMA Controller RTS Interface CTS Clock Register Block Manager Reset Slave Interface Manager L4 Peripheral Bus Table 21-1: UART Controller Block Descriptions Block Description Slave interface Slave interface between the component and L4 peripheral bus. Register block Provides main UART control, status, and interrupt generation functions.† FIFO buffer Provides FIFO buffer control and storage. † Baud clock generator Generates the transmitter and receiver baud clock. With a reference clock of 100 MHz, the UART controller supports transfer rates of 95 baud to 6.25 Mbaud. This supports communication with all known 16550 devices. The baud rate is controlled by programming the interrupt enable or divisor latch high (IER_DLH) and receive buffer, transmit holding, or divisor latch low (RBR_THR_DLL) registers. Serial transmitter Converts parallel data written to the UART into serial data and adds all additional bits, as specified by the control register, for transmission. This makeup of serial data, referred to as a character, exits the block in serial UART. † Serial receiver Converts the serial data character (as specified by the control register) received in the UART format to parallel form. Parity error detection, framing error detection and line break detection is carried out in this block. † Altera Corporation UART Controller Send Feedback a10_54021 2014.08.18 Functional Description of the UART Controller 21-3 Block Description DMA interface The UART controller includes a DMA controller interface to indicate when received data is available or when the transmit FIFO buffer requires data. The DMA requires two channels, one for transmit and one for receive. The UART controller supports single and burst transfers. You can use DMA in FIFO buffer and non-FIFO buffer mode. Related Information DMA Controller For more information, refer to the DMA Controller chapter in the Hard Processor System Technical Reference Manual. Functional Description of the UART Controller The HPS UART is based on an industry-standard 16550 UART. The UART supports serial communication with a peripheral, modem (data carrier equipment), or data set. The master (CPU) writes data over the slave bus to the UART. The UART converts the data to serial format and transmits to the destination device. The UART also receives serial data and stores it for the master (CPU). † The UART’s registers control the character length, baud rate, parity generation and checking, and interrupt generation. The UART’s single interrupt output signal is supported by several prioritized interrupt types that trigger assertion. You can separately enable or disable each of the interrupt types with the control registers. † FIFO Buffer Support The UART controller includes 128-byte FIFO buffers to buffer transmit and receive data. FIFO buffer access mode allows the master to write the receive FIFO buffer and to read the transmit FIFO buffer for test purposes. FIFO buffer access mode is enabled with the FIFO access register (FAR). Once enabled, the control portions of the transmit and receive FIFO buffers are reset and the FIFO buffers are treated as empty. † When FIFO buffer access mode is enabled, you can write data to the transmit FIFO buffer as normal; however, no serial transmission occurs in this mode and no data leaves the FIFO buffer. You can read back the data that is written to the transmit FIFO buffer with the transmit FIFO read (TFR) register. The TFR register provides the current data at the top of the transmit FIFO buffer. † Similarly, you can also read data from the receive FIFO buffer in FIFO buffer access mode. Since the normal operation of the UART is halted in this mode, you must write data to the receive FIFO buffer to read it back. The receive FIFO write (RFW) register writes data to the receive FIFO buffer. The upper two bits of the 10- bit register write framing errors and parity error detection information to the receive FIFO buffer. Bit 9 of RFW indicates a framing error and bit 8 of RFW indicates a parity error. Although you cannot read these bits back from the receive buffer register, you can check the bits by reading the line status register (LSR), and by checking the corresponding bits when the data in question is at the top of the receive FIFO buffer. † UART(RS232) Serial Protocol Because the serial communication between the UART controller and the selected device is asynchronous, additional bits (start and stop) are added to the serial data to indicate the beginning and end. Utilizing these bits allows two devices to be synchronized. This structure of serial data accompanied by start and stop bits is referred to as a character, as shown in below.† UART Controller Altera Corporation Send Feedback a10_54021 21-4 Automatic Flow Control 2014.08.18 Figure 21-2: Serial Data Format Bit Time Serial Data Start Data Bits 5 - 8 Parity Stop Bits 1, 1.5, 2 One Character An additional parity bit may be added to the serial character. This bit appears after the last data bit and before the stop bit(s) in the character structure to provide the UART controller with the ability to perform simple error checking on the received data.† The Control Register is used to control the serial character characteristics. The individual bits of the data word are sent after the start bit, starting with the least- significant bit (LSB). These are followed by the optional parity bit, followed by the stop bit(s), which can be 1, 1.5 or 2.† All the bits in the transmission (with exception to the half stop bit when 1.5 stop bits are used) are transmitted for exactly the same time duration. This is referred to as a Bit Period or Bit Time. One Bit Time equals 16 baud clocks. To ensure stability on the line, the receiver samples the serial input data at approximately the midpoint of the Bit Time once the start bit has been detected. Because the exact number of baud clocks that each bit transmission is known, calculating the midpoint for sampling is not difficult. That is, every 16 baud clocks after the midpoint sample of the start bit.† Together with serial input debouncing, this feature also contributes to avoid the detection of false start bits. Short glitches are filtered out by debouncing, and no transition is detected on the line. If a glitch is wide enough to avoid filtering by debouncing, a falling edge is detected. However, a start bit is detected only if the line is sampled low again after half a bit time has elapsed. † Figure 21-3: Receiver Serial Data Sample Points Serial Data In Start Data Bit 0 (LSB) Data Bit 1 8 16 16 The baud rate of the UART controller is controlled by the serial clock and the Divisor Latch Register ( DLH and DLL ).† Automatic Flow Control The UART includes 16750-compatible request-to-send (RTS) and clear-to-send (CTS) serial data automatic flow control mode.
Load more

Recommended publications
  • DAN189 EXAR UARTS in GPS APPLICATIONS March 2007 EXAR UARTS in GPS APPLICATIONS
    DAN189 EXAR UARTS IN GPS APPLICATIONS March 2007 EXAR UARTS IN GPS APPLICATIONS 1.0 INTRODUCTION This application note describes where an Exar UART can be used in a Global Positioning System (GPS) application. GPS has traditionally been used in military applications such as marine navigation, aircraft navigation, and weapon’s guidance. However, GPS applications have recently expanded to industrial and consumer applications such as vehicle navigation systems, fleet management, and personal navigation. In these applications, the Exar UART can be used in the GPS receiver and in the GPS application. FIGURE 1. GPS APPLICATION EXAMPLES GPS Applications Marine Navigation System Aircraft Navigation System Vehicle Navigation System Fleet Management System Personal Navigation System GPS Receiver TX RX UART RX TX UART 1.1 GPS Receiver A GPS receiver typically includes the following: • RF block for receiving the GPS data and converting it to digital data • Microprocessor for processing the data • ROM to store the firmware for processing the data • RAM used by the microprocessor for data processing • UART to send data to the GPS application The figure below shows a block diagram of a GPS receiver. FIGURE 2. GPS RECEIVER BLOCK DIAGRAM ROM RAM RF Block TX Microprocessor UART RX 1 DAN189 EXAR UARTS IN GPS APPLICATIONS The figure below shows a block diagram of an automobile GPS navigation system: FIGURE 3. AUTOMOBILE GPS NAVIGATION SYSTEM EXAMPLE Keypad ROM RAM Radio CD RX GPS UART Microprocessor DVD TX LCD The UART that has been used in the GPS receiver or in the GPS application has typically been an industry standard 16550 UART or a UART that is available on the microprocessor.
    [Show full text]
  • Ds430 Opb 16550 Uart
    0 OPB 16550 UART (v1.00d) DS430 December 2, 2005 0 0 Product Specification Introduction LogiCORE™ Facts This document provides the specification for the OPB Core Specifics 16550 UART (Universal Asynchronous QPro™-R Virtex™-II, QPro Receiver/Transmitter) Intellectual Property (IP). Virtex-II, Spartan™-II, Spartan-IIE, Supported Device Spartan-3, Spartan-3E, Virtex, The OPB 16550 UART described in this document has Family Virtex-II, Virtex-II Pro, Virtex-4, been designed incorporating features described in Virtex-E National Semiconductor PC16550D UART with FIFOs data Version of Core opb_uart16550 v1.00d sheet (June,1995),Discontinued (http://www.national.com/pf/PC/PC16550D.html). Resources Used The National Semiconductor PC16550D data sheet is Min Max referenced throughout this document and should be Slices 283 417 used as the authoritative specification. Differences LUTs 328 545 between the National Semiconductor implementation and the OPB 16550 UART Point Design implementation FFs 275 338 are highlighted and explained in Specification Block RAMs Exceptions. Provided with Core Features Documentation Product Specification • Hardware and software register compatible with all Design File Formats VHDL standard 16450 and 16550 UARTs Constraints File N/A • Implements all standard serial interface protocols Verification N/A - 5, 6, 7, or 8 bits per character Instantiation Template N/A - Odd, Even, or no parity detection and generation Reference Designs None - 1, 1.5, or 2 stop bit detection and generation Design Tool Requirements - Internal baud rate generator and separate receiver Xilinx Implementation ISE 6.1i or later clock input Tools - Modem control functions Verification ModelSim SE/EE 5.8e or later Simulation IPModelSim SE/EE 5.8e or later - False start bit detection and recovery - Prioritized transmit, receive, line status, and Synthesis XST modem control interrupts Support - Line break detection and generation Support provided by Xilinx, Inc.
    [Show full text]
  • Serial Communication Buses
    Computer Architecture 10 Serial Communication Buses Made wi th OpenOffi ce.org 1 Serial Communication SendingSending datadata oneone bitbit atat oneone time,time, sequentiallysequentially SerialSerial vsvs parallelparallel communicationcommunication cable cost (or PCB space), synchronization, distance ! speed ? ImprovedImproved serialserial communicationcommunication technologytechnology allowsallows forfor transfertransfer atat higherhigher speedsspeeds andand isis dominatingdominating thethe modernmodern digitaldigital technology:technology: RS232, RS-485, I2C, SPI, 1-Wire, USB, FireWire, Ethernet, Fibre Channel, MIDI, Serial Attached SCSI, Serial ATA, PCI Express, etc. Made wi th OpenOffi ce.org 2 RS232, EIA232 TheThe ElectronicElectronic IndustriesIndustries AllianceAlliance (EIA)(EIA) standardstandard RS-232-CRS-232-C (1969)(1969) definition of physical layer (electrical signal characteristics: voltage levels, signaling rate, timing, short-circuit behavior, cable length, etc.) 25 or (more often) 9-pin connector serial transmission (bit-by-bit) asynchronous operation (no clock signal) truly bi-directional transfer (full-duplex) only limited power can be supplied to another device numerous handshake lines (seldom used) many protocols use RS232 (e.g. Modbus) Made wi th OpenOffi ce.org 3 Voltage Levels RS-232RS-232 standardstandard convertconvert TTL/CMOS-levelTTL/CMOS-level signalssignals intointo bipolarbipolar voltagevoltage levelslevels toto improveimprove noisenoise immunityimmunity andand supportsupport longlong cablecable lengthslengths TTL/CMOS → RS232: 0V = logic zero → +3V…+12V (SPACE) +5V (+3.3V) = logic one → −3V…−12V (MARK) Some equipment ignores the negative level and accepts a zero voltage level as the "OFF" state The "dead area" between +3V and -3V may vary, many receivers are sensitive to differentials of 1V or less Made wi th OpenOffi ce.org 4 Data frame CompleteComplete one-byteone-byte frameframe consistsconsists of:of: start-bit (SPACE), data bits (7, 8), stop-bits (MARK) e.g.
    [Show full text]
  • SCR1 SDK. Altera Arria-V Starter Kit Edition. Quick Start Guide
    SCR1 SDK. Altera Arria-V Starter Kit Edition. Quick Start Guide © Syntacore, [email protected] Version 1.4, 2019-04-08 Table of Contents Revision History . 2 1. Setup equipment. 3 1.1. Prerequisites . 3 2. SDK HW assembly . 4 2.1. Connecting serial console . 4 2.2. Pins assignment. 4 3. Arria-V HW image update . 6 4. Booting the new FPGA image . 8 5. Resetting the board: . 9 6. UART connection settings . 9 7. Using UART terminal . 10 7.1. Load binary images to the Memory address . 10 7.2. Example: Dhrystone run from TCM memory . 12 7.3. Using OpenOCD. 13 7.3.1. Installing OpenOCD . 13 7.3.2. Starting the OpenOCD server. 13 7.3.3. Downloading and running an image using OpenOCD. 14 8. Building SDK FPGA-project for the Arria V GX SDK. 16 8.1. General structure of the SDK project. 16 8.2. Additional requirements for compilation . 16 8.3. Building SDK FPGA project. 17 8.3.1. FPGA firmware generation (sof-format) . 17 8.3.2. Converting FPGA-image to the board flash memory image (flash-format) . 17 8.3.3. SDK-specific pins assignment in FPGA-project . 19 8.4. SCR1 SDK FPGA-project functional description . 20 8.4.1. Common project structure . 20 8.4.2. Qsys SoC module structure. 20 8.4.3. Description of the blocks used in the SDK project . 21 8.4.3.1. SCR1-core. 21 8.4.3.2. AXI bridge . 21 8.4.3.3. Opencores UART 16550 IP . 21 8.4.4.
    [Show full text]
  • Low-Profile PCI Cards: a New Approach to Inner Space • Lavalanche Winners! • Distributor Profile Lava I/O News
    April 2002 Vol.4 No.4 Inside this issue: • Low-profile PCI cards: A New Approach to Inner Space • Lavalanche Winners! • Distributor profile Lava I/O News Low-Profile PCI Cards: A New Approach to Inner Space Most of us remember our first impression on looking inside the chassis of a desktop or tower computer: is that all there is? Apart from the motherboard, power supply, drives and cables, a few cards, and dust bunnies, things were pretty empty in there. And while we knew that air had to circulate inside the case, the empty spaces inside still seemed a bit large. Notebook computers came along and really confirmed the impression that the inside of typical computers had enough extra space for a game of baseball. sets standards for the PCI bus generally. As well as defining a maximum height for Low-profile PCI cards follow the “PCI Local cards designated as “low-profile”, the low-pro- The reason for all the empty space is historical: Bus Specification, Revision 2.2” or later, but file PCI specification also outlines two low-pro- the original PC's expansion cards were loaded in addition adopt the form factor require- file PCI card lengths —short (called “MD1”) with lots of separate and large components. ments of the new "PCI Engineering Change and long (“MD2”).An MD1 low-profile card has They were rather tall, and needed to be so. Notice —Low Profile PCI Card". Designed as a a maximum length of 4.72" (119.91 mm). An However, as integrated circuit technology collaborative effort by the PCI Special Interest MD2 card is longer than an MD1 card, but not advanced, expansion boards got smaller and Group and companies including IBM and longer than 6.6" (167.64 mm).
    [Show full text]
  • Z182 Com Port Appnote
    HIGH PERFORMANCE PC COMMUNICATION Zilog PORT USING THE Z182 MICROCONTROLLER HIGH PERFORMANCE PC COMMUNICATION PORT USING THE Z182 o meet the demands of high speed communications on the Information Superhighway, Zilog's Z182-based PC Communication Port "COMPORT.S™" software code provides the user with increased data buffering capabilities for faster communication between PCs T and modems. INTRODUCTION With the advent of the Information Superhighway, users will handle heavy traffic at only a sustained rate of 57.6 Kbps. be able to access information quickly and easily by means This factor, combined with limited CPU bandwidth (due to of PC/Modem communications. However, user-friendly complex operating systems), means users cannot take full operating systems, capable of processing large amounts advantage of the high throughput that today’s modems of data, become so performance intensive that data com- can accommodate. munication becomes a bottleneck. Although there have been many advances in modem and PC design, a satis- PC Week's labs (July 1992) analyzed the serial card factory solution to the PC/modem communication bottle- bottleneck issue and their tests showed that a standard neck has not been found. serial card could not reliably sustain data transfer over 19.2 Kbps. However, when using a 16550 UART loaded The PC/Modem communication bottleneck is caused by serial card, the user could expect 57.6 Kbps of reliable, the PC standard serial cards used to connect to the sustained data transfer. This is great for V.32bis, but what modems. Conventional serial cards were designed to about V.FAST and beyond? Serial Port Limitations If you look at a PC Standard Serial Card, you will find a 8250 quickly to interrupts in a multi-tasking system? The answer or 16450 UART as well as RS-232 line drivers.
    [Show full text]
  • XR20M1170 Data Sheet
    XR20M1170 I2C/SPI UART WITH 64-BYTE FIFO JUNE 2019 REV. 1.1.2 GENERAL DESCRIPTION FEATURES 1.62 to 3.6 Volt operation The XR20M11701 is a high performance universal asynchronous receiver and transmitter (UART) with Selectable I2C/SPI interface 64 byte TX and RX FIFOs and a selectable I2C/SPI SPI clock frequency up to slave interface. The XR20M1170 operates from 1.62 to 3.63 volts. The enhanced features in the 18MHz at 3.3V XR20M1170 include a programmable fractional baud 16MHz at 2.5V rate generator, an 8X and 4X sampling rate that 8MHz at 1.8V allows for a maximum baud rate of 16Mbps at 3.3V. The standard features include 16 selectable TX and Full-featured UART RX FIFO trigger levels, automatic hardware (RTS/ Data rate of up to 16Mbps at 3.3V CTS) and software (Xon/Xoff) flow control, and a Data rate of up to 12.5Mbps at 2.5V complete modem interface. Onboard registers provide the user with operational status and data Data rate of up to 8Mbps at 1.8V error flags. An internal loopback capability allows Fractional baud rate generator system diagnostics. The XR20M1170 is available in Transmit and receive FIFOs of 64 bytes the 24-pin QFN, 16-pin QFN, 24-pin TSSOP and 16- 16 selectable TX and RX FIFO trigger levels pin TSSOP packages. Automatic hardware (RTS/CTS) flow control NOTE: 1 Covered by U.S. Patent #5,649,122 Automatic software (Xon/Xoff) flow control APPLICATIONS Halt and resume transmission control Portable appliances Automatic RS-485 half-duplex direction control output via RTS# Battery-operated devices Wireless Infrared (IrDA 1.0 and 1.1) encoder/ Cellular data devices decoder Factory automation and process controls Automatic sleep mode (< 15uA at 3.3V) General purpose I/Os Full modem interface Crystal oscillator (up to 24MHz) or external clock (up to 64MHz) input 24-QFN, 16-QFN, 24-TSSOP, 16-TSSOP packages FIGURE 1.
    [Show full text]
  • Microprocessors and Microcontrollers (EE-231) Main Objectives
    Microprocessors and Microcontrollers (EE-231) Main Objectives • 16550 Communication Device • ADC and DAC interfacing 16550 Programmable Communications Interface • National Semiconductor Corp’s PC16550D is a programmable communications interface designed to connect to virtually any type of serial interface. • 16550 is a universal asynchronous receiver/transmitter (UART) fully compatible with Intel microprocessors. • 16550 operates at 0–1.5 M baud. – baud rate is bps (bits transferred per second) including start, stop, data, and parity • 16550 also includes a programmable baud rate generator and separate FIFOs for input and output data to ease the load on the microprocessor. • Each FIFO contains 16 bytes of storage. • The most common communications interface found in the PC and many modems. Asynchronous Serial Data • Asynchronous serial data are transmitted and received without a clock and in frames as shown in figure. – each frame contains a start bit, seven data bits, parity, and one stop bit • Most Internet services use 10 bits, but normally do not use parity. • instead, eight data bits are transferred, replacing parity with a data bit 16550 Functional Description • The device is available as a 40-pin DIP (dual in-line package) or as a 44-pin PLCC (plastic leadless chip carrier). • Two completely separate sections are responsible for data communications. – the receiver and the transmitter • Because each sections is independent, 16550 is able to function in simplex, half-duplex, or full-duplex modes. The pin-out of the 16550 UART. 16550 Functional Description • A major feature of the 16550 is its internal receiver and transmitter FIFO (first-in, first-out) memories. • Because each is 16 bytes deep, the UART requires attention from the processor only after receiving 16 bytes of data.
    [Show full text]
  • Operating System Support Matrix
    Operating System Win Win Win Win Win Win Win Win THEOS Product Description Win Win Win Win Windows Win XP Win XP Server Server Server Server Server Server Win 7 Win 7 Win 8 Win 8 Server Server Win 8.1 Win 8.1 Corona DOS Win 3.x Win NT4 Win 95 Win 98 Win 98SE Win Me Win 2000 Server Server Vista Vista Thin a Mac 8.6+ QNX 6.2 THEOS SCO 5.07 SCO 6.0 32 64 2003 2003 R2 2003 R2 2008 2008 2008 R2 32 64 32 64 2012 2012 R2 32 64 Linux Ver. 5.0 2000 2003 64 32 64 Client 32 32 64 32 64 64 64 64 PL182 USB-Serial Links USB-Serial Link 2-232-DB9 Two RS-232, 9-pin DB-9s USB-Serial Link 4-232-DB9 Four RS-232, 9-pin DB-9s USB-Serial Link 4-232-DB9 Cabled Four RS-232, 9-pin DB-9s with fan-out cable Serial PCIe SSerial-PCIe One 25-pin port, 16550 UART SSerial-PCIe/LP One 25-pin port, 16550 UART, low-profile DSerial-PCIe Two 9-pin ports, 16550 UARTs DSerial-PCIe/LP Two 9-pin ports, 16550 UARTs, low-profile Quattro-PCIe Four 9-pin ports, 16550 UARTs Serial PCI SSerial-PCI One 9-pin port, 16550 UART ? SSerial-PCI/LP One 25-pin port, 16550 UART, low-profile ? RS422 SS-PCI One 9-pin port, 16550 UART, RS-422 pinout ? LavaPort-650 One 9-pin port, 16650 UART ? DSerial-PCI Two 9-pin ports, 16550 UARTs
    [Show full text]
  • Add Ports to Your PC with These PCI Cards Featuring High-Speed Buffered Uarts
    FREE 24-hour Tech Support: 724-746-5500 blackbox.com © 2010. All rights reserved. Black Box Corporation. PCI Cards Add ports to your PC with these PCI cards featuring high-speed buffered UARTs. 4/12/2010 #26217 ­­1 of 6 Connect up to 31 RS-485 devices to each port on the Quad-Port RS-232/422/485 PCI Card. FEaturES » Provide an easily configurable interface that’s simple to connect. » Some models meet a variety of interface Quad-Port RS-232/422/485 standards. PCI Card » Advanced buffered UARTs for faster (IC974C) data transmission. » Low-profile models fit in the PCI slots of newer, slimmer PCs. » Opto-isolation available on some models. » Drivers for all Windows operating systems are included. Time Clocks OVERVIEW When you need to add extra PCI ports to your personal com puter, In both RS-232 and RS-422 modes, the PCI cards work seamlessly select a PCI card from Black Box®. All our cards feature speedy with your standard operating system’s serial driver. In RS-485 mode, buffered Universal Asynchronous Receiver/Trans mitters (UARTs); the cards’ special autoenable feature allows the RS-485 ports to be these are integrated circuits that convert bytes from the computer viewed by the operating system as a COM port. This enables you to bus into serial bits for transmission. use a standard COM driver (instead of a custom software driver) for The cards are designed to maxi mize DOS, Linux®, OS/2®, QNX, your high-speed Windows® 95/98/Me/XP, Windows 2000, Windows NT®, and UNIX® RS-485 connections.
    [Show full text]
  • 8-Port PCI Express Serial Card with 16550 UART
    8-Port PCI Express Serial Card with 16550 UART Product ID: PEX8S1050LP Add eight RS-232 DB9 serial ports to your desktop computer, through two PCIe expansion card slots. This PCI express serial card, with two breakout cables, provides you with multiple ports to connect a wide variety of serial peripherals, at speeds of up to 921.4Kbps. Connect your Peripherals with 8 Serial Ports The PCI express serial port card makes it easy to add serial ports to connect your peripherals including printers, scanners, credit/debit card readers, PIN pads and modems, industrial controls and more. The 8 port PCIe serial card includes 2 breakout cables - each with 4 DB9 connectors. Versatile Use The low profile PCIe serial card is the ideal choice for adding serial ports, even when space is at a premium. The DB9 serial card is designed to fit into small form factor and standard computer cases. The card comes pre-configured with a low-profile bracket, and includes two optional full-profile brackets, so installation is easy regardless of the case form factor. www.startech.com 1 800 265 1844 Maximum Compatibility With broad OS support, including for Windows and Linux, this PCI Express card is easy to integrate into mixed environments. PEX8S1050LP is backed by a StarTech.com lifetime warranty and free lifetime technical support. www.startech.com 1 800 265 1844 Certifications, Reports Applications and Compatibility • Manufacturing (CNC machinery, process control equipment, bar code scanners, serial printers) • POS (credit/debit card readers, receipt printers,
    [Show full text]
  • RS232/422/485 Serial Communications
    RS232/422/485 Serial Communications Users Manual (SERIAL) Version 5.1 August 19, 2011 This software is provided as-is. There are no warranties, expressed or implied. Copyright (C) 2011 All rights reserved MarshallSoft Computing, Inc. Post Office Box 4543 Huntsville AL 35815 USA Email: [email protected] Web: www.marshallsoft.com MARSHALLSOFT is a registered trademark of MarshallSoft Computing. 1 TABLE OF CONTENTS 1 The UART Page 3 1.1 Emulated UARTs Page 3 1.2 UART Types Page 3 1.2.1 National 8250 Page 3 1.2.2 National 16450 Page 3 1.2.3 National 16550 Page 3 1.2.4 StarTech 16650 Page 3 1.2.5 Texas Instruments 16750 Page 3 1.3 UART Operation Page 4 1.4 RS-232 Signals Page 5 1.5 UART Registers Page 6 1.6 Register Summary Page 7 2 Modems Page 10 2.1 Modem Standards Page 10 2.1.1 Speed Page 10 2.1.2 Data Compression Page 10 2.1.3 Error Control Page 10 2.2 Modem AT Command Set Page 11 2.3 Flow Control Page 11 2.4 Modem Initialization Page 12 2.5 Modem CONNECT Page 12 2.6 More Modem Documentation Page 12 3 RS422 and RS485 Page 13 4 Other Serial Devices Page 13 2 1 The UART The heart of serial communications is the "Universal Asynchronous Receiver Transmitter” or UART for short. The UART is responsible for controlling the computer's RS-232/422/485 port. 1.1 Emulated UARTs Some computers, particularly laptops and Handheld / Pocket PC’s, do not contain real UART chips.
    [Show full text]