Cascaded Noise Shaping for Oversampling A/D and D/A Conversion

Bruce A. Wooley Stanford University

. Oversampling modulators for A-to-D conversion

. Cascaded ΣΔ modulators

. Low-voltage ΣΔ modulator design for MHz-bandwidth signals

. Cascaded noise shaping for bandpass oversampling D-to-A conversion

Bruce A. Wooley - 2 - Stanford University, 2005 Analog-to-Digital Conversion

00001011 11000011 01001000 Digital Processor

Filtering Sampling Quantization Processing

Quantizer model: p(eQ) eQ[n]

1/Δ Σ -Δ/2 Δ/2

Bruce A. Wooley - 3 - Stanford University, 2005 Quantization Noise Shaping

S (f) NB Q Quantizer resolution increased by 3 dB per octave of OVERSAMPLING -fS/2 -fB fB fS/2

SQ(f)

Quantizer resolution NB increased through NOISE SHAPING

-fS/2 -fB fB fS/2

Bruce A. Wooley - 4 - Stanford University, 2005 Oversampling Modulators

. Embed quantizer in a feedback loop to achieve larger improvement in resolution with increased oversampling

. Feedback can be used for PREDICTION (Δ modulation) or NOISE SHAPING (ΣΔ modulation)

. Noise shaping modulators are more robust and easier to implement than predictive modulators

Bruce A. Wooley - 5 - Stanford University, 2005 Sigma-Delta (or Delta-Sigma) Modulation

EQ(z)

Integrator

z-1 X(z) A/D Y(z) Σ 1− z -1

D/A

"1 "1 Y (z) = z X(z) + (1" z )EQ(z) 2 N (f) 2sin f / f N (f) E = [ ( " S )] Q !

Bruce A. Wooley - 6 - Stanford University, 2005 ! ΣΔ Modulator Response

0.6

0.4

0.2

-0.2

-0.4 Modulator Input, Quantizer Output -0.6 0 50 100 150 200 250 Time (t/T)

Bruce A. Wooley - 7 - Stanford University, 2005 Noise Shaping

Ideal Digital Lowpass Filter

First-Order Noise Shaping

f /2 fB fN S Frequency

Bruce A. Wooley - 8 - Stanford University, 2005 Higher-Order Noise-Shaping Modulators

The order of the noise shaping can be increased using either . Single quantizer modulators − Multi-loop noise differencing − Single loop with multi-order filtering or . Cascaded (multistage) modulators

Bruce A. Wooley - 9 - Stanford University, 2005 Noise-Differencing ΣΔ Modulators

Y(z) = z–1X(z) + (1– z–1)LE(z)

L=3 L=2

LP Filter L=1 Noise Shaping

fB fN fS/2 Frequency

Bruce A. Wooley - 10 - Stanford University, 2005 ΣΔ Modulator Dynamic Range

(with 1-bit quantization)

140

120

100 L=3 L=2 80 L=1 60

40 Dynamic Range (dB) 20

0 4 8 16 32 64 128 256 512 Oversampling Ratio

Bruce A. Wooley - 11 - Stanford University, 2005 Single-Quantizer ΣΔ Modulator

E(z)

+ X(z) – A(z) + Y(z) –

F(z)

Y (z) = HX(z)X(z) + HE(z)E(z) where A(z) 1 HX(z) = , HE(z) = ! 1+ A(z)F(z) 1+ A(z)F(z) and H (z) 1" H (z) A(z) = X , F(z) = E H (z) H (z) ! E X

Bruce A. Wooley - 12 - Stanford University, 2005

! Noise Differencing Modulators

. Y(z) = z–1X(z) + (1– z–1)LE(z) . Can implement with a single quantizer and L nested loops . Limit cycle instability for L > 2 . For L = 2 z"1 A(z) = and F(z) = 2 " z"1 "1 2 (1" z )

Integrator 1 Integrator 2 Integrator L E

! 1 + + 1 + 1 + z! + X " " " !1 " Y 1!z!1 1!z!1 1!z ! ! !

Bruce A. Wooley - 13 - Stanford University, 2005 2nd-Order Modulator Implementation

E A(z) + + + + + X " " " z!1 " Y ! + + z!1

! F(z) " z!1 + + + " ! E

+ + + + + + X " " " " z!1 " Y ! + ! + z!1

Unity + + Transfer " " + ! Function 1 z!1 z!

Bruce A. Wooley - 14 - Stanford University, 2005 2nd-Order ΣΔ Modulator

E + + + + + + X " " " " z!1 " Y ! + ! + z!1

! E + + + + + + + X " " z!1 " " " z!1 " Y + ! + ! +

Bruce A. Wooley - 15 - Stanford University, 2005 2nd-Order ΣΔ Modulator

E + + + + + + X " " z!1 " " z!1 " Y ! + ! +

! E + + 1 + + + + !1 !1 X " 2 " z " 2 " z " Y ! + ! + +

Bruce A. Wooley - 16 - Stanford University, 2005 2nd-Order Noise-Differencing ΣΔ Modulator *

(with 1-bit quantization)

Can scale only w/ 1-bit quantizer

INTEGRATOR 1 INTEGRATOR 2 QUANTIZER x(nT) + + + + y(nT) 1 1 1-bit A/D ! 2 ! DELAY ! 2 ! DELAY – + – +

D/A q(nT)

* B. Boser, JSSC, Dec .1988

Bruce A. Wooley - 17 - Stanford University, 2005 Cascaded ΣΔ Modulators

. Quantizer error quantized by subsequent stage and then digitally filtered and subtracted from output of preceding stage

. Cancellation of lower-order noise-shaping terms depends on matching of analog and digital paths

. No potential instability if use first- and second-order stages

Bruce A. Wooley - 18 - Stanford University, 2005 Cascaded Noise-Shaping Modulator

Analog + Digital x !" y Delay ! In – Out e

Digital ADC Difference

Matches noise shaping of quantization error in first-stage

Bruce A. Wooley - 19 - Stanford University, 2005 Maximum Improvement in Dynamic Range

80.0

Simulation Closed form equation 60.0

40.0

20.0 Independent of OSR

0.0 0.01 0.1 1 10 Coefficient Mismatch (%)

Bruce A. Wooley - 20 - Stanford University, 2005 Third-Order (2-1) Cascaded Modulator

nd y x 2 order !" 1 Error y Cancellation e1

y2 1st order !"

"2 "1 2 Y1(z) = z X(z) + (1" z ) E1(z)

"1 "1 Y2(z) = z E1(z) + (1" z )E2(z)

"1 "1 2 "3 "1 3 Y (z) = z Y1(z) " (1" z ) Y2(z) = z X(z) + (1" z ) E2(z)

Bruce A. Wooley - 21 - Stanford University, 2005 ! 2-1 Cascaded ΣΔ Modulator

+ + x $ # $ # y1 - -

" + ! $ -

+ $ # y2 -

Bruce A. Wooley - 22 - Stanford University, 2005 Matching Error in 2-1 Cascade

2 Calculated Simulated 0 Loss in Dynamic Range (dB)

-2 -10 -5 0 5 10 Matching Error (%)

Bruce A. Wooley - 23 - Stanford University, 2005 Spectrum of 2-1 Cascade w/ Mismatch

-50

-100

Spectral Power (dB) -150

-200 0 5 10 15 20 25 Frequency (kHz)

Bruce A. Wooley - 24 - Stanford University, 2005 Matching Error in 1-1-1 Cascade

15 Calculated Simulated 10

Loss in Dynamic Range (dB) 5

0 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Matching Error (%)

Bruce A. Wooley - 25 - Stanford University, 2005 Spectrum of 1-1-1 Cascade w/ Mismatch

-50

-100

Spectral Power (dB) -150

-200 0 5 10 15 20 25 Frequency (kHz)

Bruce A. Wooley - 26 - Stanford University, 2005 Advantages of 2-1 Cascade

. Low sensitivity to precision of analog circuits

. Suppression of spurious noise tones resulting for correlation of quantization noise with input

. Considerable design flexibility

. No potential instability

Bruce A. Wooley - 27 - Stanford University, 2005 Analog Integration in CMOS

. Continuous Time (tune gm or MOS-R)

– gm-C – MOSFET-C

. Sampled Data – Switched current – Switched capacitor

Bruce A. Wooley - 28 - Stanford University, 2005 Analog Integration in CMOS

. Continuous-time (gm-C or MOSFET)

– Tune gm or MOS resistor – Performance limited by timing jitter, waveform asymmetry and integrator linearity . Switched-current – Limitations: • current sources must be cascoded to increase output resistance  high supply voltage

• large VGS – VT needed to reduce sensitivity to VT mismatch  high power dissipation • sensitive to switch parasitics and charge injection • noise introduced into “compressed” signal  Switched-capacitor approach preferable for obtaining high resolution at low supply voltage and low power dissipation

Bruce A. Wooley - 29 - Stanford University, 2005 Low-Power ΣΔ Modulator Design *

1 Cs 2 x ! H(z) Q y 2 1 +

. High-resolution converters should by limited by thermal noise – kT/C noise in switched-capacitor circuits . First stage limit performance and therefore dissipates a large fraction of power . Minimize power by minimizing capacitor size in switched-C implementations

* S. Rabii, JSSC, June 1997

Bruce A. Wooley - 30 - Stanford University, 2005 ΣΔ Modulator Implementation

1/5 1/6

y ! ! 1 x 1/5 " 1/3 " H (z) + # + # 1

1/20

! y2 + 3/4 " H2(z) " + ! # !

1/5 y

Bruce A. Wooley - 31 - Stanford University, 2005 First Stage of Modulator

1.8V 0V 1.8V 0V

S2 S5 S6 0.3V S7 0.3V 20pF 0.9V S3 S6 4pF S1 S4 S5 S8 Vi( ) + + ! + !

Vi(!) ! + ! + S1 4pF S4 S5 S8 S3 S6

0.3V 20pF 0.9V S7

S2 S5 S6 0.3V

1.8V 0V 1.8V 0V

S1, S5: !1delayed, CMOS S3, S7: !1, NMOS

S2, S6: !2delayed, CMOS S4, S8: !2, NMOS

Bruce A. Wooley - 32 - Stanford University, 2005 2-Stage Class A/AB Amplifier

1.8 V

M9 M7 Vcmfb1 M8 M10 M13 Vbz Vbz

Mz Vin(+) M1 M2 Vin(!) Mz Vout(+) Vout(!) CC CC

Vbias Vo1(!) Vo1(+) M11 M5 M3 M4 M6 M12

Bruce A. Wooley - 33 - Stanford University, 2005 Die Photo of 1.8-V CMOS ΣΔ Modulator

Bruce A. Wooley - 34 - Stanford University, 2005 Measured SNR and SNDR

100 SNR

SNDR 80

0 -100 -80 -60 -40 -20 0 Input Level (dB)

Bruce A. Wooley - 35 - Stanford University, 2005 Measured Baseband Output Spectrum

0 -20 -40 !20 dB, 2 kHz Input -60 -80 -100 -120 -140 -160 0 5 10 15 20 25 Frequency (kHz)

Bruce A. Wooley - 36 - Stanford University, 2005 Dynamic Range vs. Oversampling Ratio

110

100

60 20 50 100 200 300 Oversampling Ratio

Bruce A. Wooley - 37 - Stanford University, 2005 Dynamic Range & Power vs. Supply Voltage

100 4.0

3.5 99

3.0

98 Power 2.5 Dynamic range

97 2.0 1.5 1.7 1.9 2.1 2.3 2.5 Supply Voltage (V)

Bruce A. Wooley - 38 - Stanford University, 2005 1.8-V CMOS ΣΔ Modulator Performance

Dynamic range 99 dB Peak SNR 99 dB Peak SNDR 95 dB Bandwidth 25 kHz Oversampling ratio 80 Power dissipation 2.5 mW Active area 1.5 mm2 Technology 0.8-µm CMOS Threshold voltages +0.65 V, –0.75 V

Bruce A. Wooley - 39 - Stanford University, 2005 Power Efficiency Figure of Merit

. Power efficiency as a Figure of Merit:

DynamicRange " Bandwidth FoM = Power 22N " BW = (MHz / mW) Power ! where Dynamic Range is a POWER, not voltage, ratio N = effective # of bits of resolution !

. For circuits in which the dynamic range is limited by thermal noise and the bandwidth is not limited by technology: – Quadratic dependence on voltage dynamic range – Linear dependence on bandwidth

Bruce A. Wooley - 40 - Stanford University, 2005 ADC Power Efficiency

Bruce A. Wooley - 41 - Stanford University, 2005 Low-Voltage Broadband ΣΔ Modulation *

. Target objective is low-voltage, high-resolution broadband A/D conversion for applications such as ADSL, CDMA 2000, IS-95, and GSM

. Objectives – Conversion rate 2.5 MSample/s – Dynamic range 92 dB (15 bits) – Power supply 1.2V – Power dissipation ~ 80 mW – Technology 0.25-µm CMOS

* K. Nam, 2004 CICC

Bruce A. Wooley - 42 - Stanford University, 2005 Analog Challenges @ Low VDD

. Reduced voltage headroom

. Limited choice of op amp topologies

. Dynamic range decreases unless noise floor is reduced ∴ Low-voltage analog  high power

. In this work consider architecture and circuits needed to achieve low voltage and low power

Bruce A. Wooley - 43 - Stanford University, 2005 Low-Voltage, Low-Power Strategies

. Low oversampling ratio & high-order modulator

. Maximize the full-scale input amplitude for a given VDD

. Multi-bit quantization

. Single-stage op amps

. Linear integrator settling – allows use of slower op amps

Bruce A. Wooley - 44 - Stanford University, 2005 Architectural Decisions

. Single-bit or multi-bit quantization  multi-bit – single-bit feedback causes op amp slew  need fast op amp – single-bit quantization results in larger quantization noise leakage into the output in cascaded modulators

. Single-quantizer or cascade  cascade – Even with multi-bit quantization op amp slewing can limit performance of a high-order single-quantizer modulator  use 2nd-order modulator for first stage – 2-2 cascade with 5-bit and 3-bit quantizers

Bruce A. Wooley - 45 - Stanford University, 2005 Conventional First-Order ΣΔ Modulator

-1 U1 z V1 X Y 1– z-1 N-bit Y = z–1X + (1 – z–1)E

DAC

–1 –1 . U1 = (1 – z )X – (1 – z )E  magnitude depends on input amplitude and frequency –1 –1 . V1 = z X – z E  magnitude depends on input . Op amps designed to ensure minimum SNDR degradation for large signals  inefficient power allocation

Bruce A. Wooley - 46 - Stanford University, 2005 Reduced Integrator Swing-Range ΣΔ Modulator

U z-1 V W X 1 1 1 Y 1– z-1 N-bit Y = X + (1 – z–1)E

DAC

–1 . U1 = – (1 – z )E  |U1| ≤ LSB –1 V1 = – z E  |V1| ≤ 0.5 LSB

U1 & V1 are DECOUPLED from the input X  attractive at low VDD –1 . W1 = X – z E  swing-range burden is moved to W1 . Approach can be extended to higher-order modulators

Bruce A. Wooley - 47 - Stanford University, 2005 Second-Order RISR ΣΔ Modulator

-1 -1 U1 z V1 z V2 W1 X Y 1– z-1 1– z-1 N-bit 2 Y = X + (1 – z–1)2E DAC

–1 2 . U1 = – (1 – z ) E  |U1| ≤ 2 LSB

–1 –1 . V1 = – z (1 – z )E  |V1| ≤ LSB

–2 . V2 = – z E  |V2| ≤ 0.5 LSB

–1 –1 . W1 = X + z (z – 2)E * J. Silva, Elec Letters, June 2001

Bruce A. Wooley - 48 - Stanford University, 2005 Trade-Offs in RISR ΣΔ Modulators

1.00

0.75 –1 L U1 = – (1 – z ) E 0.50

0.25 L = 2 & N = 5 for first stage

L=1 For V = 1.2V, 0.00 L=2 REF L=3 |X|FS = 1.1V 1.00 L=4 |U1|max = 150mV 0.75 |V1|max = 75mV |V | = 37.5mV 0.50 2 max

0.25 # 2N " (2L " 1)& | X |FS = % ( VREF 0.00 % 2N 1 ( 1 2 3 4 5 6 $ " ' Number of quantizer bits

Bruce A. Wooley !- 49 - Stanford University, 2005 Implementation Issues

. Integrator op amp: requirements are greatly relaxed – small input signal range • linear settling dominates • slow op amp can be used  power saving – relaxed dc gain requirement – small output range

. Quantizer: more stringent requirements – multiple signals summed at quantizer input – offset • increases swing ranges • need offset cancellation – very fast regeneration needed since latch must be strobed after sampling of the input is complete

Bruce A. Wooley - 50 - Stanford University, 2005 Experimental Prototype

-1 -1 U1 z V1 z V2 Y1 X 1– z-1 1– z-1 5-bit 2 DWA-DAC Yout

-1 -1 z z Y2 V2 -1 1– z 1– z-1 3-bit 2 DAC

Bruce A. Wooley - 51 - Stanford University, 2005 First-Stage Implementation *

DWA-DAC

CI1 S4P j CI2 RefP C S4Nj S1j S2 RefN S5 CS2 S6 S1j 5-bit X S3 S8 S7 j=1,...,32 Y1

!1, ! 1d S1j, S3, S5, S7

!2, ! 2d S4Pj or S4Nj, S2, S6, S8

* actual implementation is fully differential

Bruce A. Wooley - 52 - Stanford University, 2005 Low Distortion Input Sampling *

!1 VDD M4 VDD VDD

M5 Cboost M3

X !1 MSj CS1j j=1,...,32

* M. Dessouky, JSSC, March 2001

Bruce A. Wooley - 53 - Stanford University, 2005 First Op Amp

VDD VDD VDD

VB1 2.4 mA 2.4 mA VB2

Vin1 M1 M2 Vin2

Vout1 Vout2 0.4 V

9.8 mA 9.8 mA VB3

CMFB Dc gain 57dB gm1 96mS

Power 29mW BWCL 122MHz

VCM(in) 0.15mV VCM(out) 0.65V

Bruce A. Wooley - 54 - Stanford University, 2005 Quantizer Comparator (1 of 32)

!1 !1d X Cq

!2d !2 !2d VRi !1 !1d V 1 C V q os !latch !2d !2 A -V1 C 1 P A !1 !1d 2 V2 Cq

!2d !2 CM

!1, ! 1d !2, ! 2d

!latch

Bruce A. Wooley - 55 - Stanford University, 2005 Prototype Die Photo

Intg4 Quant2

Intg3

Intg2 Quant1

Intg1 DWA & Logic CLK

Bruce A. Wooley - 56 - Stanford University, 2005 Measured SNR and SNDR

100.0

80.0 fin=366KHz SNR 60.0 SNDR

40.0

20.0

0.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 Input Level (dB)

Bruce A. Wooley - 57 - Stanford University, 2005 Measured Output Spectrum

–4-dB, 109-kHz Input

-50

SFDR = 97dB

-100

-150 0.00 0.25 0.50 0.75 1.00 1.25 Frequency (MHz)

Bruce A. Wooley - 58 - Stanford University, 2005 Performance Summary

Analog Supply Voltage 1.2 V Sampling Rate 40 MHz Signal Bandwidth 1.25 MHz Dynamic Range 96 dB Peak SNDR @ 366-kHz input 89 dB Analog Power 44 mW Digital Power 43 mW * Active Area 8.6 mm2 Technology 0.25-µm CMOS

* Estimate 10 mW digital power in 0.13-µm CMOS

Bruce A. Wooley - 59 - Stanford University, 2005 Bandpass Oversampling D/A Conversion *

. Consider the use of cascaded noise shaping for bandpass D/A conversion in RF transmitters

. Move IF into the digital domain to eliminate – dc offset – I & Q mismatch

. Merge D/A conversion, noise shaping, reconstruction and mixing to IF

. Explore the use of cascaded noise shaping with semi- digital filtering

* D. Barkin, 2003 VLSI Ckts Symp

Bruce A. Wooley - 60 - Stanford University, 2005 Traditional Wireless Transmitter Architecture

cos !t

I M FIR/ROM DAC LPF

Out

Q M FIR/ROM DAC LPF

sin !t Digital Analog

Bruce A. Wooley - 61 - Stanford University, 2005 Bandpass Oversampling DAC

cos(!t) = [ 1, 0, -1, 0, ... ]

Noise I M Shaping DAC Analog + IF Filtering Output

Noise Q M Shaping Digital Analog

sin(!t) = [ 0, 1, 0, -1, ... ]

. Mix to IF (at fS/4) following cascaded noise shaping . Error cancellation performed at IF

Bruce A. Wooley - 62 - Stanford University, 2005 Lowpass Cascaded Noise Shaping

nd Digital 2 Order 1 Input !" Modulator Signal

Stage 1 Error

Noise rd 3 Order Estimate !" (1 - z-1) 2 Modulator 4

. 2nd-order differentiator matches noise shaping in first stage

Bruce A. Wooley - 63 - Stanford University, 2005 Bandpass DAC Architecture

1 !1 Cascaded I "# -1,1 4 !1 Modulator (1 - z-1) 2 DAC + Filtering

1 !2 Cascaded Q "# 1,-1 Modulator 4 !2 (1 - z-1) 2

fs/2 fs

. I and Q modulators operate at fS/2, saving power

Bruce A. Wooley - 64 - Stanford University, 2005 Discrete Time - Continuous Time Interface

-1,1 1 Signal Semi-Digital Filter

-1,1 1 2 64 Noise Digital (1 - z-1) 2 Estimate Filter 4 11 6

Digital Analog

. Semi-digital filtering for reconstruction of signal − Good for 1-bit signal path, but not multi-bit noise estimation path . Digital filter reduces out-of-band quantization noise . Digital filter transfer function matches that of semi-digital filter

Bruce A. Wooley - 65 - Stanford University, 2005 Semi-Digital Filter *

1 Digital z-1 z-1 z-1 Input

a1 a2 aN

Analog Output

. Mismatch among current sources alters the transfer function but doesn’t introduce nonlinearity . Area limits number of taps and precision of coefficients . Good for 1-bit signal path but not multi-bit noise estimation path

* D. Su, JSSC, Dec. 1993

Bruce A. Wooley - 66 - Stanford University, 2005 Bandpass Data Weighted Averaging *

1 Semi-Digital Filter

-1,1

-1,1 BP 1 2 64 Digital DWA (1 - z-1) 2 4 Filter 11 6 Pointer Calc

fs/2 Notch fs/4 Notch I & Q pointer calculations are independent

7 5 3 8 2 I 7 5 3 8 2 Q 6 4 2 6 3 Time --> * T. Shui, et al., ISCAS, 1998

Bruce A. Wooley - 67 - Stanford University, 2005 Bandpass DAC Die Photo

Noise Shapers Current + Source Digital Array Filters Bias

Bruce A. Wooley - 68 - Stanford University, 2005 DAC Output Spectrum

2-3 (4 bit) Digital Noise Shaper Output Measured DAC Output 0

46 dB -50 Power Spectral Density (dB) -100 0 20 40 60 80 100 Frequency (MHz)

Bruce A. Wooley - 69 - Stanford University, 2005 SNR and SNDR

100

SFDR & SNDR (dB) Measured SFDR 0 Measured SNDR -20 -100 - 80 - 60 - 40 - 20 0 Signal Power (dB)

Bruce A. Wooley - 70 - Stanford University, 2005 Bandpass DAC Performance

Technology 0.25-µm CMOS Center frequency 50 MHz Bandwidth 6.25 MHz Peak SNDR 76 dB Dynamic range 85 dB Minimum out-of-band suppression 80 dB Mirror for –6 dB Input –90 dB Active area 2.1 mm2 Power (except for current sources) 100 mW

Bruce A. Wooley - 71 - Stanford University, 2005 Summary

. Cascades of first- and second-order noise-shaping modulator stages can be used for – A/D and D/A conversion – lowpass and bandpass data conversion . If properly designed, advantages include – no potential instability – decorrelation of quantization noise and input – low sensitivity to analog precision . Still room for architectural and circuit innovation to meet the challenges presented by – technology scaling to sub-100nm dimensions – performance demands of new applications

Bruce A. Wooley - 72 - Stanford University, 2005 References – I

OVERSAMPLING A-to-D CONVERSION

1. B. E. Boser and B. A. Wooley, “The Design of Sigma-Delta Modulation Analog-to- Digital Converters,” IEEE J. Solid-State Circuits, vol. 23, pp. 1298-1308, Dec.1988. 2. W. R. Bennett, “Spectra of Quantized Signals,” Bell Sys. Tech. Journal, vol. 27, pp. 446-472, July 1948. 3. F. de Jager, “Delta Modulation, a Method of PCM Transmission Using the 1-Unit Code,” Philips Res. Report, vol. 7, pp. 442-446. 4. C. Cutler, “Transmission Systems Employing Quantization,” U.S. Patent No. 2,927,962, Mar. 8, 1960. 5. H. Inose and Y. Yasuda, “A Unity Bit coding Method by Negative Feedback,” Proc. IEEE, vol. 51, pp. 1524-1533, Nov. 1963. 6. J. C. Candy, “A Use of Limit Oscillations to Obtain Robust Analog-to-Digital Converters, IEEE Trans. Commun., vol. COM-22, pp. 296-305, Mar. 1974. 7. S. K. Tewksbury and R. W. Hallock, “Oversampled, Linear Predictive and Noise- Shaping Coders of Order N>1,” IEEE Trans. Circuits and Sys., vol. CAS-25, pp. 436- 447, July 1978. 8. R. M. Gray, “Spectral Analysis of Quantization Noise in a Single-Loop Sigma-Delta Modulator with DC Input,” IEEE Trans. Commun., vol. 37, pp. 956-958, Sept. 1989.

Bruce A. Wooley - 73 - Stanford University, 2005 References – II

9. J. C. Candy, “A Use of Double Integration in Sigma Delta Modulation,” IEEE Trans. Commun., vol. COM-33, pp. 249-258, Mar. 1985. 10. B. P. Brandt, D. E. Wingard, and B. A. Wooley, “Second-Order Sigma-Delta Modulation for Digital-Audio Signal Acquisition,” IEEE J. Solid-State Circuits, vol. 26, pp. 618-627, Apr. 1991. 11. J. C. Candy and G. C. Temes, Oversampling Delta-Sigma Converters, IEEE Press, 1992. 12. S. R. Norsworthy, R. Schreier, G. C. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation, IEEE Press, 1997.

CASCADED ΣΔ MODULATION

9. L. Longo and M. Copeland, “A 13 bit ISDN-band Oversampled ADC using Two- Stage Third Order Noise Shaping,” IEEE Proc. Custom IC Conf., pp. 21.2.1-21.2.4, Jan. 1988. 10. Y. Matsuya, et al., “A 16-bit Oversampling A-to-D Conversion Technology Using Triple Integration Noise Shaping,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 921- 929, Dec. 1987. 11. L. A. Williams III and B. A. Wooley, “Third-Order Cascaded Sigma-Delta Modulators,” IEEE Trans. Circuits and Sys., vol. 38, pp. 489-498, May 1991.

Bruce A. Wooley - 74 - Stanford University, 2005 References – III

16. L. A. Williams III and B. A. Wooley, “A Third Order Sigma-Delta Modulator with Extended Dynamic Range,” IEEE J. Solid-State Circuits, vol. 29, pp. 193-202, Mar. 1994. 17. B. P. Brandt and B. A. Wooley, “A 50-MHz Multibit Sigma-Delta Modulator for 12-b 2- MHz A/D Conversion,” IEEE J. Solid-State Circuits, vol. 26, pp. 1746-1756, Dec. 1991. 18. S. Rabii and B. A. Wooley, “A 1.8-V Digital-Audio Sigma-Delta Modulator in 0.8-µm CMOS,” IEEE J. Solid-State Circuits, vol. 32, pp. 783-796, June 1997. 19. S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Kluwer Academic Publishers, 187 pp., 1999. 20. T. B. Cho and P. R. Gray, “A 10-b, 20 Msample/s Pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995. 21. K. Vleugels, S. Rabii, and B. A. Wooley, “A 2.5-V Sigma-Delta Modulator for Broadband Communications Applications,” IEEE J. Solid-State Circuits, vol. 36, pp. 1887-1899, Dec. 2001. 22. A. Tabatabaei and B. A. Wooley, “A Two-Path Bandpass Sigma-Delta Modulator with Extended Noise Shaping, IEEE J. Solid-State Circuits, vol. 35, pp. 1799-1809, Dec. 2000. 23. A. K. Ong and B. A. Wooley “A Two-Path Bandpass ΣΔ Modulator for Digital IF Extraction at 20 MHz,” IEEE J. Solid-State Circuits, vol. 32, pp. 1920-1934, Dec. 1997

Bruce A. Wooley - 75 - Stanford University, 2005 References – IV

DECIMATION & INTERPOLATION FILTERS

24. B. P. Brandt and B. A. Wooley, “A Low-Power, Area-Efficient Digital Filter for Decimation and Interpolation,” IEEE J. Solid-State Circuits, vol. 29, pp. 679-687, June 1994. 25. R. E. Crochiere and L. R. Rabiner, “Interpolation and Decimation of Digital Signals – A Tutorial Review,” Proc. IEEE, vol. 69, pp. 300-331, Mar. 1981.

OVERSAMPLING D-to-A CONVERSION

26. D. K. Su and B. A. Wooley, “A CMOS Oversampling D/A Converter with a Current- Mode Semi-Digital Reconstruction Filter,” IEEE J. Solid-State Circuits, vol. 28, pp. 1224-1233, Dec. 1993. 27. K. Falakshahi, C.-K. K. Yang and B. A. Wooley, “A 14-bit 10-Msamples/s D/A Converter Using Σ-Δ Modulation,” IEEE J. Solid-State Circuits, vol. 34, pp. 607-615, May 1999. 28. D. B. Barkin, A. C. Y. Lin, D. K. Su, and B. A. Wooley, “A CMOS Oversampling Bandpass Cascaded D/A Converter with Digital FIR and Current-Mode Semi- Digital Filtering,” IEEE J. Solid-State Circuits, vol. 39, pp. 585-593, Apr. 2004.

Bruce A. Wooley - 76 - Stanford University, 2005