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Intel® Quartus® Prime Standard Edition User Guide Third-Party Simulation

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Intel® Quartus® Prime Standard Edition User Guide Third-Party Simulation Intel® Quartus® Prime Standard Edition User Guide Third-party Simulation Updated for Intel® Quartus® Prime Design Suite: 18.1 Subscribe UG-20180 | 2018.09.24 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Simulating Intel FPGA Designs....................................................................................... 4 1.1. Simulator Support................................................................................................. 4 1.2. Simulation Levels.................................................................................................. 4 1.3. HDL Support......................................................................................................... 5 1.4. Simulation Flows................................................................................................... 6 1.5. Preparing for Simulation......................................................................................... 7 1.5.1. Compiling Simulation Models.......................................................................7 1.6. Simulating Intel FPGA IP Cores................................................................................8 1.6.1. Generating IP Simulation Files..................................................................... 8 1.7. Using NativeLink Simulation (Intel Quartus Prime Standard Edition)............................10 1.7.1. Setting Up NativeLink Simulation (Intel Quartus Prime Standard Edition).........10 1.7.2. Running RTL Simulation (NativeLink Flow)...................................................11 1.7.3. Running Gate-Level Simulation (NativeLink Flow)......................................... 11 1.8. Running a Simulation (Custom Flow)...................................................................... 12 1.9. Simulating Intel FPGA Designs Revision History........................................................12 2. ModelSim - Intel FPGA Edition, ModelSim, and QuestaSim............................................ 14 2.1. Quick Start Example (ModelSim with Verilog)...........................................................14 2.2. ModelSim, ModelSim-Intel FPGA Edition, and QuestaSim Guidelines............................15 2.2.1. Using ModelSim-Intel FPGA Edition Precompiled Libraries.............................. 15 2.2.2. Disabling Timing Violation on Registers....................................................... 15 2.2.3. Passing Parameter Information from Verilog HDL to VHDL............................. 16 2.2.4. Increasing Simulation Speed..................................................................... 16 2.2.5. Simulating Transport Delays...................................................................... 16 2.2.6. Viewing Simulation Messages.................................................................... 17 2.2.7. Generating Power Analysis Files................................................................. 18 2.2.8. Viewing Simulation Waveforms.................................................................. 18 2.2.9. Simulating with ModelSim-Intel FPGA Edition Waveform Editor.......................19 2.3. ModelSim Simulation Setup Script Example............................................................. 19 2.4. Unsupported Features.......................................................................................... 20 2.5. ModelSim - Intel FPGA Edition, ModelSim, and QuestaSim Revision History..................20 3. Synopsys VCS and VCS MX Support...............................................................................21 3.1. Quick Start Example (VCS with Verilog).................................................................. 21 3.2. VCS and VCS MX Guidelines.................................................................................. 21 3.2.1. Simulating Transport Delays...................................................................... 22 3.2.2. Disabling Timing Violation on Registers....................................................... 22 3.2.3. Generating Power Analysis Files................................................................. 23 3.3. VCS Simulation Setup Script Example.....................................................................23 3.4. Synopsys VCS and VCS MX Support Revision History................................................ 24 4. Cadence Simulator Support...........................................................................................25 4.1. Quick Start Example (NC-Verilog)...........................................................................25 4.2. Using GUI or Command-Line Interfaces.................................................................. 26 4.3. Cadence Incisive Enterprise (IES) Guidelines........................................................... 26 4.3.1. Elaborating Your Design............................................................................ 26 4.3.2. Back-Annotating Simulation Timing Data (VHDL Only)...................................27 4.3.3. Disabling Timing Violation on Registers....................................................... 27 Intel Quartus Prime Standard Edition User Guide: Third-party Simulation Send Feedback 2 Contents 4.3.4. Simulating Pulse Reject Delays.................................................................. 27 4.3.5. Viewing Simulation Waveforms.................................................................. 28 4.4. IES Simulation Setup Script Example......................................................................28 4.5. Cadence Simulator Support Revision History............................................................29 5. Aldec Active-HDL and Riviera-PRO * Support................................................................30 5.1. Quick Start Example (Active-HDL VHDL)................................................................. 30 5.2. Aldec Active-HDL and Riviera-PRO Guidelines.......................................................... 31 5.2.1. Compiling SystemVerilog Files................................................................... 31 5.2.2. Simulating Transport Delays...................................................................... 31 5.2.3. Disabling Timing Violation on Registers....................................................... 31 5.3. Using Simulation Setup Scripts.............................................................................. 32 5.4. Aldec Active-HDL and Riviera-PRO * Support Revision History....................................32 A. Intel Quartus Prime Standard Edition User Guides........................................................33 Send Feedback Intel Quartus Prime Standard Edition User Guide: Third-party Simulation 3 UG-20180 | 2018.09.24 Send Feedback 1. Simulating Intel FPGA Designs This document describes simulating designs that target Intel FPGA devices. Simulation verifies design behavior before device programming. The Intel® Quartus® Prime software supports RTL- and gate-level design simulation in supported EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation. 1.1. Simulator Support The Intel Quartus Prime software supports specific EDA simulator versions for RTL and gate-level simulation. Table 1. Supported Simulators Vendor Simulator Version Platform Aldec Active-HDL* 10.3 Windows Aldec Riviera-PRO* 2015.10 Windows, Linux Cadence Incisive Enterprise* 14.20 Linux Mentor Graphics* ModelSim* - Intel FPGA Edition 10.5b Windows, Linux Mentor Graphics ModelSim PE 10.4d Windows Mentor Graphics ModelSim SE 10.4d Windows, Linux Mentor Graphics QuestaSim* 10.4d Windows, Linux Synopsys* VCS* 2014,12-SP1 Linux VCS MX 1.2. Simulation Levels The Intel Quartus Prime software supports RTL and gate-level simulation of IP cores in supported EDA simulators. Table 2. Supported Simulation Levels Simulation Level Description Simulation Input RTL Cycle-accurate simulation using Verilog HDL, • Design source/testbench SystemVerilog, and VHDL design source code with • Intel simulation libraries simulation models provided by Intel and other IP • Intel FPGA IP plain text or IEEE providers. encrypted RTL models • IP simulation models • Intel FPGA IP functional simulation models continued... Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 1. Simulating Intel FPGA Designs UG-20180 | 2018.09.24 Simulation Level Description Simulation Input • Intel FPGA IP bus functional models • Platform Designer (Standard)- generated models • Verification IP Gate-level functional Simulation using a post-synthesis or post-fit • Testbench functional netlist testing the post-synthesis • Intel simulation libraries functional
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