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Media Engines Intel® Iris® Xe MAX Graphics Open Source Programmer's Reference Manual For the 2020 Discrete GPU formerly named "DG1" Volume 11: Media Engines February 2021, Revision 1.0 Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Code names are used by Intel to identify products, technologies, or services that are in development and not publicly available. These are not "commercial" names and not intended to function as trademarks. Customer is responsible for safety of the overall system, including compliance with applicable safety- related requirements or standards. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. ii Doc Ref # IHD-OS-DG1-Vol 11-2.21 Table of Contents Media Engines .............................................................................................................................. 1 Media VDBOX ............................................................................................................................................................ 1 AVP ............................................................................................................................................................................ 1 AVP Command Sequence Examples for Decoder .................................................................................. 4 Video Command Streamer (VCS) .................................................................................................................. 8 HCP.......................................................................................................................................................................... 16 VP9 Decoder Command Sequence........................................................................................... 36 MFX Pipe ............................................................................................................................................................... 85 Session Decoder StreamOut Data Structure ............................................................................................ 143 AVC Encoder MBAFF Support ................................................................................................................... 201 VDBOX Registers ............................................................................................................................................ 252 Media VEBOX ........................................................................................................................................................ 253 Media VEBOX Introduction ......................................................................................................................... 253 SFC ............................................................................................................................................................................ 260 SFC Overview .................................................................................................................................................... 260 SFC Commands Definition .......................................................................................................................... 260 Doc Ref # IHD-OS-DG1-Vol 11-2.21 iii Media Engines Media VDBOX This chapter describes the VDBOX Media Engine. AVP The AV1 Codec Pipeline (AVP) is a fixed function hardware video codec responsible for decoding AV1 (AOMedia Video 1) video streams. AVP Register Definitions The Message Channel Interface is a read-only bus used to access the AVP status registers. All registers are 32 bits where reserved bits return a value of zero and subtractive-decode is used to return 0x0000 for all register holes. Register Attributes Description Host Register Attributes gives the defined register tags and their description. Host Register Attributes Tag Name Description R/W Read/Write Bit is read and writeable. R/SW Read/Special Write Bit is readable. Write is only allowed once after a reset. RO Read Only Bit is only readable, but writes have no effects. WO Write Only Bit is only writeable, reads return zeros. RV Reserved Bit is reserved and not visible. Reads will return 0, and writes have no effect. NA Not Accessible This bit is not accessible. AVP Decoder Register Map This documents all AVP Decoder MMIO Registers. AVP Decoder Register Descriptions Reserved. AVP Command Summary The AV1 is configured through a set of batch commands defined in the following sections. The software driver builds a frame level workload using these commands and stores these workloads in graphics memory where they are fetched by the Video Command Streamer (VCS) and presented to the AVP for processing. The commands are processed by the Workload Parser within the AVP and the hardware is Doc Ref # IHD-OS-DG1-Vol 11-2.21 1 configured by the Workload Parser prior to each frame level encode or decode. A workload is defined as a set of commands necessary to encode or decode one frame. The software driver is required to read the AVP disable fuse to determine if the AVP is enabled. If it is disabled, then the software driver must not enable AVP batch commands to be sent to the AVP or a hang event may occur. Only when the AVP is enabled through the fuse, should the batch commands be sent to the AVP. AVP Workload Command Model DWord0 of each command is defined in AVP DWord0 Command Definition. The AVP is selected with the Media Instruction Opcode "8h" for all AVP Commands. HCP DWord0 Command Definition DWord Bits Description 0 31:29 Command Type = PARALLEL_VIDEO_PIPE = 3h 28:27 Pipeline Type = 2h 26:23 Media Instruction Opcode = Codec/Engine Name = AVP = 8h 22:16 Media Instruction Command = <see HCP Media Instruction Commands (Opcode=7h)> 15:12 Reserved: MBZ 11:0 Dword Length (Excludes Dwords 0, 1) = <command length> Each AVP command has assigned a media instruction command as defined in AVP Media Instruction Commands (Opcode=8h). AVP Media Instruction Commands (Opcode=8h) Media Instruction Command Command DWord0 [22:16] Mode Scope Dec Picture AVP_PIPE_MODE_SELECT 0h Dec Picture AVP_SURFACE_STATE 1h Dec Picture AVP_PIPE_BUF_ADDR_STATE 2h Dec Picture AVP_IND_OBJ_BASE_ADDR_STATE 3h Reserved 4h-5h Reserved 8h-9h 2 Doc Ref # IHD-OS-DG1-Vol 11-2.21 Media Instruction Command Command DWord0 [22:16] Mode Scope VD_CONTROL_STATE Ah Dec Picture Reserved Bh-Fh AVP_PIC_STATE 10h Dec Picture Reserved 11h AVP_REF_IDX_STATE 12h Dec Tile Reserved 13h-14h AVP_TILE_CODING 15h Dec Tile Reserved 16h-1Fh AVP_BSD_OBJECT_STATE 20h Dec Tile Reserved 21h-31h Reserved 33h-7Fh AVP Command Sequence The AV1 is configured for encoding or decoding through a set of batch commands defined in the following sections. The software driver builds a frame level workload using these commands and stores these workloads in graphics memory where they are fetched by the Video Command Streamer (VCS) and presented to the AVP for processing. The commands are processed by the Workload Parser within the AVP and the hardware is configured by the Workload Parser prior to each frame level encode or decode. A workload is defined as a set of commands necessary to encode or decode one frame. The software driver is required to read the AVP disable fuse to determine if the AVP is enabled. If it is disabled, then the software driver must not enable AVP batch commands to be sent to the AVP or a hang event may occur. Only when the AVP is enabled through the fuse, should the batch commands be sent to the AVP. Doc Ref # IHD-OS-DG1-Vol 11-2.21 3 AVP Command Sequence Examples for Decoder AV1 workload is based upon a single tile decode. There are no states saved between tile decodes in the AVP. The following programming sequence will be used by single pipe decode. <<Start Workload>> | VD_CONTROL (AVP_Pipe_Initialization) AVP PIpe Reset | AVP_PIPE_MODE_SELECT AVP Pipe Setup | AVP_SURFACE_STATE (Multiple) Frame Level Commands AVP_PIPE_BUF_ADDR_STATE Frame Level Commands AVP_IND_OBJ_BASE_ADDR_STATE Frame Level Commands AVP_PIC_STATE
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