DOCSLIB.ORG

Volume 10: HEVC Codec Pipeline (HCP)

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Volume 10: HEVC Codec Pipeline (HCP) Intel® Open Source HD Graphics, Intel Iris™ Graphics, and Intel Iris™ Pro Graphics Programmer's Reference Manual For the 2015 - 2016 Intel Core™ Processors, Celeron™ Processors, and Pentium™ Processors based on the "Skylake" Platform Volume 10: HEVC Codec Pipeline (HCP) May 2016, Revision 1.0 HEVC Creative Commons License You are free to Share - to copy, distribute, display, and perform the work under the following conditions: Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any way that suggests that they endorse you or your use of the work). No Derivative Works. You may not alter, transform, or build upon this work. Notices and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. * Other names and brands may be claimed as the property of others. Copyright © 2016, Intel Corporation. All rights reserved. ii Doc Ref # IHD-OS-SKL-Vol 10-05.16 HEVC Table of Contents High Efficiency Video Coding (HEVC) Introduction .................................................................. 1 Scope ............................................................................................................................................................................ 1 Summary of Features ..................................................................................................................... 1 HCP Hardware Pipeline Features ....................................................................................................................... 1 HEVC Decoder Features......................................................................................................................................... 2 HEVC Encoder Features ......................................................................................................................................... 2 HCP Command Summary .............................................................................................................. 2 Workload Command Model ................................................................................................................................ 2 HCP Decoder Command Sequence ......................................................................................................... 3 HCP Encoder Command Sequence ......................................................................................................... 4 Memory Address Attributes ................................................................................................................................. 6 HCP Pipe Common Commands ......................................................................................................................... 7 Buffer Size Requirements ...................................................................................................................................... 9 HCP Common Commands.................................................................................................................................. 11 Tile Size and CU Stream-out Records ....................................................................................................... 11 Stream-in Probability Table ............................................................................................................................. 1 Stream-in formats for creating compressed header ............................................................................. 1 SB, CU/PU and TU Sizes – Encoder Only .................................................................................................... 2 Allowed SB Size Encoder Only ....................................................................................................................... 2 HCP Commands ........................................................................................................................................................ 2 Multipass flow during BRC and SAO ........................................................................................................... 3 CU and Slice level stat streamOut................................................................................................................. 4 Definition of the CU Record Structure for Ext Interface – Encoder Only....................................... 5 LCU, CU, TU, and PU Sizes – Encoder Only ............................................................................................... 9 Allowed LCU Size – Encoder Only ............................................................................................................... 12 HEVC Error Concealment ............................................................................................................. 12 HEVC Register Definitions ........................................................................................................... 14 Register Attributes Description ........................................................................................................................ 14 HCP Decoder Register Map ............................................................................................................................... 14 HCP Decoder Register Descriptions ............................................................................................................... 14 HCP Encoder Register Map ................................................................................................................................ 14 HCP Encoder Register Descriptions ................................................................................................................ 14 Doc Ref # IHD-OS-SKL-Vol 10-05.16 iii HEVC Acronyms and Applicable Standards ......................................................................................... 15 Acronyms and Abbreviations ............................................................................................................................ 15 iv Doc Ref # IHD-OS-SKL-Vol 10-05.16 HEVC High Efficiency Video Coding (HEVC) Introduction The HEVC Codec Pipeline (HCP) is a fixed function hardware video codec responsible for decoding and encoding HEVC (High Efficiency Video Coding) video streams. Scope The primary scope of the HCP BSpec document is to provide a description of the HCP commands processed by the Video Command Streamer (VCS). The secondary scope is to provide a description of the status registers on the Message Channel Interface to support encoding and decoding of the HEVC video format. The BSpec sections include: Summary of Features Architecture Overview Commands Register Definitions Acronyms and Applicable Standards Summary of Features The following sections define the HEVC Decoder and Encoder general features and the features specific to HEVC decoding and encoding, respectively. HCP Hardware Pipeline Features Supports both decoder and encoder functions, setup on a per picture basis: Hardware acceleration provides Ctb/CU level decode and encode. No context switch is supported within a frame process. Supports Video Command Streamer (VCS): Shared with MFX HW pipeline, and at any one time, only one pipeline (MFX or HCP) and one operation (decoding or encoding) can be active. Supports Message Channel Interface: Feature Supports Tile-YS and Tile-YF. Supports
Load more

Recommended publications
  • Animatsiooni Töövõtted Ja Terminid
    Multimeedium, 2D animatsioon Animatsiooni töövõtted ja terminid Nii 2D kui ka 3D animatsioonide juures kasutatakse mitmeid samu võtteid ja termineid. Mõned neist on järgnevas lahtiseletatud. Keyframe Keyframe ehk võtmekaader on selline kaader, millel autor määrab objekti(de) täpse asukoha, suuruse, kuju, värvuse jms. antud ajahetkel. Kaadrid kahe keyframe vahel genereeritakse tavaliselt animatsiooniprogrammi poolt Keyframe 1 Keyframe 2 keerukate arvutuste tulemusena. Traditsioonilise animeerimise korral joonistavad peakunstnikud vajalikud keyframe'id ning nende assistendid kõik ülejäänu. Tracing Tracing on meetod uue kaadri loomiseks eelmise või vahel ka järgmise kopeerimise (trace) teel. Kopeeritava kujutise näitamiseks kasutatakse mitmeid meetodeid, sealhulgas aluseks oleva kujutise näitamine teise värviga, sageli sinisega. Tweening Tweening on tehnika, mis etteantud keyframe'ide vahele genereerib kasutaja poolt etteantud arvu kaadreid, millede jooksul toimub järkjärguline üleminek esimeselt keyframe'ilt teisele. Võttes arvesse kahe keyframe'i erinevusi, kalkuleerib arvuti iga kaadri jaoks proportsionaalsed muudatused objektide asukoha, suuruse, värvuse, kuju jms jaoks. Mida rohkem kaadreid lastakse genereerida, seda väiksemad tulevad järjestikuste kaadrite vahelised erinevused ning seda sujuvam tuleb liikumine. Keyframe 1 genereeritud kaadrid Keyframe 2 Rendering Rendering on protsess, mille käigus objektide traatmudelid (wireframe vahel ka mesh) kaetakse pinnatekstuuridega, neile lisatakse valgusefektid ja värvid, et saada realistlik
    [Show full text]
  • Intel® Desktop Board DG965PZ Technical Product Specification
    Intel® Desktop Board DG965PZ Technical Product Specification August 2006 Order Number: D56009-001US The Intel® Desktop Board DG965PZ may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in the Intel Desktop Board DG965PZ Specification Update. Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DG965PZ Technical Product August 2006 Specification. This product specification applies to only the standard Intel® Desktop Board DG965PZ with BIOS identifier MQ96510A.86A. Changes to this specification will be published in the Intel Desktop Board DG965PZ Specification Update before being incorporated into a revision of this document. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
    [Show full text]
  • NVIDIA's Fermi: the First Complete GPU Computing Architecture
    NVIDIA’s Fermi: The First Complete GPU Computing Architecture A white paper by Peter N. Glaskowsky Prepared under contract with NVIDIA Corporation Copyright © September 2009, Peter N. Glaskowsky Peter N. Glaskowsky is a consulting computer architect, technology analyst, and professional blogger in Silicon Valley. Glaskowsky was the principal system architect of chip startup Montalvo Systems. Earlier, he was Editor in Chief of the award-winning industry newsletter Microprocessor Report. Glaskowsky writes the Speeds and Feeds blog for the CNET Blog Network: http://www.speedsnfeeds.com/ This document is licensed under the Creative Commons Attribution ShareAlike 3.0 License. In short: you are free to share and make derivative works of the file under the conditions that you appropriately attribute it, and that you distribute it only under a license identical to this one. http://creativecommons.org/licenses/by-sa/3.0/ Company and product names may be trademarks of the respective companies with which they are associated. 2 Executive Summary After 38 years of rapid progress, conventional microprocessor technology is beginning to see diminishing returns. The pace of improvement in clock speeds and architectural sophistication is slowing, and while single-threaded performance continues to improve, the focus has shifted to multicore designs. These too are reaching practical limits for personal computing; a quad-core CPU isn’t worth twice the price of a dual-core, and chips with even higher core counts aren’t likely to be a major driver of value in future PCs. CPUs will never go away, but GPUs are assuming a more prominent role in PC system architecture.
    [Show full text]
  • This Thesis Has Been Submitted in Fulfilment of the Requirements for a Postgraduate Degree (E.G
    This thesis has been submitted in fulfilment of the requirements for a postgraduate degree (e.g. PhD, MPhil, DClinPsychol) at the University of Edinburgh. Please note the following terms and conditions of use: This work is protected by copyright and other intellectual property rights, which are retained by the thesis author, unless otherwise stated. A copy can be downloaded for personal non-commercial research or study, without prior permission or charge. This thesis cannot be reproduced or quoted extensively from without first obtaining permission in writing from the author. The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the author. When referring to this work, full bibliographic details including the author, title, awarding institution and date of the thesis must be given. ENHANCINGPRODUCTIVITYANDPERFORMANCE PORTABILITYOFOPENCLAPPLICATIONSON HETEROGENEOUSSYSTEMSUSINGRUNTIME OPTIMIZATIONS thibaut lutz Doctor of Philosophy School of Informatics Institute of Computing Systems Architecture University of Edinburgh 2015 Copyright © Thibaut Lutz 2014 Enhancing Productivity and Performance Portability of OpenCL Applications on Heterogeneous Systems Using Runtime Optimizations ABSTRACT Initially driven by a strong need for increased computational performance in science and engineering, heterogeneous systems have become ubiquitous and they are getting increas- ingly complex. The single processor era has been replaced with multi-core processors, which have quickly been surrounded by satellite devices aiming to increase the throughput of the entire system. These auxiliary devices, such as Graphics Processing Units, Field Pro- grammable Gate Arrays or other specialized processors have very different architectures. This puts an enormous strain on programming models and software developers to take full advantage of the computing power at hand.
    [Show full text]
  • Intel's Atom Lines 1. Introduction to Intel's Atom Lines 3. Atom-Based Platforms Targeting Entry Level Desktops and Notebook
    Intel’s Atom lines • 1. Introduction to Intel’s Atom lines • 2. Intel’s low-power oriented CPU micro-architectures • 3. Atom-based platforms targeting entry level desktops and notebooks • 4. Atom-based platforms targeting tablets • 5. Atom-based platforms targeting smartphones • 6. Intel’s withdrawal from the mobile market • 7. References 1. Introduction to Intel’s Atom lines • 1.1 The rapidly increasing importance of the mobile market space • 1.2 Related terminology • 1.3 Introduction to Intel’s low-power Atom series 1.1 The rapidly increasing importance of the mobile market space 1.1 The rapidly increasing importance of the mobile market space (1) 1.1 The rapidly increasing importance of the mobile market space Diversification of computer market segments in the 2000’s Main computer market segments around 2000 Servers Desktops Embedded computer devices E.g. Intel’s Xeon lines Intel’s Pentium 4 lines ARM’s lines AMD’s Opteron lines AMD’s Athlon lines Major trend in the first half of the 2000’s: spreading of mobile devices (laptops) Main computer market segments around 2005 Servers Desktops Mobiles Embedded computer devices E.g. Intel’s Xeon lines Intel’s Pentium 4 lines Intel’s Celeron lines ARM’s lines AMD’s Opteron lines AMD’s Athlon64 lines AMD’s Duron lines 1.1 The rapidly increasing importance of the mobile market space (2) Yearly worldwide sales and Compound Annual Growth Rates (CAGR) of desktops and mobiles (laptops) around 2005 [1] 350 300 Millions 250 CAGR 17% 200 Mobile 150 100 Desktop CAGR 5% 50 0 2003 2004 2005 2006 2007 2008
    [Show full text]
  • USER's MANUAL of Intel 945GM Express Chipset Intel FW82801GBM
    USER'S MANUAL of Intel 945GM Express Chipset & Intel FW82801GBM ICH Chipset Based M/B For Socket479 Mobile Processor NO. G03-9F2-F Rev：3.0 Release date: July 2007 Trademark: * Specifications and Information contained in this documentation are furnished for information use only, and are subject to change at any time without notice, and should not be construed as a commitment by manufacturer. ii Environmental Protection Announcement Do not dispose this electronic device into the trash while discarding. To minimize pollution and ensure environment protection of mother earth, please recycle. iii TABLE OF CONTENT USER’S NOTICE .................................................................................................................................. iii MANUAL REVISION INFORMATION ............................................................................................ iii ITEM CHECKLIST.............................................................................................................................. iii CHAPTER 1 INTRODUCTION OF MOTHERBOARD 1-1 FEATURE OF MOTHERBOARD ...................................................................................... 1 1-2 SPECIFICATION.................................................................................................................. 2 1-3 LAYOUT DIAGRAM & JUMPER SETTING................................................................... 3 CHAPTER 2 HARDWARE INSTALLATION 2-1 HARDWARE INSTALLATION STEPS............................................................................
    [Show full text]
  • Intel® Technology Journal | Volume 18, Issue 2, 2014
    Intel® Technology Journal | Volume 18, Issue 2, 2014 Publisher Managing Editor Content Architect Cory Cox Stuart Douglas Paul Cohen Program Manager Technical Editor Technical Illustrators Paul Cohen David Clark MPS Limited Technical and Strategic Reviewers Bruce J Beare Tracey Erway Michael Richmond Judi A Goldstein Kira C Boyko Miao Wei Paul De Carvalho Ryan Tabrah Prakash Iyer Premanand Sakarda Ticky Thakkar Shelby E Hedrick Intel® Technology Journal | 1 Intel® Technology Journal | Volume 18, Issue 2, 2014 Intel Technology Journal Copyright © 2014 Intel Corporation. All rights reserved. ISBN 978-1-934053-63-8, ISSN 1535-864X Intel Technology Journal Volume 18, Issue 2 No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4744. Requests to the Publisher for permission should be addressed to the Publisher, Intel Press, Intel Corporation, 2111 NE 25th Avenue, JF3-330, Hillsboro, OR 97124-5961. E-Mail: [email protected]. Th is publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold with the understanding that the publisher is not engaged in professional services. If professional advice or other expert assistance is required, the services of a competent professional person should be sought.
    [Show full text]
  • Graphics and Multimedia
    DEPARTMENT OF IT IT6501 – GRAPHICS AND MULTIMEDIA DEPARTMENT OF IT IT6501 – GRAPHICS AND MULTIMEDIA L T P C 3 1 0 4 UNIT I OUTPUT PRIMITIVES 9 Basic − Line − Curve and ellipse drawing algorithms − Attributes − Two-Dimensional geometric transformations − Two-Dimensional clipping and viewing –Input techniques. UNIT II THREE-DIMENSIONAL CONCEPTS 9 Three-Dimensional object representations − Three-Dimensional geometric and modeling transformations − Three-Dimensional viewing − Hidden surface elimination− Color models − Animation. UNIT III MULTIMEDIA SYSTEMS DESIGN 9 Multimedia basics − Multimedia applications − Multimedia system architecture −Evolving technologies for multimedia − Defining objects for multimedia systems −Multimedia data interface standards − Multimedia databases. UNIT IV MULTIMEDIA FILE HANDLING 9 Compression and decompression − Data and file format standards − Multimedia I/Otechnologies − Digital voice and audio − Video image and animation − Full motionvideo − Storage and retrieval technologies. UNIT V HYPERMEDIA 9 Multimedia authoring and user interface − Hypermedia messaging − Mobilemessaging − Hypermedia message component − Creating hypermedia message −Integrated multimedia message standards − Integrated document management −Distributed multimedia systems. L:45 T:15 Total : 60 TEXT BOOKS 1. Donald Hearn and M. Pauline Baker, “Computer Graphics C Version”,Pearson Education, 2003. 2. Andleigh, P. K and Kiran Thakrar, “Multimedia Systems and Design”, PHI,2003. REFERENCES 1. Judith Jeffcoate, “Multimedia in practice: Technology and Applications”, PHI,1998. 2. Foley, Vandam, Feiner and Huges, “Computer Graphics: Principles and Practice”, 2nd Edition, Pearson Education, 2003. UNIT I OUTPUT PRIMITIVES 9 Basic − Line − Curve and ellipse drawing algorithms − Attributes − Two-Dimensional geometric transformations − Two-Dimensional clipping and viewing –Input techniques. BASICS Computer graphics is a sub-field of computer science and is concerned with digitally synthesizing and manipulating visual content.
    [Show full text]
  • ETR 084 TECHNICAL June 1993 REPORT
    ETSI ETR 084 TECHNICAL June 1993 REPORT Source:ETSI TC-TE Reference:DTR/TE-01017 ICS: 33.020, 33.040.40 Key words: Interactive services, multimedia, hypermedia Terminal Equipment (TE); Multimedia & Hypermedia Information Retrieval Services (M&HIRS) Investigation of candidate architectures for M&HIRS ETSI European Telecommunications Standards Institute ETSI Secretariat Postal address: F-06921 Sophia Antipolis CEDEX - FRANCE Office address: 650 Route des Lucioles - Sophia Antipolis - Valbonne - FRANCE X.400: c=fr, a=atlas, p=etsi, s=secretariat - Internet: [email protected] Tel.: +33 92 94 42 00 - Fax: +33 93 65 47 16 Copyright Notification: No part may be reproduced except as authorized by written permission. The copyright and the foregoing restriction extend to reproduction in all media. New presentation - see History box © European Telecommunications Standards Institute 1993. All rights reserved. Page 2 ETR 084:June 1993 Whilst every care has been taken in the preparation and publication of this document, errors in content, typographical or otherwise, may occur. If you have comments concerning its accuracy, please write to "ETSI Editing and Committee Support Dept." at the address shown on the title page. Page 3 ETR 084:June 1993 Contents Foreword .......................................................................................................................................................7 1 Scope ..................................................................................................................................................9
    [Show full text]
  • Media Engines
    Intel® Iris® Xe MAX Graphics Open Source Programmer's Reference Manual For the 2020 Discrete GPU formerly named "DG1" Volume 11: Media Engines February 2021, Revision 1.0 Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Code names are used by Intel to identify products, technologies, or services that are in development and not publicly available. These are not "commercial" names and not intended to function as trademarks. Customer is responsible for safety of the overall system, including compliance with applicable safety- related requirements or standards. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined".
    [Show full text]
  • (12) United States Patent (10) Patent No.: US 8,848,792 B2 Macinnis Et Al
    USOO8848792B2 (12) United States Patent (10) Patent No.: US 8,848,792 B2 MacInnis et al. (45) Date of Patent: *Sep. 30, 2014 (54) VIDEO AND GRAPHICS SYSTEM WITH H04N 2 1/42653 (2013.01); G09G 5/346 VIDEO. SCALING (2013.01); G09G 2.360/02 (2013.01); (75) Inventors: Alexander MacInnis, Los Altos, CA (Continued) (US); Chengfuh Jeffrey Tang, Saratoga, (58) Field of Classification Search CA (US); Xiaodong Xie, San Jose, CA CPC ...... H04N 7/50; H04N 7/462; H04N 7/26244 (US); Vivian Hsiun, Palo Alto, CA (US) USPC ........................................ 375/240.15, 240.25 See application file for complete search history. (73) Assignee: Broadcom Corporation, Irvine, CA (56) References Cited (US) U.S. PATENT DOCUMENTS (*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 4,020,332 A 4, 1977 Crochiere et al. U.S.C. 154(b) by 322 days. 4,367,466 A 1/1983 Takeda et al. This patent is Subject to a terminal dis (Continued) claimer. FOREIGN PATENT DOCUMENTS (21) Appl. No.: 13/195,115 EP O746116 12/1996 EP O752695 1, 1997 Filed: Aug. 1, 2011 (22) (Continued) (65) Prior Publication Data OTHER PUBLICATIONS US 2011 FO28O3O7 A1 Nov. 17, 2011 Plaintiff and Counterdefendant Qualcomm Incorporated's Prelimi Related U.S. Application Data nary Invalidity Contentions for U.S. Patent 6,501,480 and 6,570,579. (Continued) (63) Continuation of application No. 10/843,657, filed on May 11, 2004, now Pat. No. 7.991,049, which is a Primary Examiner — Nhon Diep (Continued) (74) Attorney, Agent, or Firm — Foley & Lardner LLP (57) ABSTRACT (51) Int.
    [Show full text]
  • High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems
    High-Performance and Energy-Ecient Memory Scheduler Design for Heterogeneous Systems Rachata Ausavarungnirun1 Gabriel H. Loh2 Lavanya Subramanian3,1 Kevin Chang4,1 Onur Mutlu5,1 1Carnegie Mellon University 2AMD Research 3Intel Labs 4Facebook 5ETH Zürich This paper summarizes the idea of the Staged Memory Sched- 1. Introduction uler (SMS), which was published at ISCA 2012 [14], and exam- ines the work’s signicance and future potential. When multiple As the number of cores continues to increase in modern processor cores (CPUs) and a GPU integrated together on the chip multiprocessor (CMP) systems, the DRAM memory sys- same chip share the o-chip DRAM, requests from the GPU tem has become a critical shared resource [139, 145]. Mem- can heavily interfere with requests from the CPUs, leading to ory requests from multiple cores interfere with each other, low system performance and starvation of cores. Unfortunately, and this inter-application interference is a signicant im- state-of-the-art memory scheduling algorithms are ineective pediment to individual application and overall system perfor- at solving this problem due to the very large amount of GPU mance. Various works on application-aware memory schedul- memory trac, unless a very large and costly request buer ing [98,99,141,142] address the problem by making the mem- is employed to provide these algorithms with enough visibility ory controller aware of application characteristics and ap- across the global request stream. propriately prioritizing memory requests to improve system performance and fairness. Previously-proposed memory controller (MC) designs use a Recent heterogeneous CPU-GPU systems [1,27,28,37,76, single monolithic structure to perform three main tasks.
    [Show full text]