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Reverse Engineering Power Management on NVIDIA Gpus - Anatomy of an Autonomic-Ready System Martin Peres
Reverse Engineering Power Management on NVIDIA GPUs - Anatomy of an Autonomic-ready System Martin Peres To cite this version: Martin Peres. Reverse Engineering Power Management on NVIDIA GPUs - Anatomy of an Autonomic-ready System. ECRTS, Operating Systems Platforms for Embedded Real-Time appli- cations 2013, Jul 2013, Paris, France. hal-00853849 HAL Id: hal-00853849 https://hal.archives-ouvertes.fr/hal-00853849 Submitted on 23 Aug 2013 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Reverse engineering power management on NVIDIA GPUs - Anatomy of an autonomic-ready system Martin Peres Ph.D. student at LaBRI University of Bordeaux Hobbyist Linux/Nouveau Developer Email: [email protected] Abstract—Research in power management is currently limited supported nor documented by NVIDIA. As GPUs are leading by the fact that companies do not release enough documentation the market in terms of performance-per-Watt [3], they are or interfaces to fully exploit the potential found in modern a good candidate for a reverse engineering effort of their processors. This problem is even more present in GPUs despite power management features. The choice of reverse engineering having the highest performance-per-Watt ratio found in today’s NVIDIA’s power management features makes sense as they processors. -
GPU Developments 2018
GPU Developments 2018 2018 GPU Developments 2018 © Copyright Jon Peddie Research 2019. All rights reserved. Reproduction in whole or in part is prohibited without written permission from Jon Peddie Research. This report is the property of Jon Peddie Research (JPR) and made available to a restricted number of clients only upon these terms and conditions. Agreement not to copy or disclose. This report and all future reports or other materials provided by JPR pursuant to this subscription (collectively, “Reports”) are protected by: (i) federal copyright, pursuant to the Copyright Act of 1976; and (ii) the nondisclosure provisions set forth immediately following. License, exclusive use, and agreement not to disclose. Reports are the trade secret property exclusively of JPR and are made available to a restricted number of clients, for their exclusive use and only upon the following terms and conditions. JPR grants site-wide license to read and utilize the information in the Reports, exclusively to the initial subscriber to the Reports, its subsidiaries, divisions, and employees (collectively, “Subscriber”). The Reports shall, at all times, be treated by Subscriber as proprietary and confidential documents, for internal use only. Subscriber agrees that it will not reproduce for or share any of the material in the Reports (“Material”) with any entity or individual other than Subscriber (“Shared Third Party”) (collectively, “Share” or “Sharing”), without the advance written permission of JPR. Subscriber shall be liable for any breach of this agreement and shall be subject to cancellation of its subscription to Reports. Without limiting this liability, Subscriber shall be liable for any damages suffered by JPR as a result of any Sharing of any Material, without advance written permission of JPR. -
Panstamps Documentation Release V0.5.3
panstamps Documentation Release v0.5.3 Dave Young 2020 Getting Started 1 Installation 3 1.1 Troubleshooting on Mac OSX......................................3 1.2 Development...............................................3 1.2.1 Sublime Snippets........................................4 1.3 Issues...................................................4 2 Command-Line Usage 5 3 Documentation 7 4 Command-Line Tutorial 9 4.1 Command-Line..............................................9 4.1.1 JPEGS.............................................. 12 4.1.2 Temporal Constraints (Useful for Moving Objects)...................... 17 4.2 Importing to Your Own Python Script.................................. 18 5 Installation 19 5.1 Troubleshooting on Mac OSX...................................... 19 5.2 Development............................................... 19 5.2.1 Sublime Snippets........................................ 20 5.3 Issues................................................... 20 6 Command-Line Usage 21 7 Documentation 23 8 Command-Line Tutorial 25 8.1 Command-Line.............................................. 25 8.1.1 JPEGS.............................................. 28 8.1.2 Temporal Constraints (Useful for Moving Objects)...................... 33 8.2 Importing to Your Own Python Script.................................. 34 8.2.1 Subpackages.......................................... 35 8.2.1.1 panstamps.commonutils (subpackage)........................ 35 8.2.1.2 panstamps.image (subpackage)............................ 35 8.2.2 Classes............................................ -
Mali-400 MP: a Scalable GPU for Mobile Devices
Mali-400 MP: A Scalable GPU for Mobile Devices Tom Olson Director, Graphics Research, ARM Outline . ARM and Mobile Graphics . Design Constraints for Mobile GPUs . Mali Architecture Overview . Multicore Scaling in Mali-400 MP . Results 2 About ARM . World’s leading supplier of semiconductor IP . Processor Architectures and Implementations . Related IP: buses, caches, debug & trace, physical IP . Software tools and infrastructure . Business Model . License fees . Per-chip royalties . Graphics at ARM . Acquired Falanx in 2006 . ARM Mali is now the world’s most widely licensed GPU family 3 Challenges for Mobile GPUs . Size . Power . Memory Bandwidth 4 More Challenges . Graphics is going into “anything that has a screen” . Mobile . Navigation . Set Top Box/DTV . Automotive . Video telephony . Cameras . Printers . Huge range of form factors, screen sizes, power budgets, and performance requirements . In some applications, a huge difference between peak and average performance requirements 5 Solution: Scalability . Address a wide variety of performance points and applications with a single IP and a single software stack. Need static scalability to adapt to different peak requirements in different platforms / markets . Need dynamic scalability to reduce power when peak performance isn’t needed 6 Options for Scalability . Fine-grained: Multiple pipes, wide SIMD, etc . Proven approach, efficient and effective . But, adding pipes / lanes is invasive . Hard for IP licensees to do on their own . And, hard to partition to provide dynamic scalability . Coarse-grained: Multicore . Easy for licensees to select desired performance . Putting cores on separate power islands allows dynamic scaling 7 Mali 400-MP Top Level Architecture Asynch Mali-400 MP Top-Level APB Geometry Pixel Processor Pixel Processor Pixel Processor Pixel Processor Processor #1 #2 #3 #4 CLKs MaliMMUs RESETs IRQs IDLEs MaliL2 AXI . -
Intel Desktop Board DG41MJ Product Guide
Intel® Desktop Board DG41MJ Product Guide Order Number: E59138-001 Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DG41MJ Product Guide February 2009 If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and the receiver. • Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected. -
Discrete Cosine Transform for 8X8 Blocks with CUDA
Discrete Cosine Transform for 8x8 Blocks with CUDA Anton Obukhov [email protected] Alexander Kharlamov [email protected] October 2008 Document Change History Version Date Responsible Reason for Change 0.8 24.03.2008 Alexander Kharlamov Initial release 0.9 25.03.2008 Anton Obukhov Added algorithm-specific parts, fixed some issues 1.0 17.10.2008 Anton Obukhov Revised document structure October 2008 2 Abstract In this whitepaper the Discrete Cosine Transform (DCT) is discussed. The two-dimensional variation of the transform that operates on 8x8 blocks (DCT8x8) is widely used in image and video coding because it exhibits high signal decorrelation rates and can be easily implemented on the majority of contemporary computing architectures. The key feature of the DCT8x8 is that any pair of 8x8 blocks can be processed independently. This makes possible fully parallel implementation of DCT8x8 by definition. Most of CPU-based implementations of DCT8x8 are firmly adjusted for operating using fixed point arithmetic but still appear to be rather costly as soon as blocks are processed in the sequential order by the single ALU. Performing DCT8x8 computation on GPU using NVIDIA CUDA technology gives significant performance boost even compared to a modern CPU. The proposed approach is accompanied with the sample code “DCT8x8” in the NVIDIA CUDA SDK. October 2008 3 1. Introduction The Discrete Cosine Transform (DCT) is a Fourier-like transform, which was first proposed by Ahmed et al . (1974). While the Fourier Transform represents a signal as the mixture of sines and cosines, the Cosine Transform performs only the cosine-series expansion. -
GMAI: a GPU Memory Allocation Inspection Tool for Understanding and Exploiting the Internals of GPU Resource Allocation in Critical Systems
The final publication is available at ACM via http://dx.doi.org/ 10.1145/3391896 GMAI: A GPU Memory Allocation Inspection Tool for Understanding and Exploiting the Internals of GPU Resource Allocation in Critical Systems ALEJANDRO J. CALDERÓN, Universitat Politècnica de Catalunya & Ikerlan Technology Research Centre LEONIDAS KOSMIDIS, Barcelona Supercomputing Center (BSC) CARLOS F. NICOLÁS, Ikerlan Technology Research Centre FRANCISCO J. CAZORLA, Barcelona Supercomputing Center (BSC) PEIO ONAINDIA, Ikerlan Technology Research Centre Critical real-time systems require strict resource provisioning in terms of memory and timing. The constant need for higher performance in these systems has led industry to recently include GPUs. However, GPU software ecosystems are by their nature closed source, forcing system engineers to consider them as black boxes, complicating resource provisioning. In this work we reverse engineer the internal operations of the GPU system software to increase the understanding of their observed behaviour and how resources are internally managed. We present our methodology which is incorporated in GMAI (GPU Memory Allocation Inspector), a tool which allows system engineers to accurately determine the exact amount of resources required by their critical systems, avoiding underprovisioning. We first apply our methodology on a wide range of GPU hardware from different vendors showing itsgeneralityin obtaining the properties of the GPU memory allocators. Next, we demonstrate the benefits of such knowledge in resource provisioning of two case studies from the automotive domain, where the actual memory consumption is up to 5.6× more than the memory requested by the application. ACM Reference Format: Alejandro J. Calderón, Leonidas Kosmidis, Carlos F. Nicolás, Francisco J. -
GPU4S: Embedded Gpus in Space
© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. “The final publication is available at: DOI: 10.1109/DSD.2019.00064 GPU4S: Embedded GPUs in Space Leonidas Kosmidis∗,Jer´ omeˆ Lachaizey, Jaume Abella∗ Olivier Notebaerty, Francisco J. Cazorla∗;z, David Steenarix ∗Barcelona Supercomputing Center (BSC), Spain yAirbus Defence and Space, France zSpanish National Research Council (IIIA-CSIC), Spain xEuropean Space Agency, The Netherlands Abstract—Following the same trend of automotive and avion- in space [1][2]. Those studies concluded that although their ics, the space domain is witnessing an increase in the on-board energy efficiency is high, their power consumption is an order computing performance demands. This raise in performance of magnitude higher than the limited power budget of a space needs comes from both control and payload parts of the space- craft and calls for advanced electronics able to provide high system, which is limited to a couple of Watts. computational power under the constraints of the harsh space Interestingly, GPUs entered in the embedded domain to environment. On the non-technical side, for strategic reasons it is satisfy the increasing demand for multimedia-based hand- mandatory to get European independence on the used computing held and consumer devices such as smartphones, in-vehicle technology. In this project, which is still in its early phases, we entertainment systems, televisions, set-top boxes etc. -
Intel® Desktop Board DG965RY Product Guide
Intel® Desktop Board DG965RY Product Guide Order Number: D46818-003 Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DG965RY Product Guide June 2006 -002 Second release of the Intel® Desktop Board DG965RY Product Guide September 2006 -003 Added operating system support December 2006 If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. -
RISC-V Software Ecosystem
RISC-V Software Ecosystem Palmer Dabbelt [email protected] UC Berkeley February 8, 2015 Software on RISC-V So it turns out there is a lot of software... 2 Software on RISC-V sys-libs/zlib-1.2.8-r1 media-libs/libjpeg-turbo-1.3.1-r1 virtual/shadow-0 virtual/libintl-0-r1 sys-apps/coreutils-8.23 sys-apps/less-471 sys-libs/ncurses-5.9-r3 sys-libs/readline-6.3 p8-r2 app-admin/eselect-python-20140125 sys-apps/gentoo-functions-0.8 sys-libs/glibc-2.20-r1 sys-apps/grep-2.21-r1 dev-libs/gmp-6.0.0a sys-apps/util-linux-2.25.2-r2 virtual/service-manager-0 sys-libs/db-6.0.30-r1 sys-apps/sed-4.2.2 virtual/editor-0 virtual/libiconv-0-r1 sys-apps/file-5.22 sys-devel/gcc-4.9.2-r1 app-arch/bzip2-1.0.6-r7 dev-libs/mpfr-3.1.2 p10 x11-libs/libX11-1.6.2 sys-apps/busybox-1.23.0-r1 sys-process/psmisc-22.21-r2 virtual/pager-0 sys-devel/gcc-config-1.8 net-misc/netifrc-0.3.1 x11-libs/libXext-1.3.3 sys-libs/timezone-data-2014j dev-libs/popt-1.16-r2 x11-libs/libXfixes-5.0.1 app-misc/editor-wrapper-4 sys-devel/binutils-config-4-r1 x11-libs/libXt-1.1.4 net-firewall/iptables-1.4.21-r1 virtual/libffi-3.0.13-r1 x11-libs/fltk-1.3.3-r2 sys-libs/e2fsprogs-libs-1.42.12 sys-libs/cracklib-2.9.2 x11-libs/libXi-1.7.4 dev-libs/libpipeline-1.4.0 sys-apps/kmod-19 x11-libs/libXtst-1.2.2 sys-libs/gdbm-1.11 sys-devel/make-4.1-r1 net-misc/tigervnc-1.3.1-r2 app-portage/portage-utils-0.53 sys-process/procps-3.3.10-r1 dev-lang/perl-5.20.1-r4 sys-apps/sandbox-2.6-r1 sys-apps/iproute2-3.18.0 app-admin/perl-cleaner-2.19 app-misc/pax-utils-0.9.2 virtual/dev-manager-0 perl-core/Data-Dumper-2.154.0 -
Thermal Covert Channels Leveraging Package-On-Package DRAM
Thermal Covert Channels Leveraging Package-On-Package DRAM Shuai Chen∗, Wenjie Xiongy, Yehan Xu∗, Bing Li∗ and Jakub Szefery ∗Southeast University, Nanjing, China fchenshuai ic,220174472, bernie [email protected] yYale University, New Haven, CT, USA fwenjie.xiong, [email protected] Abstract—Package-on-Package (PoP) is an intergraded circuit observation of execution time [2], [3], or on observation packaging technique where multiple separate packages are of physical emanation, such as heat [4] or electromagnetic mounted vertically one on top of the other, allowing for more (EM) field [5], for example. This work focuses on thermal compact system design and reduction in the distance between channels, and shows how the heat, or temperature, can modules. However, this can introduce security vulnerabilities. be measured without special measurement equipment or In particular, this work shows that due to the close physical physical access in commodity SoC devices. Especially, this proximity of a System-on-a-Chip (SoC) package and a PoP work focuses on an SoC DRAM Package-on-Package (PoP) DRAM that is on top of it, a thermal covert channel exists configuration [6] where two chips (SoC and DRAM) are between the SoC and the PoP DRAM. The thermal covert stacked on top of each other. The heat transfers between the channel can allow multiple cores in the SoC to communicate two can be observed by measuring decay rate of DRAM by modulating the temperature of the PoP DRAM. Especially, cells, which is the basis for this work. it is possible for one core in the SoC to generate heat patterns, Previously, heat-based or thermal covert channels have which encode data that is to be transmitted, and another been demonstrated in data centers [7], or in multicore core to observe the transmitted pattern by measuring the processors [8], but these require dedicated thermal sensors decay rate of DRAM cells. -
Intel® Desktop Board DG41TX Product Guide
Intel® Desktop Board DG41TX Product Guide Order Number: E88309-001 Revision History Revision Revision History Date ® -001 First release of the Intel Desktop Board DG41TX Product Guide February 2010 Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel Desktop Board DG41TX may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from Intel Corporation by going to the World Wide Web site at: http://intel.com/ or by calling 1-800-548-4725. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. * Other names and brands may be claimed as the property of others.