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Design and Architectures for Signal and Image Processing EURASIP Journal on Embedded Systems Design and Architectures for Signal and Image Processing Guest Editors: Markus Rupp, Dragomir Milojevic, and Guy Gogniat Design and Architectures for Signal and Image Processing EURASIP Journal on Embedded Systems Design and Architectures for Signal and Image Processing Guest Editors: Markus Rupp, Dragomir Milojevic, and Guy Gogniat Copyright © 2008 Hindawi Publishing Corporation. All rights reserved. This is a special issue published in volume 2008 of “EURASIP Journal on Embedded Systems.” All articles are open access articles distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Editor-in-Chief Zoran Salcic, University of Auckland, New Zealand Associate Editors Sandro Bartolini, Italy Thomas Kaiser, Germany S. Ramesh, India Neil Bergmann, Australia Bart Kienhuis, The Netherlands Partha S. Roop, New Zealand Shuvra Bhattacharyya, USA Chong-Min Kyung, Korea Markus Rupp, Austria Ed Brinksma, The Netherlands Miriam Leeser, USA Asim Smailagic, USA Paul Caspi, France John McAllister, UK Leonel Sousa, Portugal Liang-Gee Chen, Taiwan Koji Nakano, Japan Jarmo Henrik Takala, Finland Dietmar Dietrich, Austria Antonio Nunez, Spain Jean-Pierre Talpin, France Stephen A. Edwards, USA Sri Parameswaran, Australia Jurgen¨ Teich, Germany Alain Girault, France Zebo Peng, Sweden Dongsheng Wang, China Rajesh K. Gupta, USA Marco Platzner, Germany Susumu Horiguchi, Japan Marc Pouzet, France Contents Design and Architectures for Signal and Image Processing, Markus Rupp, Dragomir Milojevic, and Guy Gogniat Volume 2008, Article ID 275975, 3 pages Flexible Hardware-Based Stereo Matching, Kristian Ambrosch, Wilfried Kubinger, Martin Humenberger, and Andreas Steininger Volume 2008, Article ID 386059, 12 pages High Speed 3D Tomography on CPU, GPU, and FPGA, Nicolas GAC, Stephane´ Mancini, Michel Desvignes, and Dominique Houzet Volume 2008, Article ID 930250, 12 pages An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing, Dominique Ginhac, Jer´ omeˆ Dubois, Michel Paindavoine, and Barthel´ emy´ Heyrman Volume 2008, Article ID 961315, 13 pages Design of a Real-Time Face Detection Parallel Architecture Using High-Level Synthesis, Nicolas Farrugia, Franck Mamalet, Sebastien´ Roux, Fan Yang, and Michel Paindavoine Volume 2008, Article ID 938256, 9 pages Smart Camera Based on Embedded HW/SW Coprocessor, Romuald Mosqueron, Julien Dubois, Marco Mattavelli, and David Mauvilet Volume 2008, Article ID 597872, 13 pages An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications, Philippe Manet, Daniel Maufroid, Leonardo Tosi, Gregory Gailliard, Olivier Mulertt, Marco Di Ciano, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba, Pol Cuvelier, Bertrand Rousseau, and Paul Gelineau Volume 2008, Article ID 367860, 11 pages Using High-Level RTOS Models for HW/SW Embedded Architecture Exploration: Case Study on Mobile Robotic Vision,Franc¸ois Verdier, Benoˆıt Miramond, Mickael¨ Maillard, Emmanuel Huck, and Thomas Lefebvre Volume 2008, Article ID 349465, 17 pages A Platform for the Development and the Validation of HW IP Components Starting from Reference Software Specifications, Christophe Lucarz, Marco Mattavelli, and Julien Dubois Volume 2008, Article ID 685139, 16 pages A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis, Rasmus Abildgren, Jean-Philippe Diguet, Pierre Bomel, Guy Gogniat, Peter Koch, and Yannick Le Moullec Volume 2008, Article ID 280347, 12 pages Multiple Word-Length High-Level Synthesis, Philippe Coussy, Ghizlane Lhairech-Lebreton, and Dominique Heller Volume 2008, Article ID 916867, 11 pages Accuracy Constraint Determination in Fixed-Point System Design,D.Menard,R.Serizel,R.Rocher, and O. Sentieys Volume 2008, Article ID 242584, 12 pages Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2008, Article ID 275975, 3 pages doi:10.1155/2008/275975 Editorial Design and Architectures for Signal and Image Processing Markus Rupp (EURASIP Member),1 Dragomir Milojevic,2 and Guy Gogniat3 1 Institute of Communications and Radio-Frequency Engineering (INTHFT), Technical University of Vienna, 1040 Vienna, Austria 2 BEAMS, Universit´e Libre de Bruxelles, CP165/56, 1050 Bruxelles, Belgium 3 Lab-STICC Laboratory, University of South Brittany, CNRS, UMR 3192, 56321 Lorient, France Correspondence should be addressed to Markus Rupp, [email protected] Received 30 December 2008; Accepted 31 December 2008 Copyright © 2008 Markus Rupp et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. The development of complex applications involving signal, many applications to enable parallel interconnections and image, and control processing is classically divided into three communication throughputs. Adaptive and reconfigurable consecutive steps: a theoretical study of the algorithms, a architectures represent a new computation paradigm whose study of the target architecture, and finally an implementa- trend is clearly increasing. tion. This forms a driving force for the future evolution of Today, such sequential design flow is reaching its limits embedded system design methodologies. for the following reasons. This special issue of the EURASIP Journal of Embed- ded Systems is intended to present innovative methods, (i) The complexity of today’s systems designed with tools, design methodologies, and frameworks for algorithm- the emerging submicron technologies for integrated architecture-matching approach in the design flow including circuit manufacturing. system level design and hardware/software codesign, real- (ii) The intense pressure on the design cycle time in time operating system, system modelling and rapid pro- order to reach shorter time-to-market, and to reduce totyping, system synthesis, design verification, as well as development and production costs. performance analysis and estimation. (iii) The strict performance constraints that have to be We received 24 submissions for this special issue of which reached in the end, typically low and/or guaranteed we finally selected 11 for publication. application execution time, integrated circuit area, In the paper entitled “Flexible Hardware-Based Stereo overall system power dissipation. Matching” Kristian Ambrosch et al. propose a novel tech- nique for implementing a flexible block size, disparity range, An alternative approach to a traditional design flow, and frame rate for hardware-based embedded adaptive called algorithm-architecture matching, aims to leverage the stereo-vision systems. By reusing existing resources of a design flow by a simultaneous study of both algorithmic and static architecture, rather than dynamic reconfiguration, the architectural issues, taking into account multiple design con- proposed technique allows both ASIC and FPGA implemen- straints, as well as algorithm and architecture optimizations, tations. Using the proposed architecture, the authors show not only in the beginning but all the way throughout the the impact of the flexible stereo matching on the generated design process. disparity maps for the sum of absolute differences (SADs), Introducing such design methodology is also necessary rank, and census transform algorithms. Finally, the authors when facing the new emerging applications such as high- quantify the resource usage and achievable performance performance, low-power, low-cost mobile communication when synthesized for an Altera Stratix II FPGA. systems and/or smart sensors-based systems. Back-projection (BP) is a costly computational step in This design methodology will have to face also future tomography image reconstruction such as positron emission architectures based on multiple processor cores and dedi- tomography (PET). To reduce the computation time, the cated coprocessors to achieve the required efficiency. NoC- paper entitled “High Speed 3D Tomography on CPU, based communications will become also mandatory for GPU and FPGA” by Nicolas Gac et al. proposes pipelined, 2 EURASIP Journal on Embedded Systems prefetch, and parallelized architecture for PET BP (3PA- DPR in real professional electronics applications, and to PET). The key feature of the proposed architecture is in the provide guidelines to improve its applicability. It makes an original memory access strategy, masking the high latency evaluation of DPR based on experiments made on a set of of the external memory by an efficient use of the intrinsic seven signal and image processing applications carried out temporal and spatial locality of the BP algorithm. Proposed in real conditions. It also identifies the missing elements architecture is prototyped on a System on Programmable and set of advantages for its use in professional electronic Chip (SoPC) to validate the system and to measure its applications. Research directions are also proposed in order performances. Time performances are then compared with to improve its usage. a desktop PC, a workstation, and a graphic processor unit The paper entitled “Using High-Level RTOS Models for (GPU). HW/SW Embedded Architecture Exploration: Case Study on Thepaperentitled“ASIMDProgrammableVision Mobile Robotic Vision” by Franc¸ois Verdier et al. deals with Chip with High
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