A SIMD Microprocessor for Image Processing

Total Page:16

File Type:pdf, Size:1020Kb

A SIMD Microprocessor for Image Processing A SIMD microprocessor for image processing Author: Zhiqiang Qiu Student ID: 20716003 Email: [email protected] Supervisor: Prof. Dr. Thomas Bräunl Computational Intelligence - Information Processing Systems (CIIPS) School of Electrical, Electronic and Computer Engineering The University of Western Australia 1 November 2013 A SIMD microprocessor for image processing Abstract The aim of this project is to design a Single Instruction Multiple Data (SIMD) microprocessor for image processing. Image processing is an important topic in computer science. There are many interesting applications based on image processing, such as stereo matching, 3D object reconstruction and edge detection. The core of image processing is matrix manipulations on the digital image. A digital image captured by a modern digital camera is made up of millions of pixels. The common challenge for most of image processing applications is the amount of data needs to be processed. It will be very slow if each pixel is processed in a sequential order. In addition, general-purpose microprocessors are highly inefficient for image processing due to their complicated internal circuit and large instruction set. One particular solution is to process all pixels simultaneously. A SIMD microprocessor with a simple instruction set can significantly increase the overall processing speed. This project focuses on the development of a SIMD image processor using software simulation. It takes a three step approach. The first step is to improve and further develop our circuit simulation software, Retro. Retro is a powerful circuit design tool with build-in real time graphical simulation. A number of improvements have been made to Retro to fulfil our design requirements. The second step is to design the actual SIMD circuit using Retro software. Tasks include designing the internal circuit of each Process Element (PE), internal circuit of the Sequencer CPU, interconnections between PEs and the instruction set of this SIMD image processor. The final step is to verify the correctness of the design by simulating the SIMD circuit in Retro using a number of image processing applications. This has been a successful project. A number of image processing applications demonstrate the correctness of both Retro software and the SIMD circuit. This project is part of an ongoing project. It lays down a solid foundation and provides a good direction for future tasks. We should expect a simple and highly efficient image microprocessor available for embedded systems in foreseeable future. - ii - A SIMD microprocessor for image processing Acknowledgement I would like to acknowledge and express my deep gratitude to the following persons who made the completion of this project possible: My project supervisor, Prof. Dr. Thomas Braunl, for his guidance, enthusiastic encouragement and valuable support. My project partner, Tim Forrest, for his contribution and valuable support. All teaching staff at UWA, for their assistance in my academic development. The Faculty of Engineering, Computing and Mathematics for providing laboratory facilities. Finally I would like to express my thanks and appreciation to our colleagues and industry persons for giving me such attention and time. - iii - A SIMD microprocessor for image processing Content Abstract ..................................................................................................................................... ii Acknowledgement .................................................................................................................. iii Content ..................................................................................................................................... iv Abbreviations .......................................................................................................................... vi Chapter 1 Introduction ........................................................................................................... 1 1.1 Digital Image ................................................................................................................... 2 1.2 Image processing ............................................................................................................. 4 1.3 Microprocessor ................................................................................................................ 6 Chapter 2 Background ............................................................................................................ 8 2.1 Microarchitecture ............................................................................................................. 9 2.2 Single Instruction Multiple Data (SIMD) ...................................................................... 11 2.3 Instructions Set ............................................................................................................... 12 Chapter 3 Retro ...................................................................................................................... 13 3.1 Overview of Retro .......................................................................................................... 13 3.2 Retro source file ............................................................................................................. 15 3.3 Standard Library ............................................................................................................ 18 3.4 Toy file ........................................................................................................................... 18 3.5 Module ........................................................................................................................... 19 3.5.1 Why do we need modules? ..................................................................................... 19 3.5.2 Solution ................................................................................................................... 19 3.5.3 Design ..................................................................................................................... 20 3.6 3.6 Pin ............................................................................................................................ 21 3.6.1 Design ..................................................................................................................... 22 3.7 Workspace ...................................................................................................................... 22 3.7.1 Why do we need a workspace? ............................................................................... 22 3.7.2 Solution ................................................................................................................... 23 Chapter 4 SIMD Image Microprocessor ............................................................................. 25 4.1 Requirements ................................................................................................................. 25 4.2 Instruction Set ................................................................................................................ 26 4.2.1 PE Instruction Set ................................................................................................... 26 4.2.2 Sequencer CPU Instruction Set ............................................................................... 29 4.3 Processes Element (PE) ................................................................................................. 31 - iv - A SIMD microprocessor for image processing 4.3.1 Arithmetic Logic Unit ............................................................................................. 34 4.3.2 Input / Output (Data Bus & Interconnections) ........................................................ 36 4.3.3 Instruction Bus ........................................................................................................ 37 4.3.4 Internal Memory ..................................................................................................... 37 4.3.5 Status Register ........................................................................................................ 37 4.4 Sequencer CPU .............................................................................................................. 38 4.4.1 Control Unit (CU) ................................................................................................... 41 4.4.2 ALU ........................................................................................................................ 42 4.4.3 Status Register ........................................................................................................ 42 4.4.4 Memory ................................................................................................................... 43 4.4.5 Clock ....................................................................................................................... 44 4.4.6 PE Network ............................................................................................................. 44 4.4.7 Conditional Statements & Loops ............................................................................ 47 Chapter 5 Image Processing ................................................................................................. 51 5.1 Summation ..................................................................................................................... 51 5.2 Thresholding .................................................................................................................
Recommended publications
  • A 2000 Frames / S Programmable Binary Image Processor Chip for Real Time Machine Vision Applications
    A 2000 frames / s programmable binary image processor chip for real time machine vision applications A. Loos, D. Fey Institute of Computer Science, Friedrich-Schiller-University Jena Ernst-Abbe-Platz 2, D-07743 Jena, Germany {loos,fey}@cs.uni-jena.de Abstract the inflexible and fixed instruction set. To meet that we present a so called ASIP (application specific instruction Industrial manufacturing today requires both an efficient set processor) which combines the flexibility of a GPP production process and an appropriate quality standard of (General Purpose Processor) with the speed of an ASIC. each produced unit. The number of industrial vision appli- cations, where real time vision systems are utilized, is con- tinuously rising due to the increasing automation. Assem- Embedded Vision System bly lines, where component parts are manipulated by robot 1. real scene image sensing, AD- CMOS-Imager grippers, require a fast and fault tolerant visual detection conversion and read out of objects. Standard computation hardware like PC-based 2. grey scale image image segmentation platforms with frame grabber boards are often not appro- representation priate for such hard real time vision tasks in embedded sys- 3. raw binary image image enhancement, tems. This is because they meet their limits at frame rates of representation removal of disturbance a few hundreds images per second and show comparatively ASIP FPGA long latency times of a few milliseconds. This is the result 4. improved binary image calculation of of the largely serial working and time consuming process- projections ing chain of these systems. In contrast to that we designed 5.
    [Show full text]
  • United Health Group Capacity Analysis
    Advanced Technical Skills (ATS) North America zPCR Capacity Sizing Lab SHARE Sessions 7774 and 7785 August 4, 2010 John Burg Brad Snyder Materials created by John Fitch and Jim Shaw IBM 1 © 2010 IBM Corporation Advanced Technical Skills Trademarks The following are trademarks of the International Business Machines Corporation in the United States and/or other countries. AlphaBlox* GDPS* RACF* Tivoli* APPN* HiperSockets Redbooks* Tivoli Storage Manager CICS* HyperSwap Resource Link TotalStorage* CICS/VSE* IBM* RETAIN* VSE/ESA Cool Blue IBM eServer REXX VTAM* DB2* IBM logo* RMF WebSphere* DFSMS IMS S/390* xSeries* DFSMShsm Language Environment* Scalable Architecture for Financial Reporting z9* DFSMSrmm Lotus* Sysplex Timer* z10 DirMaint Large System Performance Reference™ (LSPR™) Systems Director Active Energy Manager z10 BC DRDA* Multiprise* System/370 z10 EC DS6000 MVS System p* z/Architecture* DS8000 OMEGAMON* System Storage zEnterprise ECKD Parallel Sysplex* System x* z/OS* ESCON* Performance Toolkit for VM System z z/VM* FICON* PowerPC* System z9* z/VSE FlashCopy* PR/SM System z10 zSeries* * Registered trademarks of IBM Corporation Processor Resource/Systems Manager The following are trademarks or registered trademarks of other companies. Adobe, the Adobe logo, PostScript, and the PostScript logo are either registered trademarks or trademarks of Adobe Systems Incorporated in the United States, and/or other countries. Cell Broadband Engine is a trademark of Sony Computer Entertainment, Inc. in the United States, other countries, or both and is used under license therefrom. Java and all Java-based trademarks are trademarks of Sun Microsystems, Inc. in the United States, other countries, or both. Microsoft, Windows, Windows NT, and the Windows logo are trademarks of Microsoft Corporation in the United States, other countries, or both.
    [Show full text]
  • Design and Architectures for Signal and Image Processing
    EURASIP Journal on Embedded Systems Design and Architectures for Signal and Image Processing Guest Editors: Markus Rupp, Dragomir Milojevic, and Guy Gogniat Design and Architectures for Signal and Image Processing EURASIP Journal on Embedded Systems Design and Architectures for Signal and Image Processing Guest Editors: Markus Rupp, Dragomir Milojevic, and Guy Gogniat Copyright © 2008 Hindawi Publishing Corporation. All rights reserved. This is a special issue published in volume 2008 of “EURASIP Journal on Embedded Systems.” All articles are open access articles distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Editor-in-Chief Zoran Salcic, University of Auckland, New Zealand Associate Editors Sandro Bartolini, Italy Thomas Kaiser, Germany S. Ramesh, India Neil Bergmann, Australia Bart Kienhuis, The Netherlands Partha S. Roop, New Zealand Shuvra Bhattacharyya, USA Chong-Min Kyung, Korea Markus Rupp, Austria Ed Brinksma, The Netherlands Miriam Leeser, USA Asim Smailagic, USA Paul Caspi, France John McAllister, UK Leonel Sousa, Portugal Liang-Gee Chen, Taiwan Koji Nakano, Japan Jarmo Henrik Takala, Finland Dietmar Dietrich, Austria Antonio Nunez, Spain Jean-Pierre Talpin, France Stephen A. Edwards, USA Sri Parameswaran, Australia Jurgen¨ Teich, Germany Alain Girault, France Zebo Peng, Sweden Dongsheng Wang, China Rajesh K. Gupta, USA Marco Platzner, Germany Susumu Horiguchi, Japan Marc Pouzet, France Contents
    [Show full text]
  • Traffic Management Using Image Processing and Arm Processor
    International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 05 | May 2020 www.irjet.net p-ISSN: 2395-0072 TRAFFIC MANAGEMENT USING IMAGE PROCESSING AND ARM PROCESSOR Bhaskar MS1, Nandana CH1, Navya S1, Pooja P1 1Department of ECE, Sai Vidya Institute of Technology, India-560064. ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - In this paper, we aim to establish a smart and 2. With the advancement in computer technology, this system efficient traffic surveillance system which monitors the has an advantage of instantaneity, reliability and security. enormous movement of vehicles that cause traffic congestion. 3. It has easy maintenance. Here, we hope to develop a vision-based vehicle detection module that identifies the presence of vehicles and counts The rest of the paper is organized as follows: them. We achieve it with the help of Mali-C52, which is an ARM Section II: System overview based video processor which captures the real time video of Section III: System design and prototype the area of interest (AOI). This video is processed in various stages and is later interfaced with an ARM microcontroller Section IV: Conclusion which controls the traffic. II: SYSTEM OVERVIEW Key Words: Traffic congestion, Vehicle detection, MALI C52, Area of Interest (AOI) In the very first step, we obtain the real time video which is read and converted into images and then frames. This frame I: INTRODUCTION can be processed in a series of steps which are listed below: The rapid growth in the number of vehicles is a key feature of A. VEHICLE DETECTION BY BACKGROUND good economic development.
    [Show full text]
  • Suchitra Sathyanarayana +1-858-717-2399 [email protected]
    Suchitra Sathyanarayana +1-858-717-2399 [email protected] EDUCATION Doctor of Philosophy Nanyang Technological University, Singapore (Thesis submitted) M.Eng. (by research) Computer Eng., Nanyang Technological University, Singapore [2004-2006] B.Eng. (with Honors) Computer Eng., Nanyang Technological University, Singapore [1999-2003] RESEARCH EXPERIENCE Image Processing Architectures: Responsible for innovating high speed image processing cores by exploiting underlying parallelisms and image symmetries - (i) line feature extractor based on Hough Transform, which gives 1000x speedup; (ii) a novel parallel image rotation engine that achieves order of magnitude speedups especially for high-resolution images; (iii) low-cost pattern recognition system that achieves on-the-fly image rotation using line buffers and recognition using a simplified MLP neural network; (iv) a parallel EZW Wavelet encoding architecture that can be deployed for Haar based image compression systems. Hardware efficient techniques for Vision based Advanced Driver Assistance: As part of my PhD thesis, I developed computationally efficient techniques that detects and classifies various kinds of road markings, including lane markings, arrow markings of different types, zigzag markings, pedestrian markings etc. The proposed techniques are scale-invariant, hardware efficient and robust to complexities in road scenes such as shadows, lighting and weather changes. Vision-based Medical Applications: As part of my M.Eng (by research) thesis, I developed real-time techniques to assess the movements of camera during medical endoscopy. This included methods to infer camera rotations and longitudinal movements using image unrolling and corresponding matching of features. I am also currently involved with another PhD project on vision-based patient monitoring system, using multiple cues such as breathing and movements to infer abnormal patient behavior.
    [Show full text]
  • Image Processor May Be Copied by Individuals and Not - for - Profit
    DISTRIBUTION RELIGION THE IMAGE PROCESSOR MAY BE COPIED BY INDIVIDUALS AND NOT - FOR - PROFIT INSTITUTIONS WITHOUT CHARGE FOR - PROFIT INSTITUTIONS WILL HAVE TO NEGOTIATE FOR PERMISSION TO COPY I VIEW MY RESPONSIBILITY TO THE EVOLUTION OF NEW CONSCIOUSNESS HIGHER THAN MY RESPONSIBILITY TO MAKE PROFIT ; I THINK CULTURE HAS TO LEARN TO USE HIGH-TEK MACHINES FOR PERSONAL AESTHETIC, .RELIGIOUS, INTUITIVE, COMPREHENSIVE, EXPLORATORY GROWTH THE DEVELOPMENT OF MACHINES LIKE THE IMAGE PROCESSOR IS PART OF THIS EVOLUTION I AM PAID BY THE STATE, AT LEAST IN PART, TO DO AND DISEMINATE THIS INFORMATION ; SO I DOI As I am sure you (who are you) understand a work like developing and expanding the Image Processor requires much money and time . The 'U' does not have much money for evolutionary work and getting of grants are almost as much work as holding down a job . Therefore, I have the feeling that if considerable monies were to be made with a copy of the Image Processor, I would like some of it . So, I am asking (not telling) that if considerable money were made, by an individual with a copy of. the Image Processor, or if a copy of the Image Processor were sold (to an individual or not-for-profit institution), I would like 20% gross profit . I Things like $100 .00 honorariums should be ignored . Of course enforcing such a request is too difficult to be bothered with . But let it be known that I consider it to be morally binding Much Love . Daniel J . Sandin Department of Art University of Illinois at Chicago Circle Box 4348 Chicago, Illinois 60680 Office phone : 312-996-8689 Lab phone: 312-996-2312 Messages : 312-996-3337 (Department of Art) NOTES ON THE AESTHETICS OF 'copying-an-Ima ge Processor' : Being a 'copier' of many things, in this case the first copier of an Image Processor, .1 trust the following notes to find meaning to .
    [Show full text]
  • A SIMD Programmable Vision Chip with High Speed Focal Plane Image Processing Dominique Ginhac, Jérôme Dubois, Michel Paindavoine, Barthélémy Heyrman
    A SIMD Programmable Vision Chip with High Speed Focal Plane Image Processing Dominique Ginhac, Jérôme Dubois, Michel Paindavoine, Barthélémy Heyrman To cite this version: Dominique Ginhac, Jérôme Dubois, Michel Paindavoine, Barthélémy Heyrman. A SIMD Pro- grammable Vision Chip with High Speed Focal Plane Image Processing. EURASIP Journal on Em- bedded Systems, SpringerOpen, 2009, pp.13. 10.1155/2008/961315. hal-00517911 HAL Id: hal-00517911 https://hal.archives-ouvertes.fr/hal-00517911 Submitted on 15 Sep 2010 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. ACCEPTED TO EURASIP - JOURNAL OF EMBEDDED SYSTEMS 1 A SIMD Programmable Vision Chip with High Speed Focal Plane Image Processing Dominique Ginhac, Jer´ omeˆ Dubois, Michel Paindavoine, and Barthel´ emy´ Heyrman Abstract— A high speed analog VLSI image acquisition and and column-level [9]–[12]. Indeed, pixel-level processing is low-level image processing system is presented. The architecture generally dismissed because pixel sizes are often too large of the chip is based on a dynamically reconfigurable SIMD to be of practical use. However, as CMOS scales, integrating processor array. The chip features a massively parallel archi- tecture enabling the computation of programmable mask-based a processing element at each pixel or group of neighboring image processing in each pixel.
    [Show full text]
  • Sony's Emotionally Charged Chip
    VOLUME 13, NUMBER 5 APRIL 19, 1999 MICROPROCESSOR REPORT THE INSIDERS’ GUIDE TO MICROPROCESSOR HARDWARE Sony’s Emotionally Charged Chip Killer Floating-Point “Emotion Engine” To Power PlayStation 2000 by Keith Diefendorff rate of two million units per month, making it the most suc- cessful single product (in units) Sony has ever built. While Intel and the PC industry stumble around in Although SCE has cornered more than 60% of the search of some need for the processing power they already $6 billion game-console market, it was beginning to feel the have, Sony has been busy trying to figure out how to get more heat from Sega’s Dreamcast (see MPR 6/1/98, p. 8), which has of it—lots more. The company has apparently succeeded: at sold over a million units since its debut last November. With the recent International Solid-State Circuits Conference (see a 200-MHz Hitachi SH-4 and NEC’s PowerVR graphics chip, MPR 4/19/99, p. 20), Sony Computer Entertainment (SCE) Dreamcast delivers 3 to 10 times as many 3D polygons as and Toshiba described a multimedia processor that will be the PlayStation’s 34-MHz MIPS processor (see MPR 7/11/94, heart of the next-generation PlayStation, which—lacking an p. 9). To maintain king-of-the-mountain status, SCE had to official name—we refer to as PlayStation 2000, or PSX2. do something spectacular. And it has: the PSX2 will deliver Called the Emotion Engine (EE), the new chip upsets more than 10 times the polygon throughput of Dreamcast, the traditional notion of a game processor.
    [Show full text]
  • A 4K@15,000 Lps High-Accuracy CMOS Linear Sensor Chip With
    A 4k@15,000 LPs High-Accuracy CMOS Linear Sensor Chip with Programmable Gain and Offset and Embedded Digital Correction Francisco Jiménez-Garrido 1, Rafael Domínguez-Castro 1,2, Fernando Medeiro 1,2, Alberto García, Cayetana Utrera, Rafael Romay and Angel Rodríguez-Vázquez 1 AnaFocus (Innovaciones Microelectrónicas S.L.) 2 IMSE-CNM/CSIC and Universidad de Sevilla Avda Isaac Newton, Pabellón de Italia, Ático Parque Tecnológico Isla de la Cartuja, 41092-Sevilla (SPAIN) [email protected] Introduction Machine Vision (MV) applications require high quality images and hence dedicated CMOS technologies (CIS) and optimized pixels such as for instance those based on pin photodiodes. High-performance CMOS MV sensors with image moving capture, exposure control, anti- blooming, high-speed readout, etc have been devised elsewhere using these CIS technologies [1]. However, most of them require off-chip digital processors for correction of the raw sensor data, which has an impact on power, reliability and compactness. This paper reports a CMOS tri-linear image sensor with and on-chip embedded digital processor for MV. This single chip smart sensor is conceived to reach performance levels similar to those of multi-chip CCD digital camera systems [2]. Table 1 summarizes data of available linear sensors, including a CCD one to the purpose of performance comparison. The last column corresponds to the device reported in this paper, called AFLS4k. The AFLS4k performs similar to the CCD one and has better accuracy specs than its CMOS counterparts.
    [Show full text]
  • Transchip TC5747 Preliminary Product Brief
    TC5747 CMOS Imager Product Brief CoderCam™ TC5747 VGA CMOS camera module with on-chip image processor, motion JPEG and display graphics Description Features TC5747 is a high performance, low power • VGA format sensor with 1/4.5” optics miniature camera module that incorporates • Embedded micro-controller a VGA CMOS sensor, image processing, a • Supports wide dynamic range and a motion JPEG codec, and display graphics variety of illumination conditions on a single chip. • Motion JPEG codec TC5747 imager is specifically designed to • 64 KB memory for JPEG frames meet the requirements of small mobile devices, in terms of automatic adjustments, • Standard host interface of 8/16 bits low power and small size. Its direct • Direct interface of 8/9/16/18 bits to LCD interface to the LCD as well as the host • Low power design, sleep modes data bus enables easy and fast integration • On chip PLL supports wide clock range into mobile devices. Bypass mode of the camera operation provides direct streaming • 2x and 4x electronic zoom from the host processor to the LCD. • Downsize to fit target display size Parallel host interface enables real motion • Vertical and horizontal inversion JPEG operation. • Auto flicker detection and correction TC5747 performs the graphic functions • Anti shading correction required for the display, lightening the load • on the baseband and reducing the solution On screen display cost and size. • Digital effects and fun frame overlay • TC5747 implements sophisticated digital Thumbnails and portrait images image processing algorithms using • Vertical and horizontal inversion dedicated hardware and a programmable • Supports up to two displays microcontroller.
    [Show full text]
  • RIP Architecture L Technical Information
    L Technical Information RIP Architecture A raster image processor (RIP) is a computer with a very specific task to perform. It translates a series of computer commands into something that an output device can print. For an imagesetter, this means the instructions that instruct the laser to expose certain areas on the film. Acronyms ASIC Application Specific Integrated Circuit RIP architecture refers to the CISC Complex Instruction Set Computer 1An excellent source of design of the RIP, particularly CPU Central Processing Unit information on computer EPROM Erasable Programmable Read-Only technology is The Computer the hardware and software Memory Glossary by Alan Freedman. that make the RIP work. It is I/O Input/Output It is available from The impossible to discuss RIP MHz Megahertz Computer Language architecture without MIPS Million Instructions Per Second Company, (215) 297-5999. mentioning a number of 1 (also the name of a company that computer buzz words , many manufactures CPUs) of which are acronyms (see PROM Programmable Read-Only Memory list to right). And so to begin, RIP Raster Image Processor we’ll start with a review of RISC Reduced Instruction Set Computer computer basics, and see how SPARC Scalable Performance ARChitecture those principles apply to RIPs. TAXI Transparent Asynchronous Xmitter receiver Interface XMO eXtended Memory Option Computer basics The CPU of a computer is where the bulk of the computing gets done. Microprocessor designations The CPU may also be called the Intel Corporation microprocessor if the CPU is built on a • 8080, 8088 single miniaturized electronic circuit (i.e. • 8086, 80286, 80386, 80486 chip).
    [Show full text]
  • A Programmable Image Processor for Real-Time Image Processing Applications
    Microprocessors and Microsystems 23 (1999) 35–41 A programmable image processor for real-time image processing applications M.Y. Siyala,1,*, M. Fathyb,2 aSchool of EEE, Nanyang Technological University, Nanyang Avenue, Singapore, Singapore 639798 bDepartment of Computer Engineering, Iran University of Science and Technology, Narmark, Tehran, Iran Received 22 September 1998; received in revised form 25 October 1998; accepted 12 November 1998 Abstract In this article we present an architectural design and analysis of a programmable image processor, named Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures. q 1999 Elsevier Science B.V. All rights reserved. Keywords: SIMD; RISC; CISC; Array processor; Parallel processing; Image processing Real-time 1. Introduction area operations with 3 × 3 mask. This is because area processing with 3 × 3 mask is commonly used in many Low-level image processing operations usually involve image processing applications [5,9]. This is particularly simple and repetitive operations over the entire input images true for the image processing algorithms developed for [1–5]. In real time applications, these input images are road traffic analysis [8,9]. However, other area processing required to be processed at a rate of 25 frames per second with larger masks can be easily realised through several 3 × (in most countries).
    [Show full text]