DOCSLIB.ORG

Curtiss-Wright / Systran SL100 Datasheet (Pdf)

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Curtiss-Wright / Systran SL100 Datasheet (Pdf) Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Curtiss-Wright / Systran SL240 at our website: Click HERE SL100 Series Short Form Catalog PRELIMINARY PRODUCT DATA è è è è è è è è è è è è è è è è è è è è è è è è è è è è è è è è Second-Generation SL100 SERIES Now Available! • 105 MB/second Sustained Data Rate – The Fastest, Most Efficient Way to Transfer Anything! • Dedicated Point-to-Point, Broadcast Chaining, or Single and Multiple Master Ring Topologies • Extends Front Panel Data Port (FPDP) Connections Up To 10 Km • Supports Shortwave and Longwave Fiber Optic Connections • Compatible with Mercury RACEway and Sky Computers’ SKYchannelTM architectures Introduction Systran Corporation introduces the next wave in high- munication in today’s advanced DSP systems. It is fully bandwidth, low-latency data communication — it’s the compatible with both Mercury’s RACEway Interlink Stan- FibreXtreme SL100 Series! Based on the technology pio- dard and Sky Computers’ SKYchannel, two of the leading neered in our original Simplex Link series, FibreXtreme DSP communications architectures. It’s field-tested tech- SL100 blasts data at a sustained 105 MB per second with nology that produces real-world results. microsecond data latency – up to 25% faster than other technologies. You won’t find a faster, more efficient, eas- Powerful and Flexible ier-to use data link for your data-intensive application: Each SL100 board features programmable bi-directional • Digital Signal Processing communication capability. There’s no need for specialized • source and destination cards – you have more communica- High-speed data acquisition tion flexibility with FibreXtreme SL100. For even more • Medical imaging flexibility in system design, SL100 cards support a variety • Range and telemetry systems of system topologies. Choose from point-to-point, broad- • Simulation systems cast chaining, or single and multiple master ring topologies • Video production that enable a single SL100 card to simultaneously send data to multiple destinations. FibreXtreme SL100 is a 1.062 GHz serial data link which FibreXtreme offers flexibility in software support with driv- utilizes a highly specialized communications protocol opti- ers for today’s popular operating systems. With support for mized for maximum data throughput. Data transfers occur Windows NT, SGI IRIX, VxWorks, Sun Solaris, Red Hat without the CPU overhead and non-deterministic latencies Linux, and Lynx OS, you can choose the best OS solution associated with many layers of complex communication for your application. protocols. The FibreXtreme on-board DMA engine handles single transactions up to 64 MB for maximum data through- The flexibility offered by FibreXtreme doesn’t stop there. put without processor intervention. DMA and register byte/ With media options for both short-wave and long-wave fi- word swapping provide additional system flexibility. ber, FibreXtreme links can extend Front Panel Data Port (FPDP) connections up to 10 Km with no significant impact Industry Standard Architecture on performance. System designers have the flexibility to FibreXtreme Serial FPDP technology (VITA 17.1p) is fast distribute system components across the building, across becoming the industry standard for high-speed serial com- the campus, or even across town! Corporate Headquarters • 4126 Linden Avenue • Dayton, OH 45432-3068 • Phone: 937-252-5601 Sales Phone: 800-252-5601 • Fax: 937-258-2729 • E-mail: [email protected] • http://www.systran. com Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com Unique Design Characteristics With support for 1 Gbit/sec transmission rates between the Analog-to-Digital Converter (ADC) of a Sensor Sub- interconnected subsystems separated by as much as 10 system and the Digital Signal Processors (DSP) of ad- kilometers and low-latency performance to match, vanced DSP based image processing systems. FPDP FibreXtreme data link technology is ideal for many of to- can be either an 80 or 160 MB/sec parallel connection day’s high-throughput Digital Signal Processing (DSP) made via ribbon cable across the VME front panel. The applications like those shown in Figure 1. FPDP provides the simplicity, bandwidth, and reliability necessary to support these types of DSP systems. This Sensors DSP Systems High Performance concept is summarized in Figure 2. (Scan the Image) (Develop the Image) GP Computers (Analyze the Image) However, FPDP has one major limitation, the ADC must 105 MB/s be located within the one meter maximum cable length of FPDP. For many reasons, it is often desirable to lo- 105 MB/s 100 MB/s PMC cate the ADC as close as possible to the sensing unit, Radar 105 MB/s IR PMC which may be located more than one meter from the Sonar Acoustic DSP system(s). FibreXtreme SL100 extends the reach of Photon Fibre Channel Video FPDP up to 10 kilometers while retaining its simplicity, Etc. 100 MB/s 100 MB/s 100 MB/s 100 MB/s bandwidth, and reliability. This concept is illustrated in Figure 3 below. High Speed Storage Fig. 1 - Typical DSP Imaging System FibreXtreme employs hardware-based insertion of data into fixed frames with flow control to keep the data con- nection open and operating at full speed. There’s no need for complex communication protocols that cause data latency and reduce system performance as they FPDP FPDP establish and arbitrate the connection. Extend Front Panel Data Port Connections ADC SL100 SL100 DSP The Front Panel Data Port (FPDP) was specifically in- vented to address the high speed connection between 10 kilometer max Fig. 3 - FibreXtreme Extends FPDP to 10 Km Front Panel Data Port (FPDP) Specification The link is implemented on standard 6U VME cards with ANSI/VITA 17 -1998 a sending card at the sensor and a receiving card at the DSP. PCI and PMC FibreXtreme cards allow data to flow • SIMPLE PARALLEL INTERFACE from FPDP directly into the computer backplane and Front Panel Data Port • DEFACTO STANDARD FPDP also provides high speed computer to computer connec- • HIGH THROUGHPUT (up to 160 MB/s) tions. • LOW OVERHEAD ADC DSP • LOW LATENCY In demanding high-throughput applications, even the • AND smallest delay can mean the difference between suc- 1 meter max cess and failure. FibreXtreme SL100 offers the speed, ALREADY SUPPORTED BY MANY SENSOR & DSP SUPPLIERS ! power, flexibility, and reliability to ensure that your appli- cation succeeds! Fig. 2 - Industry-standard FPDP Connections Features & Specifications • Programmable bi-directional boards for provide more • Proven 8B/10B encoding for data transmission configuration flexibility • Memory: 1 MB receive buffer • Built-in data synchronization with minimal impact on • Electrical Requirements: +5 VDC ±5%, 2 Amps overall data throughput • Operating Environment: • Integrated interrupt controller to report link failure, ° ° transaction completion, or buffer space request Temperature Range: +0 to +50 C Humidity Range: 5% to 95% (noncondensing) • Loop operation with out-of-band arbitration or point- • to-point operation Storage Environment: Temperature Range: -40° to +85°C • Watchdog timer for failover operation Humidity Range: 0% to 95% (noncondensing) Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com SL100 Series Products 6U VME FPDP LX1500 Modular Hub The LinkXchange LX1500 Modular Hub is a 32-port crosspoint matrix Hardware Compatibility: switching device that supports a 6U VME (power only) variety of digital signals at baud Front Panel Data Port Specification, rates up to 1.5 GB/second. It sup- ANSI/VITA 17-1998 ports up to eight “port cards” with up to four I/O ports per card. Different types of port Physical Dimensions: cards provide the specific media connectors, signal con- 6.690” x 10.320” (169.926 mm x 262.128 mm) version, and conditioning required for a specific type of network or digital signal to be switched. VME64 DSP CMC FPDP FibreXtreme SYSTEM P2 I/O RACEway SKYchannel Myrinet P2 CI SENSOR Hardware Compatibility: FibreXtreme FibreXtreme Front Panel Data Port FCAL FX NIC Specification, ANSI/VITA 17-1998 FCDA IEEE Draft Standard for CMC Family, P1386/Draft 2.0 STORAGE SYSTEM Physical Dimensions: RAW DATA 2.913” x 5.866” (74.000 mm x 149.000 mm) STORAGE When the LX1500 is utilized with the FibreXtreme SL100 data link, high-speed digital signals from a single send- ing card can be instantly copied and distributed to multi- ple receiving cards. This provides the capability for si- multaneous parallel processing of identical data PMC streams. Hardware Compatibility: PCI Local Bus SL100 Series Software Specification, Rev. 2.1 The FibreXtreme SL100 Physical Dimensions: Series data link system 2.913” x 5.866” (74.000 mm x 149.000 mm) interfaces with various computing platforms typi- cally utilized in data- intensive high bandwidth applications such as DSP. Specific software PCI packages are covered under our Software Maintenance Service, which offers Hardware Compatibility: free, automatic software and documentation upgrades when new versions are released during the mainte- PCI Local Bus nance term. Specification, Rev. 2.1 Physical Dimensions: Operating System Support Windows NT® VxWorks® LynxOS® 4.725” x 4.200” (120.015 mm x 106.680 mm) Red Hat Linux Sun Solaris™ SGI IRIX® Product Specifications are to change without notice. SCRAMNet and FibreXpress are registered trademarks of Systran Corporation. Systran, the Systran logo, FibreXtreme, LinkXchange, BusXchange, 1553 Solutions, I/O Solutions, SCRAMalyzer and EZ-SCRAMware are trademarks of Systran Corporation.
Load more

Recommended publications
  • Vita Standard Update Spring 2011
    By John Rynearson VITA 51.2 moves into ANSI/VITA balloting VSO ANSI accreditation Accredited as a Standards Development Organization (SDO) in June 1993 by the American National Standards Institute (ANSI), the VITA Standards Organization (VSO) meets every two months to address vital embedded bus and board industry standards Editor’s note: This update is based on the issues. Information on ANSI/VITA standards is available on the January 2011 VSO meeting. Additional VSO meetings are VITA website at www.vita.com. scheduled for March 2011 and May 2011. Be sure to check out our online E-cast archives for the latest video VSO study and working group activities and audio updates on VITA 41 (VXS), 46 (VPX), 48 (VPX-REDI), Standards within the VSO may be initiated by a study group and and 65 (OpenVPX). See www.opensystemsmedia.com/ecast. developed by a working group. A study group requires the spon- sorship of only one VSO member. A working group requires the sponsorship of at least three VITA members. VITA 51.2, Physics of Reliability Failure Objective: Establish uniform practices, take advantage TechChannels of current developments, and clarify reliability prediction expecta- tions using physics of failure methodologies. Status: The working group voted to move VITA 51.2 into ANSI/ VITA ballot. The initial ballot is complete, comments were reviewed, the draft was revised, and a recirculation ballot was started. VITA 61, XMC 2.0 Objective: To specify an alternative connector for use on XMC mezzanine modules. Status: The draft has been completed and after revisions is now Up-to-the minute, in a working group recirculation ballot.
    [Show full text]
  • Review of Diagnostics for Next Generation Linear Accelerators
    Proceedings DIPAC 2001 – ESRF, Grenoble, France REVIEW OF DIAGNOSTICS FOR NEXT GENERATION LINEAR ACCELERATORS M. Ross, Stanford Linear Accelerator Center, Stanford, CA 94309, USA Abstract will review ideas and tests of diagnostics for measuring electron beam position, profile (transverse and New electron linac designs incorporate substantial longitudinal) and loss. advances in critical beam parameters such as beam loading and bunch length and will require new levels of 2 POSITION performance in stability and phase space control. In the coming decade, e- (and e+) linacs will be built for a high 2.1 Purposes power linear collider (TESLA, CLIC, JLC/NLC), for fourth generation X-ray sources (TESLA FEL, LCLS, High peak current linacs require accurate, well Spring 8 FEL) and for basic accelerator research and referenced, beam position monitors (BPM’s) to suppress development (Orion). Each project assumes significant the interaction between the RF structure and the beam. In instrumentation performance advances across a wide addition, equally as important, the small beam must pass front. close to the center of each quadrupole magnet in order to This review will focus on basic diagnostics for beam avoid emittance dilution arising from the dispersion position and phase space monitoring. Research and generated from a small dipole kick. Some LC designs development efforts aimed at high precision multi-bunch include two separate BPM systems in each linac. Typical beam position monitors, transverse and longitudinal requirements are shown in table 2. profile monitors and timing systems will be described. Table 2: NLC Linac quadrupole BPM performance requirements 1 INTRODUCTION Parameter Value Conditions 10 - Next generation linacs have smaller beam sizes, Resolution 300 nm @ 10 e single increased stability and improved acceleration efficiency.
    [Show full text]
  • Conceptual Design Review Vol 2
    GSAOI CONCEPTUAL DESIGN REVIEW DOCUMENTATION VOL. 2 Submitted to the International Gemini Project Office under AURA Contract No. 9414257-GEM00304 Research School of Astronomy and Astrophysics Australian National University Canberra, Australia August 20-21, 2002 AUSTRALIAN NATIONAL UNIVERSITY RESEARCH SCHOOL OF ASTRONOMY AND ASTROPHYSICS This page is left blank intentionally. CONCEPTUAL DESIGN REVIEW VOL. 2 - ii - AUSTRALIAN NATIONAL UNIVERSITY RESEARCH SCHOOL OF ASTRONOMY AND ASTROPHYSICS TECHNICAL REVIEW GSAOI Conceptual Design Review Document Research School of Astronomy and Astrophysics Australian National University Canberra, Australia August 20-21, 2002 CONCEPTUAL DESIGN REVIEW VOL. 2 - 1 - AUSTRALIAN NATIONAL UNIVERSITY RESEARCH SCHOOL OF ASTRONOMY AND ASTROPHYSICS This page is left blank intentionally. CONCEPTUAL DESIGN REVIEW VOL. 2 - 2 - AUSTRALIAN NATIONAL UNIVERSITY RESEARCH SCHOOL OF ASTRONOMY AND ASTROPHYSICS Table of Contents 1 Overview ....................................................................................................................... 11 1.1 Design Priorities......................................................................................................... 11 1.2 Technical Implementation......................................................................................... 11 1.3 Systems Design........................................................................................................... 12 1.4 Optical Design...........................................................................................................
    [Show full text]
  • Download Resume
    4 8 0 R O B I N S O N R D . • B O X B O R O U G H , M A 0 1 7 1 9 P H O N E 9 7 8 - 8 4 4 - 4 1 0 4 • E - M A I L B O B _ B L A U @ A L U M . M I T . E D U R O B E R T B L A U Productive Knowledgeable Innovative CAREER SUMMARY Expert in design, development, and delivery of high performance, cost-effective computation and communication solutions. Experienced in all facets of project development: innovation, technical analysis, planning, design, implementation, delivery, and support. Excellent organizational, budget management, leadership, team building, and project management qualifications. A career spent innovating, championing, and implementing new technologies to improve the capabilities, performance, and differentiation of products. Examples of innovations include: applying converged Ethernet to real-time applications, design and development of the first switched-PCI ASIC, applying switched-PCI to blade servers, and using Reed-Solomon encoding to provide error correction for an entire 16 bit wide DRAM component failure. SKILLS High performance system design Network convergence over 10/40Gb Data Center Ethernet . Ethernet protocols and standards . FCoE and IBoE technologies . Switch and NIC roadmaps Cluster and I/O interfaces . PCIe - Gen 2 and Gen 3 . MPI, RDMA, Open Fabrics, I/OAT Accelerator architectures and limitations . FPGA's and GPGPU’s . OpenCL programming SMP interconnects . QPI and HyperTransport . Multicore programming Intel and AMD Processor roadmaps H/W development System Verilog, VHDL, Modelsim/Questasim Design tools: Xilinx, Altera, ASIC’s, Boards Software development C, Python, C++, Ruby Perl, Javascript, Bash LAMP development Linux, SVN, Bugzilla Algorithm development Matlab Simulink, Sysgen PROFESSIONAL EXPERIENCE Mercury Computer Systems, Inc., 2004-2009 Chelmsford, MA Consulting Engineer Network/Storage/IPC/IO convergence over Layer 2 Ethernet Innovated the use of Data Center Ethernet as a transport layer for reliable, low latency, high bandwidth, inter-processor communication and streaming I/O.
    [Show full text]
  • Real Time Controller As Built Design Document
    KECK NEXT GENERATION WAVEFRONT CONTROLLER Real Time Controller As Built Design Document Document : NGWFC_RTC_ASB_001.doc Issue : 1 Date : September 2nd, 2007 Prepared by : MICROGATE ................................................. R.Biasi ................................................. D.Pescoller ................................................. M.Andrighettoni Checked by : ................................................. Approved by : ................................................. Released by : ................................................. September 2nd , 2007 NGWFC Doc. : NGWFC_RTC_ASB_001.doc REAL TIME CONTROLLER Issue : 1 – September 2nd , 2007 As Built Data Package Page : 2 of 158 CHANGE RECORDS SECTION / QA/ REASON/INITIATION ISSUE DATE Author Approved PARAG. QC AFFECTED DOCUMENTS/REMARKS 1 2007.09.02 Microgate All First Issue NGWFC Doc. : NGWFC_RTC_ASB_001.doc REAL TIME CONTROLLER Issue : 1 – September 2nd , 2007 As Built Data Package Page : 3 of 158 TABLE OF CONTENTS 1 ACRONYMS ............................................................................................................................ 11 2 APPLICABLE DOCUMENTS ............................................................................................... 13 3 REFERENCE DOCUMENTS ................................................................................................ 14 4 INTRODUCTION .................................................................................................................... 15 5 SYSTEM OVERVIEW...........................................................................................................
    [Show full text]
  • Serial Front Panel Data Port (FPDP) Draft Standard VITA 17.1 – 199X
    Serial Front Panel Data Port (FPDP) Draft Standard VITA 17.1 – 199x Draft 0.6 January 30, 2002 This draft standard is being prepared by the VITA Standards Organization (VSO) and is unapproved. Do not specify or claim conformance to this draft standard. VSO is the Public Domain Administrator of this draft standard and guards the contents from change except by sanctioned meetings of the task group under due process. VITA Standards Organization 7825 East Gelding Drive, Suite 104 Scottsdale, AZ 85260 Ph: 602-951-8866 Fx: 602-951-0720 URL: http://www.vita.com Table of Contents Chapter 1- Introduction..........................................................................................................................5 1.1 Standard Terminology.............................................................................................................5 Chapter 2 - Scope and Purpose.............................................................................................................7 2.1 Scope ......................................................................................................................................7 2.2 Purpose ...................................................................................................................................7 2.3 References ..............................................................................................................................7 Chapter 3 ..............................................................................................................................................8
    [Show full text]
  • Serial Port Protocol Analyzer
    Serial Port Protocol Analyzer Adventitious or affronted, Ez never wadings any tromometers! Berberidaceous Juergen outjest gratingly while Merrel always blots his disuses gluttonising roaringly, he instigate so stolidly. Dominical Odie wall no tangent disillusionise stunningly after Duke lallygagging despondingly, quite droughtiest. Thank you all serial port to exchange or drag with performance measurements on our main menu selection that matches your device so on contents to the oscilloscope Free Network Protocol Analyzer Features. TOP 5 Serial Port Monitors software DEV Community. Hardware serial port communication monitor One Transistor. Serial Port Monitors Top 10 apps and their features you need. FREE RS232 Serial Monitor Protocol Analyzer Terminal. Protocol analyzers Test and measurement software. This instrument is also referred to as Protocol within WaveForms Prerequisites A Digilent Test Measurement Device with Digital InputOutput Channels Analog. Unbounded Labs Protocol Analyzer Manual. Until the data quickly see the following screen, which will appear as you. The already feature which meant sometimes called port mirroring or port monitoring selects network traffic for analysis by special network analyzer The network analyzer. Dce as protocol packets are already opened by another protocol is asynchronous sampling fast and protocols into memory resources. To monitor our serial monitor is either true knowledge it intercepts calls between an application and a serial port driver. Also lets you are usually inexpensive thanks for the async signal analysis, with a com interface. In 1995 and replaces the serial parallel mouse and keyboard ports. Simply running the above to save a variety of. Your it will expedite your own this software such as well as shown below to install the older versions are quite a quality while trying for? RS232 Sniffer Serial Protocol Analyzer EZ-Tap Pro.
    [Show full text]
  • 4 Channel 2.5 GSP Optical Sfpdp PMC Virtex-4 with Powerpc Core Description
    id497359 pdfMachine by Broadgun Software - a great PDF writer! - a great PDF creator! - http://www.pdfmachine.com http://www.broadgun.com FM481 4 Channel 2.5 GSP Optical sFPDP PMC Virtex-4 with PowerPC Core Description: The FM481 is a high performance four (4) channel optical 2.5 Gbit/s serial Front Panel Data Port (sFPDP) industry standard PMC board with Pn4 User Definable I/O. The FM481 is designed to be used as an embedded sFPDP board module dedicated to high performance serial communications that require support of the sFPDP protocol. The FM481 provides four (4) each full-duplex 2.5Gbps LC optical transceivers for support of the embedded sFPDP protocol IP core implemented in the on-board Xilinx Virtex-4 “Plug ” high speed serial FPGA. Fast on-board memory resources are available to the FPGA which can be used as a -N-Play communication processor with the optional ability for customer specific signal process and customization. ’s MGTs Up to 2.5Gbps per optical transceiver via the Virtex-4 Up to 230MBytes/s per optical transceiver Unidirectional and bi-directional links Framing supported: Dataflow Control, PIO per specification, Copy Mode, Copy-Loop mode and CRC Fully compliant ANSI/VITA 17.1-2003 SFPDP standard FPGA • XC4VFX20 or XC4VFX60 with embedded PowerPC RISC processor • FPGA configuration on -board storage • Optional Off-the-shelf IP cores • FPGA Firmware Design Services available upon request Memory • 2 x 32M x 16 DDR2 SDRAM • 128Mbit flash device PCI interface • PCI -X 64-bit 133MHz, 3.3V • PCI -X/PCI 64/32-bit 66MHz, 3.3V • P CI 64/32-bit 33MHz, 3.3V • PCI E – xpress - 4 lanes Special Order Measured sustained bandwidth 64-bit 133MHz = 760Mbytes/s 64-bit 66MHz = 450Mbytes/s 32-bit 33MHz = 120Mbytes/s I/O and Front Panel Interface • Four full -duplex 2.5Gbps LC optical transceivers provide hardware support for Fiber Channel, Gigabit Ethernet, Infiniband and other fiber optic based communication standard protocol applications.
    [Show full text]
  • Form 4D Recloser Control Instructions
    Reclosers COOPER POWER Effective September 2017 MN280049EN Supersedes January 2012 (S280-104-1) SERIES Form 4D Microprocessor-based pole-mount recloser control installation and operation instructions Figure 1. Form 4D microprocessor-based pole-mount recloser control Applicable to the following serial numbers: ●● Type KME4DPB control: serial number CP571231527 and above, applies to control-powered NOVA Form 4D ●● Type KME4DPA control: serial number CP571231477 control for use with control-powered reclosers. and above, applies to Form 4D control for use with W, VS, and auxiliary-powered NOVA reclosers. DISCLAIMER OF WARRANTIES AND LIMITATION OF LIABILITY The information, recommendations, descriptions and safety notations in this document are based on Eaton Corporation’s (“Eaton”) experience and judgment and may not cover all contingencies. If further information is required, an Eaton sales office should be consulted. Sale of the product shown in this literature is subject to the terms and conditions outlined in appropriate Eaton selling policies or other contractual agreement between Eaton and the purchaser. THERE ARE NO UNDERSTANDINGS, AGREEMENTS, WARRANTIES, EXPRESSED OR IMPLIED, INCLUDING WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY, OTHER THAN THOSE SPECIFICALLY SET OUT IN ANY EXISTING CONTRACT BETWEEN THE PARTIES. ANY SUCH CONTRACT STATES THE ENTIRE OBLIGATION OF EATON. THE CONTENTS OF THIS DOCUMENT SHALL NOT BECOME PART OF OR MODIFY ANY CONTRACT BETWEEN THE PARTIES. In no event will Eaton be responsible to the purchaser or user in contract, in tort (including negligence), strict liability or other-wise for any special, indirect, incidental or consequential damage or loss whatsoever, including but not limited to damage or loss of use of equipment, plant or power system, cost of capital, loss of power, additional expenses in the use of existing power facilities, or claims against the purchaser or user by its customers resulting from the use of the information, recommendations and descriptions contained herein.
    [Show full text]
  • 4DSP FM482 Manual (Pdf)
    Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Abaco Systems / 4DSP FM482V1 at our website: Click HERE FM482 user manual V1.4 FM482 User Manual 4DSP Inc. 955 S Virginia Street, Suite 214, Reno, NV 89502, USA Email: [email protected] This document is the property of 4DSP Inc. and may not be copied nor communicated to a third party without the written permission of 4DSP Inc. 4DSP Inc. 2007 FM482 user manual V1.4 Revision History Date Revision Version 02-01-07 First release 1.0 02-23-07 Updated Pn4 pin allocation table 1.1 03-14-07 Updated clock tree diagram 1.2 04-26-07 Corrected typos 1.3 05-15-09 - Added the technical support chapter and the external 1.4 power warning. - Added external power warning paragraph FM482 User manual May 2009 www.4dsp.com - 2 - FM482 user manual V1.4 Table of Contents 1 Acronyms and related documents ............................................................................. 4 1.1 Acronyms............................................................................................................... 4 1.2 Related Documents ..............................................................................................
    [Show full text]
  • Confidential
    Unit / Module Name: Dual DSP PMC Module Unit / Module Number: SMT417 Used On: PMC Carriers Document Issue: See Revision History Date: See Revision History CONFIDENTIAL Approvals Date Managing Director Software Manager Design Engineer Sundance Digital Signal Processing Inc, 4790 Caughlin Parkway #233, Reno, NV 89509-0907, USA. This document is the property of Sundance and may not be copied nor communicated to a third party without the written permission of Sundance. © Sundance Digital Signal Processing Inc. 2003 Page 1 Revision History Changes Made Issue Initials 5/30/06 First Draft, from 407 0.0 FRH 06/09/06 Revised RSL, added SMA connector, removed SLB, 0.1 BV updated JTAG description, added external power connector, compliance references. 6/16/06 Merged QL JTAG into Xilinx chain for manufacturing 0.2 FRH testing. Separated QL/DSP clocks. Identified RSL allocation for different Virtex devices. 6/22/06 Updated top-level block diagram. Clarified FPGA block 0.3 BV diagram and switch operation. Updated Sec 2.4 regarding XMC standard. Added several illustrative figures. 08/28/06 2.1: Fixed typo in block diagram (SDR SDRAM is used). RFC.2 BV 2.2.5.3, 2.7: Set 64MHz as QL5064 local bus speed. 2.3.1: Added indication of SMT417 actual width. 2.3.4: Changed side 2 max component height to 1.5mm, reflecting change in PCB thickness to 2.0mm. 2.4.3: Added design change for PCIe compatibility. 2.7: Added descriptions of RSLCLK and XMC REFCLK. 2.8: Moved section 3.3 description to this section. 3.3: Added pinout of JTAG header connector.
    [Show full text]
  • Packet Switch Fabrics for Adaptive Optics Systems
    Packet Switching Networks For Adaptive Optics Systems Robert J. Eager Boeing – LTS, Starfire Optical Range, AFRL/DE, KAFB, NM. ABSTRACT High Performance and Extremely Large Adaptive Optics systems place great demands on the data distribution and electronic control sub-systems. These servo-loop sub-systems acquire, process, and drive electro-optical/mechanical devices with large degrees of freedom. Two of the key parameters that affect AO loop performance are latency and jitter. To minimize these parameters, data must be efficiently acquired from sensors, processed into servo commands and then distributed to actuators. In addition to these critical path activities, there is also a requirement to “tap” into many points in the processing pipeline to monitor, characterize and perform high-level corrections. One answer to this communications dilemma is the use of a low-latency serial packet switched network. This paper illustrates the actual performance and flexibility of such a network by describing the high-performance system used at the Starfire Optical Range. The paper will then demonstrate the adaptability of this network architecture to accommodate the more complex communication requirements of extremely large AO systems. 1. INTRODUCTION High Performance and Extremely Large Adaptive Optics systems place great demands on the data distribution and electronic control sub-systems. These systems operate with large (1K+) degrees of freedom and high (1-10 KHz+) sampling rates to achieve optimal loop performance. These characteristics place heavy demands on the electronic communication’s infrastructure to convey data efficiently between the sensors, processing nodes and actuator elements, with minimal latency and jitter. One emerging technology that best addresses these demanding communication requirements is packet switched networks.
    [Show full text]