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Real Time Controller As Built Design Document KECK NEXT GENERATION WAVEFRONT CONTROLLER Real Time Controller As Built Design Document Document : NGWFC_RTC_ASB_001.doc Issue : 1 Date : September 2nd, 2007 Prepared by : MICROGATE ................................................. R.Biasi ................................................. D.Pescoller ................................................. M.Andrighettoni Checked by : ................................................. Approved by : ................................................. Released by : ................................................. September 2nd , 2007 NGWFC Doc. : NGWFC_RTC_ASB_001.doc REAL TIME CONTROLLER Issue : 1 – September 2nd , 2007 As Built Data Package Page : 2 of 158 CHANGE RECORDS SECTION / QA/ REASON/INITIATION ISSUE DATE Author Approved PARAG. QC AFFECTED DOCUMENTS/REMARKS 1 2007.09.02 Microgate All First Issue NGWFC Doc. : NGWFC_RTC_ASB_001.doc REAL TIME CONTROLLER Issue : 1 – September 2nd , 2007 As Built Data Package Page : 3 of 158 TABLE OF CONTENTS 1 ACRONYMS ............................................................................................................................ 11 2 APPLICABLE DOCUMENTS ............................................................................................... 13 3 REFERENCE DOCUMENTS ................................................................................................ 14 4 INTRODUCTION .................................................................................................................... 15 5 SYSTEM OVERVIEW............................................................................................................ 16 6 HARDWARE DESIGN ........................................................................................................... 19 6.1 WIF/WFP HARDWARE ....................................................................................................... 19 6.1.1 Microgate Adaptive Optics crate (MGAOS) .................................................................. 19 6.1.1.1 AdOpt BCU board ................................................................................................. 20 6.1.1.1.1 Main system logic ............................................................................................ 22 6.1.1.1.2 Main real time computational unit ................................................................... 22 6.1.1.1.3 Reconfiguration logic ....................................................................................... 22 6.1.1.1.4 Non volatile storage memory (FLASH) ........................................................... 23 6.1.1.1.5 SRAM memory ................................................................................................ 23 6.1.1.1.6 SDRAM memory ............................................................................................. 23 6.1.1.1.7 High speed backplane bus ................................................................................ 24 6.1.1.1.8 Diagnostic backplane bus ................................................................................. 24 6.1.1.1.9 High speed communication links ..................................................................... 24 6.1.1.1.10 Diagnostic communication link...................................................................... 24 6.1.1.1.11 Expansion programmable input/output ports ................................................. 24 6.1.1.1.12 Serial links ...................................................................................................... 25 6.1.1.1.13 „Slow‟ fiber input/output ................................................................................ 25 6.1.1.1.14 Power supply .................................................................................................. 25 6.1.1.1.15 Direct backplane bus signals .......................................................................... 26 6.1.1.1.16 High speed communication description ......................................................... 26 6.1.1.1.17 Diagnostic communication description .......................................................... 28 6.1.1.1.18 Boards layout .................................................................................................. 30 6.1.1.2 AdOpt DSP BOARD ............................................................................................. 32 6.1.1.2.1 DSP board block scheme .................................................................................. 32 6.1.1.2.2 Main System Logic .......................................................................................... 34 6.1.1.2.3 Computational devices ..................................................................................... 34 6.1.1.2.4 Configuration Logic ......................................................................................... 34 6.1.1.2.5 Non volatile storage memory (FLASH) ........................................................... 34 6.1.1.2.6 SRAM memory ................................................................................................ 34 6.1.1.2.7 SDRAM memory ............................................................................................. 34 6.1.1.2.8 High speed backplane bus ................................................................................ 35 6.1.1.2.9 Diagnostic backplane bus ................................................................................. 35 6.1.1.2.10 The diagnostic serial monitor ......................................................................... 35 6.1.1.2.11 Direct backplane bus signals .......................................................................... 35 6.1.1.2.12 Power supply .................................................................................................. 35 NGWFC Doc. : NGWFC_RTC_ASB_001.doc REAL TIME CONTROLLER Issue : 1 – September 2nd , 2007 As Built Data Package Page : 4 of 158 6.1.1.2.13 Mechanical configuration ............................................................................... 36 6.1.1.3 AdOpt HVC board ................................................................................................. 38 6.1.1.3.1 DSP board analog input section ....................................................................... 39 6.1.1.3.1.1 DSP board analog output section .............................................................. 39 6.1.1.3.1.2 High voltage drives daughter-board .......................................................... 40 6.1.1.3.2 Power dissipation ............................................................................................. 44 6.1.1.3.3 Mechanical configuration ................................................................................. 44 6.1.1.3.4 Performance estimate through numerical simulation ....................................... 45 6.1.1.3.5 Experimental tests ............................................................................................ 50 6.1.1.3.5.1 Test setup ................................................................................................... 50 6.1.1.3.5.2 Test description and results ....................................................................... 51 6.1.1.3.6 CLMP loop tuning ............................................................................................ 56 6.1.1.3.7 CLMP loop servo oscillation detection ............................................................ 57 6.1.1.4 Backplane ............................................................................................................... 58 6.1.1.5 Reset circuitry ........................................................................................................ 58 6.1.1.6 WFS to BCU and BCU to DM HVA interface boards .......................................... 59 6.1.2 VME components ........................................................................................................... 59 6.1.2.1 CPU board .............................................................................................................. 59 6.1.2.2 IRIG decoder .......................................................................................................... 59 6.1.3 Power dissipation ........................................................................................................... 60 6.1.4 Power supply system ...................................................................................................... 61 6.1.4.1 VME and MGAOS power supply .......................................................................... 61 6.1.4.2 HVC supply............................................................................................................ 61 6.1.5 Mechanical aspects and cooling .................................................................................... 62 6.1.5.1 Cooling ................................................................................................................... 62 6.2 TRS HARDWARE ................................................................................................................. 62 6.2.1 Storage Server ................................................................................................................ 63 6.2.2 Disk array ...................................................................................................................... 63 6.3 HW INTERFACES ................................................................................................................. 64 6.3.1 Internal HW interfaces ..................................................................................................
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