Serial Front Panel Data Port (FPDP) Draft Standard VITA 17.1 – 199x
Draft 0.6 January 30, 2002
This draft standard is being prepared by the VITA Standards Organization (VSO) and is unapproved.
Do not specify or claim conformance to this draft standard.
VSO is the Public Domain Administrator of this draft standard and guards the contents from change except by sanctioned meetings of the task group under due process.
VITA Standards Organization 7825 East Gelding Drive, Suite 104 Scottsdale, AZ 85260 Ph: 602-951-8866 Fx: 602-951-0720 URL: http://www.vita.com
Table of Contents
Chapter 1- Introduction...... 5 1.1 Standard Terminology...... 5 Chapter 2 - Scope and Purpose...... 7 2.1 Scope ...... 7 2.2 Purpose ...... 7 2.3 References ...... 7 Chapter 3 ...... 8 Chapter 4 - Overview ...... 9 4.1 General...... 9 Chapter 5 - Background...... 11 5.1 Parallel FPDP Signals...... 11 5.2 Parallel FPDP Frame Structure...... 13 Chapter 6 - System Specifications...... 15 6.1 Serial FPDP System Configurations...... 15 6.1.1 Basic Serial FPDP Configuration ...... 16 6.1.2 Flow Control (Optional)...... 16 6.1.3 Bi-directional Data Flow (Optional) ...... 18 6.1.4 Copy Mode (Optional)...... 19 6.1.5 Copy/Loop Mode (Optional)...... 21 Chapter 7 - Link Specifications...... 23 7.1 Overview ...... 23 7.2 Link Bandwidth...... 23 7.3 Serial FPDP Transmission Frames ...... 24 7.3.1 8B/10B Encoding / Decoding ...... 24 7.3.2 Serial FPDP Control Signals...... 26 7.3.3 Fiber Frames...... 27 Chapter 8 - Physical Specifications ...... 33 8.1 Link Interface ...... 33 Appendix A - Interoperability Issues...... 34
List of Figures
Figure 4-1 Typical Parallel FPDP to Serial FPDP Application...... 9 Figure 4-2 Serial FPDP Bi-directional Example ...... 10 Figure 6-1 Basic Serial FPDP system configuration...... 16 Figure 6-2 Serial FPDP with Flow Control...... 16 Figure 6-3 Bi-directional Serial FPDP Link...... 18 Figure 6-4 Serial FPDP Copy Mode...... 19 Figure 6-5 Serial FPDP Copy/Loop Mode ...... 21 Figure 7-1 Typical Serial FPDP Process ...... 23 Figure 7-2 Serial FPDP Fiber Frames ...... 28
List of Tables
Table 5-1 Parallel FPDP Signals ...... 12 Table 7-1 Fibre Channel to Serial FPDP Ordered Sets...... 25 Table 8-1 Media Interfaces...... 33
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 2 January 30, 2002 Abstract
This standard defines “Serial FPDP”, a high-speed low-latency serial communications protocol for use in high-speed data transfer applications, typically using a fiber optic link. As the name implies, it is directly related to Standard Front Panel Data Port (FPDP), deriving its serial protocol from the defined protocol and control signals of FPDP. Serial FPDP currently supports two link speeds, 1.0625 Gbaud and 2.5 Gbaud. These two link speeds can support data transfer rates in excess of 105 MBps and 245 MBps respectively.
Comments, Corrections, Additions
Currently, all comments, corrections, or additions should be addressed to:
Ron Taulton Systran Corporation 4126 Linden Ave. Dayton, OH 45432-3068 Ph: 937-252-5601 x231 Fax: 937-258-2729 email: [email protected]
Draft History
Draft Date Comments Number D0.1 July 21, 1999 Preliminary Draft. D0.2 September 22, 1999 Total Revision. D0.3 February 24, 2000 Minor modifications. Changed designation from VITA 33 to VITA 17.1. Provided to VITA web site. D0.4 November 10, 2000 Detailed Update (not Published on VITA Website). D0.5 February 26,2001 Detailed Update to include submitted comments. D0.6 January 28,2002 Inclusion of comments and changes suggested by task group. Expanded copy and copy/loop sections to include a requirement for a copy or copy/loop master mode – adding idles to allow for receive and re-transmit clock differences.
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 3 January 30, 2002 Task Group Members
The VITA-17.1 Task Group consists of the following members:
First Last Company email address Status
Tom Bohman VMETRO [email protected] Sponsor Danny Cohen Sun [email protected] Participant Richard Jaenicke Mercury Computer Systems, Inc. [email protected] Participant Jonathan Jones Interactive Circuits & Systems [email protected] Sponsor Jim Koser FCI/Berg Electronics [email protected] Participant Tony Lavely Mercury Computer Systems, Inc. [email protected] Participant Mike Macpherson MITRE [email protected] Observer Stephen Paavola SKY Computers, Inc. [email protected] Participant Elwood Parsons AMP [email protected] Observer Doug Patterson VISTA Controls Corporation [email protected] Observer Greg Rocco Mercury Computer Systems, Inc. Observer John Rynearson VITA [email protected] Participant Ron Seese Chrislin Industries, Inc. [email protected] Observer Hermann Strass Technology Consulting [email protected] Participant Ron Taulton Systran Corporation [email protected] Sponsor Larry Thompson Naval Surface Warfare Center [email protected] Observer Istvan Vadasz Force Computers [email protected] Observer
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 4 January 30, 2002 Chapter 1- Introduction
Serial FPDP is a high-speed low-latency data-streaming serial communications protocol for use in high- speed real-time data transfer applications. It currently is defined to operate at two distinct link speeds, 1.0625 Gbaud and 2.5 Gbaud – with sustained data rates in excess of 105 and 245 Mbytes/sec. respectively. Serial FPDP can also operate over long distances (up to 10 kilometers) using fiber optic cable.
1.1 Standard Terminology
To avoid confusion and to make very clear what the requirements for compliance are, many of the para- graphs in this standard are labeled with keywords that indicate the type of information they contain. The keywords are listed below:
Rule Recommendation Suggestion Permission Observation
These key words are used as follows:
Rule
Recommendation
Suggestion
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 5 January 30, 2002 Permission
Observation
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 6 January 30, 2002 Chapter 2 - Scope and Purpose
2.1 Scope
This document defines “Serial FPDP”, a serial communications interface. Included in this definition are the data frame structure, the link layer protocol, and the physical media requirements.
2.2 Purpose
The purpose of this standard is to allow products to be designed to work with other Serial FPDP products. The degree of interoperability will depend on the specific options implemented. Although all options are supported by this standard, all products are not required to support all options.
2.3 References
ANSI X3.230-1994, Fibre Channel Physical and Signaling Interface (FC-PH) ANSI X3.272-1996, Fibre Channel Arbitrated Loop (FC-AL) ANSI/VITA 17-1998, Front Panel Data Port Specifications
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 7 January 30, 2002 Chapter 3
Definitions
Parallel FPDP The industry standard Front Panel Data Port (FPDP) as specified in the standard document ANSI/VITA 17-1998, Front Panel Data Port Specifications.
Host-Bus The interface side of a Serial FPDP device that provides date to a Serial FPDP transmitter or receives data from a Serial FPDP receiver.
Serial FPDP Transmitter A Serial FPDP interface that has the ability to receive data via from a Host-Bus and transmit as serial data using the Serial FPDP protocol.
Serial FPDP Transmitter A Serial FPDP interface that has the ability to receive from a Host- Bus interface and transmit serial data useing the Serial FPDP protocol.
Serial FPDP Trasmission Frame The Serial FPDP data and control word frames that are sent across the serial link. Also referred to a Fiber Frame in this document.
Fiber Frame The Serial FPDP data and control word frames that are sent across the serial link. Although fiber optics is considered the most common media, Fiber Frames can be sent across other media types (i.e. copper).
Flow Control The ability of the Serial FPDP receiver to communicate to the transmitter a pending Receive FIFO overflow condition, allowing the transmitter to temporarily back off sending data.
Copy Mode A Serial FPDP option that permits a receiving node to re-transmit the incoming control words and data stream to another receiving node. This provides for a limited broadcast of the data (limited to 5 nodes – 4 copies).
Copy/Loop Mode A Serial FPDP option that allows a receiving node to re-transmit the incoming control words and data to another receiving node and set the flow control signal. Setting the flow control signal permits any of the receiving nodes to back off the transmitter.
Copy Master Mode An optional mode for a Serial FPDP transmitter which supports the Copy and Copy/Loop modes. This mode adds additional IDLE ordered sets to the beginning of each transmission frame.
MByte / MB It is customary to have MB equal to 1,048,576 when referring to the size of memory and equal to 1,000,000 bytes when used in reference to data rates. This standard is using it to refer to data rates and so an MB is equal to 1,000,000 bytes in this standard.
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 8 January 30, 2002 Chapter 4 - Overview
4.1 General
The purpose of this standard is to define “Serial FPDP”, a high-speed low-latency serial communications link for use in high-speed data transfer applications. As the name implies, it is directly related to standard Front Panel Data Port (FPDP), deriving its serial protocol from the defined protocol and control signals of FPDP. In order to avoid confusion with the subject of this standard (Serial FPDP), this document will refer to this standard FPDP as “Parallel FPDP.”
Parallel Front Panel Data Port (FPDP) is a 32-bit parallel synchronous bus intended to provide high- speed data transfer between FPDP connections at speeds up to 160MB/s. Parallel FPDP is an existing ANSI/VITA standard (ANSI/VITA 17-1998, Front Panel Data Port Specifications). Although widely used for high-speed communications within a single chassis or rack of equipment, one of the limitations of Parallel FPDP is that link connections are limited to relatively short distances – usually 1 to 3 meters. One of the direct advantages and common applications of Serial FPDP is the extension of a Parallel FPDP connection over much greater distances – in some cases up to 10 kilometers (assuming the selection of appropriate optical transceiver and fiber optic cable).
Figure 4-1 provides a conceptual example of this typical Serial FPDP implementation. It demonstrates a possible application in which Serial FPDP is used as a direct link between two Parallel FPDP connections. It shows the conversion from Parallel FPDP to Serial FPDP on the source side, transmission across the link, and the reverse conversion, Serial FPDP to Parallel FPDP on the destination side. This figure represents one very basic configuration of Serial FPDP and is provided only as a conceptual reference to show the relationship between Parallel FPDP and Serial FPDP.
The area delineated by the triple line in figure 4-1 conceptually defines the scope of this standard. The interface represented by the heavy solid line represents what this document refers to as the Host-Bus Interface. The concept of the Host-Bus is used throughout this standard to describe the interface that provides data to, or receives data from, the serial link. The Host-Bus Interface provides the data to the Serial FPDP OUT (Transmitter) and receives the data from the Serial FPDP IN (Receiver). In the particular case shown in Figure 4-1, the Host-Bus would be Parallel FPDP.
Serial FPDP Dat Serial FPDP Data OUT IN Destination Data Source With With FPDP IN FPDP OUT Flow Control FPDP-RM FPDP IN FPDP-TM (Optional) FPDP OUT FPDP-R FPDP-RM FPDP-TM FPDP-R Host-Bus Interface
Parallel FPDP Parallel FPDP Connection Connection Up to10 kilometer (Serial FPDP)
Figure 4-1 Typical Parallel FPDP to Serial FPDP Application Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 9 January 30, 2002 The flow control signal shown in figure 4-1 is embedded as part of the Serial FPDP framing protocol structure – the same structure that is used to transmit data. This provides the option of transmitting an independent data stream in the opposite direction – providing for bi-directional data flow. This bi- directional functionality is an option within Serial FPDP. In this bi-directional configuration, both data and flow control are transmitted across each connection on the link. Figure 4-2 shows this bi-directional capability.
Serial FPDP Data & Flow Serial FPDP OUT Control IN (Optional) IN OUT
Data & Flow Control (Optional) Host-Bus Interface
Figure 4-2 Serial FPDP Bi-directional Example
In addition to Parallel FPDP (ANSI/VITA 17-1998), Serial FPDP is a standard whose implementation takes advantage of elements of other existing current standards. The Serial FPDP speed of 1.0625 Gbaud corresponds to the link speed defined for 1 Gb Fibre Channel (FC-0) and the encoding / decoding method corresponds to that used in Fibre Channel (FC-1), as well as other technologies. These are described in detail in the Fibre Channel Physical and Signaling Interface (FC-PH) standard (ANSI X3.230-1994). The 2.5 Gbaud link speed correspons to 2 times Gigibit Ethernet speed and also uses the 8B/10B encoding. Using existing standards and the technology that supports those standards facilitates the use of more common and more available components in Serial FPDP designs. Although related at a basic level, Serial FPDP is not meant to be an extension of these existing standards.
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 10 January 30, 2002 Chapter 5 - Background
5.1 Parallel FPDP Signals
Serial FPDP is conceptually based on the control signals and data structure currently used by Parallel FPDP and consequentially, allows a straightforward implementation from Parallel FPDP to Serial FPDP. In designs with a Parallel FPDP Host-Bus, the protocol defined in this specification is a mapping of these signals into a serial format for transmission across the serial link. The frame structure used by Parallel FPDP can also be duplicated in a serial format with Serial FPDP. In non-Parallel FPDP Host-Bus designs, such as PCI, these parallel signals need to be simulated or replicated. Table 5-1 lists these Parallel FPDP signals and provides a brief description as defined in the Parallel FPDP specification. For more detailed information on these signals, refer to the Front Panel Data Port Specifications document, ANSI/VITA 17-1998.
Permission 5.1.1:
Although Serial FPDP is based on the data and signal structure of Parallel FPDP, Serial FPDP does not require Parallel FPDP to be the Host-Bus or connection as the front-end (input) to a Serial FPDP “Transmitter” design – and it does not require Parallel FPDP to be the Host-Bus or connection as the back-end (output) of a Serial FPDP “Receiver” design. The Host-Bus section of a Serial FPDP design is not considered part of this standard. Designers MAY design either a standard Host-Bus (such as Parallel FPDP or PCI) or a custom Host-Bus interface.
Observation 5.1.1:
Although the Parallel FPDP clock signals STROBE, PSTROBE, and /PSTROBE would need to be considered if implementing a Parallel FPDP Host-Bus front or back-end to a Serial FPDP design, they are not used by Serial FPDP. They are listed in Table 5-1 for reference only.
Observation 5.1.2:
Although not required for Serial FPDP, a Serial FPDP Receiver design with a Parallel FPDP Host-Bus must generate the necessary Parallel FPDP clock signals to clock the FPDP signals out of the Host-Bus interface.
Observation 5.1.3:
The Parallel FPDP signals /DVALID and /SYNC determine the Parallel FPDP frame structure. They are not transmitted as part of the Serial FPDP Frame header information. As a result:
· In a Parallel FPDP Host-Bus configuration with a Parallel FPDP data source, these signals are used to determine the type of Serial FPDP Frame to be generated by the Serial FPDP transmitter.
· In a Parallel FPDP Host-Bus configuration with a Parallel FPDP data destination, these signals must also be generated and sent to the Parallel FPDP Host-Bus based on the type of Serial FPDP Frame received by the Serial FPDP receiver.
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 11 January 30, 2002 Recommendation 5.1.1:
The Parallel FPDP /SUSPEND signal, which is used for Parallel FPDP flow control SHOULD NOT be confused with the Serial FPDP flow control signal (STOP), although they are related.
In a Parallel FPDP Host-Bus design, a Serial FPDP “STOP” signal SHOULD result in the Parallel FPDP /SUSPEND signal being asserted, but this is SHOULD NOT be implemented as a direct mapping of the STOP signal (Serial FPDP STOP ¹ Parallel FPDP /SUSPEND).
It SHOULD be an indirect relationship, with a typical example as follows:
(1) The Serial FPDP STOP signal stops transmissions from the Serial FPDP transmit FIFO. (2) This creates a pending overflow condition in the Serial FPDP transmit FIFO. (3) This Serial FPDP transmit FIFO pending overflow condition asserts the Parallel FPDP /SUSPEND signal (4) The Parallel FPDP /SUSPEND stops the FPDP source.
SIGNAL NAME COMMENTS D<31:00> Data Bus 32-bit data bus driven by FPDP/TM Interfaces. /DIR Data Direction The FPDP/TM asserts /DIR low. /DVALID Data Valid When asserted, /DVALID indicates that the data bus has valid data. This signal is generated by the FPDP/TM. STROB Data Strobe STROB is a free running clock supplied by the FPDP/TM. FPDP/R and FPDP/RM interfaces should sample the data with the rising edge of STROB when /DVALID is asserted. /NRDY Not Ready /NRDY should be asserted by FPDP/R or FPDP/RM interfaces, when they are not ready to receive data. The FPDP/TM should sample this signal until the FPDP/R or FPDP/RM brings it high, at which time the transfer should commence. Since /NRDY is asynchronous to STROB, the FPDP/TM should double synchronize to it before sampling its state; this avoids metastability problems. PIO1, PIO2 Programmable The PIO signals are programmable I/O lines. They may be configured as inputs or I/O outputs. PSTROBE +PECL Data This signal along with /PSTROBE may be generated by the FPDP/TM as an Strobe optional differential ±PECL data strobe. PSTROBE is the positive version of the differential clock and has the same polarity as STROB. For high data rate applications, the differential ±PECL data strobe should be used instead of STROB. /PSTROBE -PECL Data This signal is the negative version of the differential PECL data strobe. Strobe Reserved No connection should be made to reserved signals. /SUSPEND Suspend Data /SUSPEND should be generated by FPDP/R or FPDP/RM interfaces to inform the data source of a pending FIFO overflow condition. The FPDP/TM may delay for no more than 16 cycles in total before suspending the transfer by negating /DVALID. Since /SUSPEND is asynchronous to STROB, the FPDP/TM should double-synchronize to it before sampling its state; this avoids metastability problems. /SYNC Sync Pulse The FPDP/TM must provide a Sync pulse to FPDP/R and FPDP/RM interfaces to synchronize data transfers when transmitting Single Frame data, Fixed Size Repeating Frame data or Dynamic Size Repeating Frame data. FPDP/R and FPDP/RM interfaces should wait for the Sync pulse before accepting data. FPDP/R and FPDP/RM interfaces should start to accept data on the first Data Valid period following the Sync pulse.
Table 5-1 Parallel FPDP Signals
(This table is not part of this standard but is provided for information only)
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 12 January 30, 2002 5.2 Parallel FPDP Frame Structure
This section is not part of this standard but is provided for information only. Designer should refer to the FPDP Specification (ANSI/VITA 17-1998, Front Panel Data Port Specification).
Parallel FPDP defines four different types of data frames: (1) Unframed Data, (2) Single Frame Data, (3) Fixed Size Repeating Frame Data, and (4) Dynamic Size Repeating Frame Data. A brief description of each frame type is provided here. It is important for the Serial FPDP designer to understand the frame structure of Parallel FPDP, because the Serial FPDP Frame structure is based on these Parallel FPDP concepts. Serial FPDP supports all four Parallel FPDP frame types.
Unframed data
· Used when the source and the organization of the data is not important. · Used when the Parallel FPDP receivers do not need to be synchronized to the data stream. · /SYNC is not used.
When unframed data is transmitted onto the Parallel FPDP bus, no synchronization is required. Thus, the Parallel FPDP-TM must not generate /SYNC, and the Parallel FPDP-RM and Parallel FPDP-R devices must not require a /SYNC pulse in order to correctly receive data.
Single frame data
· Synchronization must occur prior to data to which it applies. · Synchronization occurs between data blocks. · /SYNC must be asserted before /DVALID is asserted. · Synchronization occurs infrequently, perhaps only once.
When single frame data is transmitted onto the Parallel FPDP bus, the Parallel FPDP-TM must assert a /SYNC pulse before valid data starts being transmitted. Valid data is transmitted when the data valid signal /DVALID is asserted. Thus, a /SYNC pulse must be asserted before /DVALID is asserted when transmitting single frame data. After a /SYNC pulse is asserted, the Parallel FPDP-RM and Parallel FPDP-R devices should not accept data until the first STROBE period after /DVALID is asserted. The /SYNC pulse does not have to be asserted again until before the start of the next data transmission.
Fixed size repeating frame data
· Synchronization must occur prior to data to which it applies. · Synchronization occurs at the same time the last data word in the block before is transferred. · /SYNC must be asserted at the end of the data block while /DVALID is still asserted. · Because synchronization occurs at the end of the data block, the first data block will not be synchronized. · Synchronization occurs frequently. · All data frames are the same size.
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 13 January 30, 2002 Dynamic size repeating frame data
· Synchronization must occur prior to data to which it applies. · Synchronization occurs at the same time the last data word in the block before is transferred. · /SYNC must be asserted at the end of the data block while /DVALID is still asserted. · Because synchronization occurs at the end of the data block, the first data block will not be synchronized. · Synchronization occurs frequently. · Data frames may vary in size.
When fixed or dynamic size repeating frame data is transmitted onto the Parallel FPDP bus, the Parallel FPDP-TM must assert a SYNC pulse while /DVALID is already asserted. The /SYNC pulse must be asserted at the same time as the last data item of every frame. The Parallel FPDP-RM and Parallel FPDP-R devices must recognize that the current data is the last data item in current frame when both /SYNC and /DVALID are asserted. Since /SYNC is asserted at the end of a frame, the first data frame transmitted will not be synchronized. As a result, the system designer may wish to discard this first unsynchronized data frame. All data frames are the same size when fixed size repeating frame data is transmitted.
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 14 January 30, 2002 Chapter 6 - System Specifications
6.1 Serial FPDP System Configurations
This section discusses some of the standard and optional system configurations that are supported by Serial FPDP. A Serial FPDP “system” is considered to be two or more Serial FPDP interfaces and the appropriate interconnecting cabling.
The configurations / features discussed in this section include:
· Basic System · Flow Control · Bi-directional Data Flow · Copy Mode · Copy/Loop Mode
Serial FPDP is a data streaming protocol, rather than a network protocol. The protocol header does not provide for node identification or addressing. It is a point-to-point communications protocol and does not support loop arbitration.
Rule 6.1.1:
Serial FPDP does not provide arbitration on the link; therefore a Serial FPDP link SHALL have only one transmitter.
Rule 6.1.2:
The average variance of the transmit clock (or re-transmit clock in the case of copy or copy/loop mode) SHALL not exceed 100 PPM.
Observation 6.1.1:
The “single transmitter” rule is not violated in a bi-directional Serial FPDP configuration. If a bi- directional Serial FPDP link is implemented, each direction is treated as a separate independent link, each one with a single transmitter (Refer to Bi-directional Data Flow – Section 6.1.3).
Permission 6.1.1:
Although a Serial FPDP link is limited to a single Transmitter, a Serial FPDP link MAY have more than one receiver (Refer to Copy Mode – Section 6.1.4).
Observation 6.1.2:
Use of flow control with multiple receivers is limited to loop type configurations (Refer to Copy/Loop Mode – Section 6.1.5).
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 15 January 30, 2002 6.1.1 Basic Serial FPDP Configuration
A basic Serial FPDP system consists of a single transmitter, a single receiver, and an inter-connecting cable. This configuration does not provide for any feedback or flow control. Figure 6-1 shows this basic configuration
Data TX RX
Figure 6-1 Basic Serial FPDP system configuration
Observation 6.1.1.1:
The single transmitter, single receiver configuration assumes that the receiver end of the system is capable of receiving and processing the incoming data at a rate sufficient to remain ahead of the transmitter. Failure to assure this transmitter / receiver data rate relationship can result in receiver FIFO overflow and loss of data.
6.1.2 Flow Control (Optional)
Serial FPDP supports flow control as an option. The flow control signal is transmitted as part of the Serial FPDP frame structure. Flow control is set by the receiver and returned to the transmitter by a separate cable. Figure 6-2 shows the basic Serial FPDP configuration with flow control.
Data TX RX RX TX Flow Control
Figure 6-2 Serial FPDP with Flow Control
Rule 6.1.2.1:
A Serial FPDP Link that uses the Flow Control option SHALL consist of a data source or transmit node, a data destination or receive node, and two independent unidirectional interconnecting cables with signals flowing in opposite directions. This requires that the receive node have a transmit capability and the transmit node have receive capability.
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 16 January 30, 2002 Rule 6.1.2.2:
The return signals containing the flow control information SHALL follow the same link protocol as is used to transmit and receive data. This is facilitated by the fact that the flow control signal is an ordered set that is embedded in the header information of the standard data protocol (Refer to Serial FPDP Transmission Frames - Section 7.3).
Rule 6.1.2.3:
The flow control signal is an ordered set that is sent as part of the Serial FPDP frame structure (Refer to Serial FPDP Transmission Frames - Section 7.3). When flow control is implemented (without bi-directional data flow) and the return cable is connected, the receive node SHALL continuously send empty data frames back to the transmitter.
Rule 6.1.2.4:
When flow control is disabled at the Serial FPDP transmitter, the receiving node SHALL still transmit the ordered set for flow control (if it has a transmitter available). When flow control is disabled, the transmitter SHALL transmit data regardless of any flow control it is receiving.
Observation 6.1.2.1:
When a Serial FPDP receiver is designed to accept a continuous stream without the need for flow control, it is OK to always transmit flow control indicating it is ready for data regardless of what its input FIFO state is.
Observation 6.1.2.2:
Flow control being disabled allows the protocol to work under the following conditions:
· When there is only a single fiber from the transmitting end point to the receiving end point.
· The transmit and receive fibers do not go to the same end point.
Flow control is set by the receiver when the receive FIFO is about to go into an overflow condition, which would result in the loss of data. Since the transmission of data does not cease instantaneously, this signal must be set to leave enough space in the receive FIFO to compensate the receipt of data based on any delays. Designers must consider the delay between when the receiver actually sets the flow control suspend signal, when the transmit node actually stops the transmission of data, and when the data flow actually stops at the receive node. The two variables that impact these delays are the length of the cable (both directions) and the amount of time required for the transmitter to actually suspend the data transmission.
Rule 6.1.2.5:
When flow control is enabled, the flow control suspend signal SHALL be asserted by the receiver at a point which provides sufficient additional capacity in the receive FIFO to store the data that may be received during the time interval between the assertion of the flow control suspend signal (STOP) and the actual stoppage of data at the receiver.
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 17 January 30, 2002 Rule 6.1.2.6:
The maximum delay between receipt of the flow control suspend signal (STOP) at the Serial FPDP Transmitter and the actual stoppage of the data transmission SHALL be sixteen (16) cycles of the 32-bit transmit clock.
Rule 6.1.2.7:
On receipt of the flow control suspend signal (STOP) at the Serial FPDP Transmitter, the current Fiber Frame being transmitted SHALL be terminated immediately, even if in mid-frame. This is necessary to insure compliance with Rule 6.1.2.6.
Observation 6.1.2.3:
The amount of additional capacity needed in the receive FIFO due to cable delay varies depending on the length of the cable and the link rate (either 1.0625 Gbaud or 2.5 Gbaud). Assuming 5 ns/m for the speed of light, a 100 m cable length (50m from transmitter to receiver and return), provides 500 ns of delay due to the cable. Each byte in a 1.0625 Gbaud link takes 9.41 ns – and each 32-bit word takes 37.64 ns. A 100-meter cable would hold approximately 13- 14 words. A 2.5 Gbaud link of the same cable length would hold 32-33 words.
6.1.3 Bi-directional Data Flow (Optional)
Serial FPDP supports optional bi-directional data flow. Since flow control is sent across the return cable using standard Serial FPDP frames, this cable can also be used to transmit data. Figure 6-3 shows a bi- directional Serial FPDP configuration with flow control.
Data & Flow Control TX RX RX TX Data & Flow Control
Figure 6-3 Bi-directional Serial FPDP Link
Rule 6.1.3.1:
When implementing a bi-directional data flow, each Serial FPDP Transmitter SHALL be implemented independent of each other (except for flow control). A bi-directional Serial FPDP link is actually two separate links.
Rule 6.1.3.2:
The only dependency relationship between the transmit side and the receive side of a bi- directional Serial FPDP interface SHALL be flow control. This relationship is identical to a single directional interface with Flow Control (using two cables).
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Serial FPDP, VITA 17.1 – 199x/Draft 0.6 18 January 30, 2002 Rule 6.1.3.3:
Any dependency between opposite flowing data streams in a bi-directional link SHALL be implemented at the application level. The exception to this is flow control (See Rule 6.1.3.2).
Rule 6.1.3.4:
The flow control signals for each data transmitter in a bi-directional configuration SHALL be embedded in the data frames of the opposite flowing data streams.
Observation 6.1.3.1:
The same rules that apply to flow control for a single direction data link apply to a bi-directional link.
Observation 6.1.3.2:
The difference between a single direction Serial FPDP link with flow control and a bi-directional Serial FPDP is that the single directional link transmits empty data frames back to the transmitter, while the bi-directional link transmits data frames containing data.
6.1.4 Copy Mode (Optional)
Serial FPDP supports optional copy mode. A Serial FPDP receiver designed with copy mode allows the data and control signals sent by the original Serial FPDP transmitter to be re-transmitted out the transmit section of the receiver. This can be used to send the same bit stream to multiple end points and is very useful for data recording. Figure 6-4 shows the Serial FPDP Copy Mode.
Data Data
TX RX RX
Copy Mode
Figure 6-4 Serial FPDP Copy Mode
Rule 6.1.4.1:
If implemented, the optional Serial FPDP Copy Mode SHALL re-transmit all data and control signals generated by the originating transmitter. The only exception to this would be IDLE ordered sets which may be added or deleted in the process (See Observation 6.1.4.4).
Rule 6.1.4.2:
In the copy/loop mode, the maximum amount of time between receipt of data by a Serial FPDP receiver and the re-transmission of the data on the next segment of the link is thirty-two (32) 32- bit clock cycles.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 19 January 30, 2002 Observation 6.1.4.1:
In the normal copy mode, flow control is not supported. There is no return line to the transmitter.
Observation 6.1.4.2:
In the copy mode, the Serial FPDP receiver is not required to de-serialize and decode the incoming data prior to re-transmitting (copy). Flow control is not used in the normal copy only mode. Refer to section 6.1.5 (Copy/Loop Mode) on the use of flow control with multiple receivers.
Observation 6.1.4.3:
The optional Serial FPDP copy mode is not limited to a single receiver. Chaining together a series of receivers with the copy mode active allows the original data and control signals to be broadcast to multiple receiver nodes.
Rule 6.1.4.3:
The maximum number of receiver nodes in a copy mode chain the SHALL be limited to five (5), or six (6) total nodes including the transmitter.
Permission 6.1.4.1:
A Serial FPDP Receiver with the Copy Mode Option MAY either (1) just receive the data, (2) receive the data and re-transmit it, or (3) ignore the data and simply re-transmit it only.
When implementing the copy mode, there are two possible methods for generating the re-transmit clock: (1) Mapping the receive clock directly to the re-transmit path without any decoding of the data; or use the local transmit clock to re-transmit the data independent of the receive clock. In the first method, additional jitter is typically introduced into the circuit while in the second method, the variance or skew between receive and transmit clocks must be taken into account. Both methods will support copy mode, while Method 2 is required to support copy/loop mode. The terms “Method 1” and “Method 2” will be used as references in this document to distinguish the two approaches.
Recommendation 6.1.4.1:
Although not required by this standard, designers SHOULD strongly consider applying Method 2 when implementing the Serial FPDP copy mode.
Observation 6.1.4.4:
Designers are advised refer to the referenced document, ANSI X3.272-1996, Fibre Channel Arbitrated Loop (FC-AL) specification, Annex G, for a detailed discussion and example of the Clock skew smoothing function, the recommended technique for implementing Method 2 of the Serial FPDP copy mode.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 20 January 30, 2002 Rule 6.1.4.4:
When implementing the Serial FPDP copy mode Method 2, the designer SHALL provide for a selectable Copy Master Mode. This Copy Master Mode SHALL provide the transmitter with the ability to add a minimum of three (3) additional IDLE ordered sets to each Fiber Frame type. This translates to four (4) IDLEs in the Normal Data and Sync with Data Fiber frames, and three (3) IDLEs and a SWDV ordered set in a Sync without Data Fiber frame. (Refer to section 7.3 for a discussion of the various Fiber frames). These extra IDLEs are necessary to support the addition/deletion of IDLEs method of handling the clock variations required in Method 2.
Recommendation 6.1.4.2:
Since adding additional IDLEs to the Serial FPDP Fiber frames has the effect of adding overhead to each Fiber frame and reducing the throughput, the Copy Master Mode SHOULD be designed as an optional mode of operation, selectable by either a jumper or control register.
Observation 6.1.4.5:
In addition to the direct implementation of the copy mode on a Serial FPDP interface, copying or broadcasting the data from a Serial FPDP transmitter can be accomplished using a transparent switch that supports the Serial FPDP link baud rates.
6.1.5 Copy/Loop Mode (Optional)
Serial FPDP supports Copy/Loop mode as an option. Copy/loop mode is implemented using the copy mode with a return cable from the last receiver back to the transmitter. Receivers in the copy/loop mode must also have the ability to set the flow control signal in the event that a receive FIFO overflow condition occurs. This allows any of the receive nodes to back off the transmitter. Figure 6-5 shows the Serial FPDP Copy/Loop Mode.
All discussion, references, rules, recommendations, etc. provided in the Serial FPDP Copy Mode section (Section 6.1.4) apply to the Copy/Loop mode.
Data/Flow Control
Data/ Data/ Data Flow Flow Control Control
RX TX RX RX RX
Figure 6-5 Serial FPDP Copy/Loop Mode
Rule 6.1.5.1:
The maximum number of receiver nodes in a copy/loop mode chain the SHALL be limited to five (5), or six (6) total nodes including the transmitter.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 21 January 30, 2002 Rule 6.1.5.2:
Each receive node in the copy/loop mode SHALL set the flow control signal based on its own receive FIFO status using an “OR” type function. This allows any of the receive nodes to set this signal for return to the transmit node.
Rule 6.1.5.3:
The transmit node SHALL NOT have its copy mode or copy/loop mode active.
Rule 6.1.5.4:
In the copy/loop mode, the maximum amount of time between receipt of data by a Serial FPDP receiver and the re-transmission of the data on the next segment of the link is 32 32-bit clock cycles.
Observation 6.1.5.1:
Using the flow control in the copy/loop mode requires a designer to consider the following elements when planning the amount of reserve space to allocate in a receive FIFO to compensate for the delay between when the overflow suspend signal (STOP) is set and when the data is actually stopped at the receiver.
· The total length of cable in the entire loop. · Delays attributed to the process of re-transmitting the data and control signals at each receive node. · The delay between the receipt of the flow control signal by the transmit node and the actual disabling of the transmitter.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 22 January 30, 2002 Chapter 7 - Link Specifications
7.1 Overview
The theory behind Serial FPDP (on the transmit side) is that the Host-Bus, such as Parallel FPDP, supplies data to a Transmit FIFO and the Serial FPDP logic removes this data from this FIFO, encodes it, serializes it, and transmits it across the link using the framing protocol defined by this specification. The receive side performs in a similar, but reverse manner. Figure 7-1 show a typical Serial FPDP process approach, with the double dashed lines indicating the separation between the Host-Bus side and the Serial FPDP side. The single dashed lines indicate the flow for the optional copy and copy/loop modes.
Transmit Fiber Out Encoder Serializer Serial Host FIFO Transmitter Bus Optional Copy or
Loop/Copy Mode – Optional Copy Mode – Parallel Method 2 (Transmit FIFO Method 1 (Transmit FIFO
FPDP Disabled) Disabled)
PCI
ETC. Receive Decoder De- Serial
FIFO serializer Receiver Fiber In
Figure 7-1 Typical Serial FPDP Process
Throughout this specification, there will be many references to the existing Parallel FPDP. These references are necessary to explain both the signals generated by the Host-Bus and the Frame structure used by Serial FPDP. These continuous references to Parallel FPDP are not meant to limit the use of FPDP to Parallel FPDP Host-Bus only. For example, products meeting this specification are available with a PCI as the Host-Bus.
7.2 Link Bandwidth
This standard defines and supports two different link speeds (or link bandwidths): (1) 1.0625 Gbaud – which corresponds to one of the link speeds currently defined by Fibre Channel, and (2) 2.5 Gbaud – which corresponds to link speed that represents a double Gigibit Ethernet speed (2 x 1.25 Gbaud).
Rule 7.2.1:
A Serial FPDP interface SHALL be capable of operating at either 1.0625 Gbaud or 2.5 Gbaud across the link.
Permission 7.2.1:
Although not required, a single Serial FPDP interface MAY be capable of operating at both 1.0625 and 2.5 Gbaud.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 23 January 30, 2002 Observation 7.2.1:
An interface operating at 1.0625 Gbaud and an interface operating at 2.5 Gbaud are not intended to inter-operate across the same link. In cases where an interface is capable of operating at both rates, a methodology such as a jumper or control bit can be used to configure the interface for operation at the desired rate.
Rule 7.2.2:
The clock speed at the Host-Bus interface side (input to a FPDP Transmitter and output from a FPDP Receiver) SHALL be designed to operate independently of the Serial FPDP clock speed.
Suggestion 7.2.1:
Designers should carefully consider the speed differential (including burst speed) between the Host-Bus and the Serial FPDP link in determining the appropriate Transmit FIFO size. For example, a Host-Bus speed (including possible data burst) that is guaranteed to always operate slower than the effective Serial FPDP link speed will require only a small transmit FIFO. Host- Bus interfaces that allow for high data burst rates will require a larger transmit FIFO in order to avoid possible data losses (disregarding any flow control mechanism that may be in place).
7.3 Serial FPDP Transmission Frames
Parallel FPDP defines four different types data frames: Unframed Data, Single Frame Data, Fixed Size Repeating Data, and Dynamic Size Repeating Frame Data. The characteristics of these Parallel FPDP Frames are generally described in chapter 5 of this document and are described in detail in the Front Panel Data Port Specifications (ANSI/VITA 17-1998) Standard.
Serial FPDP supports all four of these Parallel FPDP frames, using a serialized frame structure defined by this standard. The data frame concept is important in many applications to delineate “real life” frame separation, such as a video frame, a radar signal frame, etc. Serial FPDP also uses a serial frame structure in order to send information and maintain synchronization across the link. In order to avoid confusion, this document will refer to a Parallel FPDP frame as a “Parallel FPDP Data Frame” or just “Data Frame” – and will refer to a Serial FPDP Frame as a “Serial FPDP Fiber Frame” or just “Fiber Frame.” For clarification, although “Fiber Frame” references the most common media used for Serial FPDP, Fiber Optic media is not the only media option allowed by this standard.
7.3.1 8B/10B Encoding / Decoding
The Serial FPDP uses a transmission protocol based on the standard 8B/10B encoding method invented and patented by IBM Corp. Designers may implement this 8B/10B process by using commercially available components that perform this function, or they may choose to implement the logic directly in some type of programmable device. As long as the IBM patent remains in effect, any direct implementation of the 8B/10B logic requires permission/agreement from IBM. This encoding/decoding scheme is used extensively in other communications protocols and IBM will license this patent on an equal and non-discriminatory basis. Fibre Channel is one of the technologies that use 8B/10B. Fibre Channel denotes a certain mapping of the transmission words in the 8B/10B protocol to be ordered sets, which denote special control information for Fibre Channel. Serial FPDP has adopted and uses a subset of the total available ordered sets used by Fibre Channel – as defined in the Fibre Channel Specification (ANSI X3.230-1994, Fibre Channel Physical and Signaling Interface (FC-PH) – to also denote control information. Serial FPDP assigns a different meaning to these ordered sets. Table 7-1 shows the ordered sets used by Serial FPDP. Also included in this table are the Fibre Channel and the Serial FPDP meaning. These ordered sets make up the Serial FPDP framing protocol.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 24 January 30, 2002
Ordere Fibre Channel Serial Serial FPDP Meaning Value d Set Meaning FPDP Name IDLE Idle IDLE Idle N-K28.5 D21.4 D21.5 D21.5 R_RDY Receiver_Ready SWDV Start of SYNC Frame, SYNC N-K28.5 D21.4 D10.2 D10.2 with DVALID SOFc1 SOF Connect Class 1 SOF Start of Frame N-K28.5 D21.5 D23.0 D23.0 PIO1, PIO2, DIR = “000” SOFi1 SOF Initiate Class1 SOF Start of Frame N-K28.5 D21.5 D23.2 D23.2 PIO1, PIO2, DIR = “001” SOFn1 SOF Normal Class 1 SOF Start of Frame N-K28.5 D21.5 D23.1 D23.1 PIO1, PIO2, DIR = “010” SOFi2 SOF Initiate Class 2 SOF Start of Frame N-K28.5 D21.5 D21.2 D21.2 PIO1, PIO2, DIR = “011” SOFn2 SOF Normal Class 2 SOF Start of Frame N-K28.5 D21.5 D21.1 D21.1 PIO1, PIO2, DIR = “100” SOFi3 SOF Initiate Class 3 SOF Start of Frame N-K28.5 D21.5 D22.2 D22.2 PIO1, PIO2, DIR = “101” SOFn3 SOF Normal Class 3 SOF Start of Frame N-K28.5 D21.5 D22.1 D22.1 PIO1, PIO2, DIR = “110” SOFf SOF Fabric SOF Start of Frame N-K28.5 D21.5 D24.2 D24.2 PIO1, PIO2, DIR = “111” Data Data Data Data Dnn.n Dnn.n Dnn.n Dnn.n EOFdti EOF Disconnect- FEOF Frame End of Frame N-K28.5 D10.4 D21.4 D21.4 Terminate-Invalid End of a normal data frame P-K28.5 D10.5 D21.4 D21.4 EOFni EOF Normal-Invalid MEOF Mark End of Frame N-K28.5 D10.4 D21.6 D21.6 End of SYNC frame P-K28.5 D10.5 D21.6 D21.6 EOFt EOF terminate SEOF Status End of Frame N-K28.5 D21.4 D21.3 D21.3 TX FIFO Overflow, NRDY = “00” P-K28.5 D21.5 D21.3 D21.3 EOFdt EOF Disconnect- SEOF Status End of Frame N-K28.5 D21.4 D21.4 D21.4 Terminate TX FIFO Overflow, NRDY = “01” P-K28.5 D21.5 D21.4 D21.4 EOFa EOF abort SEOF Status End of Frame N-K28.5 D21.4 D21.7 D21.7 TX FIFO Overflow, NRDY = “10” P-K28.5 D21.5 D21.7 D21.7 EOFn EOF Normal SEOF Status End of Frame N-K28.5 D21.4 D21.6 D21.6 TX FIFO Overflow, NRDY = “11” P-K28.5 D21.5 D21.6 D21.6 CLS Close Port GO Suspend = 0 (Flow Control) N-K28.5 D05.4 D21.5 D21.5 NOS Not Operational STOP Suspend = 1 (Flow Control) N-K28.5 D21.2 D31.5 D05.2
Table 7-1 Fibre Channel to Serial FPDP Ordered Sets
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 25 January 30, 2002 7.3.2 Serial FPDP Control Signals
Serial FPDP uses a minimal set of status and control signals and encodes them for transmission across the serial link using the ordered sets defined in Table 7-1. There are six status and control signals transmitted across the Serial FPDP Link. These are DIR, PIO1, PIO2, NRDY, TX FIFO Overflow and STOP/GO. The origin of these signals is as follows:
(1) The embedded Serial FPDP signals DIR, PIO1, PIO2, and NRDY are derived from the Parallel FPDP signals /DIR, PIO1, PIO2, and /NRDY in an interface with a Parallel FPDP Host-Bus. These signals must be generated (simulated) by a non Parallel FPDP Host-Bus. Serial FPDP does not directly use these four signals, but simply transmits them from Host-Bus to Host-Bus.
(2) Serial FPDP directly generates the other two embedded signals, TX FIFO Overflow and the STOP/GO (Flow Control) signals. The TX FIFO Overflow is asserted to indicate an overflow condition in the Transmit FIFO – indicating a loss of data. The STOP/GO signal is used for Flow Control.
Of the eighteen ordered sets used by Serial FPDP, the eight “Start-of-Frame (SOF)” ordered sets are used to embed the three signals – PIO1, PIO2, and DIR. The four “Status End-of-Frame (SEOF)” ordered sets are used to embed the Serial FPDP signals NRDY and TX FIFO Overflow. The ordered sets GO and STOP are the ordered sets used for Serial FPDP flow control.
Rule 7.3.2.1:
The Serial FPDP signals DIR, PIO1, PIO2, and NRDY SHALL be generated by the Host-Bus interface of the Serial FPDP Transmitter for embedding in the appropriate ordered set.
Rule 7.3.2.2:
In a Serial FPDP design with a Parallel FPDP Host-Bus, the embedded Serial FPDP signals DIR, PIO1, PIO2, and NRDY (shown in Table 7-1) SHALL correspond exactly to the Parallel FPDP signals /DIR, PIO1, PIO2 and /NRDY (shown in Table 5-1).
Recommendation 7.3.2.1:
For compatibility with Serial FPDP designs with a Parallel FPDP Host-Bus, designers of non Parallel FPDP Host-Bus interfaces SHOULD simulate or replicate DIR, PIO1, PIO2, and NRDY.
Observation 7.3.2.1:
All five signals (PIO1, PIO2, DIR, NRDY, TX FIFO Overflow) embedded in the SOF and SEOF ordered sets and the GO/STOP ordered sets are transmitted as part of a Fiber Frame rather than within the actual data. Therefore, these signals are asynchronous with regard to the data.
Rule 7.3.2.3:
The TX FIFO Overflow signal SHALL be generated by the Serial FPDP Transmitter to communicate that an overflow condition has occurred within the transmit FIFO – causing a potential loss of data.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 26 January 30, 2002 7.3.3 Fiber Frames
There are three Fiber Frame types defined by Serial FPDP – Normal Data Fiber Frame, SYNC without Data Fiber Frame, and SYNC with Data Fiber Frame. These three Fiber Data Frames support all four types of Parallel FPDP Data frames. These Fiber Frames also guarantee that the receiver periodically receives the IDLE ordered set necessary to maintain synchronization. Figure 7-2 shows the three types of Fiber Frames.
In addition to the four Status End-of-Frame (SEOF) ordered sets discussed in section 7.3.2, there are two additional End-Of-Frame (EOF) ordered sets used by Serial FPDP. These two ordered sets are used to distinguish between a frame that only contains data and a frame that contains a SYNC. The Frame End-of-Frame (FEOF) denotes the end of a Normal Data Fiber Frame and the Mark End-of-Frame (MEOF) denotes a Fiber Frame that has SYNC associated with it.
Rule 7.3.3.1:
All Serial FPDP Frames SHALL consist of: (1) at least one IDLE or Sync with Data Valid (SWDV) ordered set; (2) a Start of Frame (SOF) ordered set; (3) a Frame End-of-Frame (FEOF) or Mark End-of-Frame (MEOF) ordered set; (4) a Status End-of-Frame (SEOF) ordered set; and (5) a GO/STOP ordered set. CRC is an optional data word (not a control character or ordered set) that is generated if the CRC function is active.
Rule 7.3.3.2:
Serial FPDP Receiver interfaces SHALL be designed to receive all three Serial FPDP Fiber Frame types – Normal Data Fiber Frame, Sync without Data Fiber Frame, and Sync with Data Fiber Frame.
Rule 7.3.3.3:
Serial FPDP Transmit interfaces SHALL be designed to transmit Serial FPDP Normal Data Fiber Frames.
Permission 7.3.3.1:
Serial FPDP Transmitter designs are not required to support all Serial FPDP Frame types, therefore, in addition to Normal Data Fiber Frames; Serial FPDP Transmitters MAY be designed to transmit either Sync without Data Fiber Frames or Sync with Data Fiber Frames or both.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 27 January 30, 2002 Rule 7.3.3.4:
All Serial FPDP Normal Data Fiber Frames and Sync without Data Fiber Frames SHALL be preceded by one or more IDLE ordered sets.
NORMAL DATA FIBER FRAME (/SYNC Not Asserted, /DVALID Asserted) CRC GO/ 0 to 512 DATA WORDS (32 bit or 4 Byte words) IDLE SOF (Optional) FEOF SEOF STOP (Maximum 2048 Bytes)
SYNC WITHOUT DATA FIBER FRAME (/SYNC Asserted, /DVALID Not Asserted)
CRC GO/ IDLE SOF NO DATA MEOF SEOF (Optional) STOP
SYNC WITH DATA FIBER FRAME (/SYNC Asserted, /DVALID Asserted)
CRC SWDV SOF 1 DATA WORD (4 Bytes) associated with SYNC (Optional) MEOF SEOF GO/ (No more – No less) STOP
FEOF: DATA Frame. MEOF: SYNC Frame PIO1,PIO2,DIR SOFc1 0, 0, 0 FIFO OV, NRDY SOFil 0, 0, 1 EOFt 0,0 SOFn1 0, 1, 0 EOFdt 0,1 SOFi2 0, 1, 1 EOFa 1,0 SOFn2 1, 0, 0 EOFn 1,1 SOFi3 1, 0, 1 SOFn3 1, 1, 0 SOFf 1, 1, 1 STOP: Suspend. GO: OK to transmit
IDLE: An ordered set used to pad a DATA or SYNC without DATA Frame. (At least one is required) SWDV: An ordered set used to pad a SYNC with DATA Frame. (At least one is required)
Figure 7-2 Serial FPDP Fiber Frames
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 28 January 30, 2002
Rule 7.3.3.5:
Serial FPDP Sync with Data Fiber Frames SHALL be preceded by one or more Sync with Data Valid (SWDV) ordered sets.
Rule 7.3.3.6:
The maximum amount of data that can be sent in a single Serial FPDP Normal Data Fiber Frame is 512 32-bit words (2048 bytes).
The calculation of CRC is optional in a Serial FPDP design. Although operating with CRC is preferred, this standard supports three different implementations of this feature: (1) designs that support only CRC (CRC mode only); (2) designs that do not support CRC (No-CRC mode only); and (3) designs that support both CRC and No-CRC. Designers are encouraged to consider interoperability issues when implementing this optional feature.
Permission 7.3.3.2:
A Serial FPDP interface MAY support CRC only, No-CRC only, or both CRC and No-CRC.
Observation 7.3.3.1:
The No-CRC mode effectively reduces the overhead in the Fiber Frame structure (header/footer) by one 32 it word (from 6 words to 5 words), effectively increasing the efficiency of the protocol slightly.
Rule 7.3.3.7:
A Serial FPDP interface which only supports CRC SHALL only interoperate with other Serial FPDP interfaces which support CRC (either CRC only or both CRC and No-CRC designs)
Rule 7.3.3.8:
A Serial FPDP interface which only supports No-CRC SHALL only interoperate with other Serial FPDP interfaces which support No-CRC (either No-CRC only or both CRC and No-CRC designs)
Rule 7.3.3.9:
If both the CRC and No-CRC feature is supported in a single interface design, selection of the mode (CRC or No-CRC) SHALL be via jumper or control bit.
Rule 7.3.3.10:
CRC SHALL be calculated on the actual data stream only, and SHALL NOT include any of the Fiber Frame header words (ordered sets).
Observation 7.3.3.2:
The CRC does not provide any error check on any of the control words used to convey control information, such as the SOF; therefore it does not validate the control words. This means that errors in PIO1, PIO2, DIR, FIFO OV, and NRDY are not detected by the CRC.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 29 January 30, 2002 Recommendation 7.3.3.1:
CRC is sent across the link as a data word and is indistinguishable from the actual data itself. The Serial FPDP Receiver SHOULD check whether the CRC function is enabled in order to determine if the last word received is the CRC or an actual data word.
/SYNC and /DVALID are Parallel FPDP signals used to define Parallel FPDP Data Frames. They are used directly by a serial FPDP design with a Parallel FPDP Host-Bus to determine which type of Fiber Frame to generate for transmission across the link. This direct association is shown in Figure 7-2 in the parentheses following the Fiber Frame title.
The method used to map between the four Parallel FPDP Frames and the three Serial FPDP Frames is as follows.
· The Parallel FPDP “Unframed Data” frame type requires no frame formatting and does not use /SYNC. This is mapped into Serial FPDP as one or more Serial FPDP “Normal Data Fiber Frames.”
· The Parallel FPDP Single Frame Data frame type requires that a /SYNC be asserted prior to the data being sent. This is mapped into Serial FPDP as a Serial FPDP Sync without Data Fiber Frame, followed by one or more Serial FPDP Normal Data Frames. The next and following frames of data are handled in the same manner – a Serial FPDP Sync without Data Fiber Frame followed by one or more Serial FPDP Normal Data Frames.
· The Parallel FPDP Fixed Size Repeating Frame Data and Dynamic Size Repeating Frame Data are mapped into Serial FPDP Frames in an identical manner. The size or amount of data is in the frame does not matter to Serial FPDP. Both of these Parallel FPDP Frames require that the /SYNC be asserted coincident with the last word of the data frame. This is mapped into Serial FPDP as one or more Serial FPDP “Normal Data Frames” followed by a Serial FPDP “Sync with Data Fiber Frame” (containing the last data word) followed by one or more Serial FPDP “Normal Data Frames” followed by a Serial FPDP “Sync with Data Fiber Frame” etc. As is true with Parallel FPDP, the first “Data Frame” is sent prior to the Synchronization signal, and therefore the integrity of the data is questionable.
Observation 7.3.3.3:
Two possible implementations for a Serial FPDP Receiver to identify SYNC without DVALID and SYNC with DVALID frames are:
SWDV Method
· When a MEOF is received and the Serial FPDP Fiber Frame being terminated is not preceded by an SWDV, then the Serial FPDP Fiber Frame is a “SYNC without Data Fiber Frame.”
· When an MEOF is received and the Serial FPDP Fiber Frame being terminated is preceded by an SWDV, then the Serial FPDP Fiber Frame is a “SYNC with Data Fiber Frame.”
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 30 January 30, 2002 Ignore SWDV Method
· When an MEOF is received and the Serial FPDP Fiber Frame being terminated has no data, the Fiber Frame is a Serial FPDP “SYNC without Data Fiber Frame.”
· When an MEOF is received and the Serial FPDP Fiber Frame being terminated has data, then the Fiber Frame is a Serial FPDP “SYNC with Data Fiber Frame.” The Serial FPDP Receiver does not need to make sure that there is only one single 32-bit word. It simply looks for a fiber frame with some amount of data ended by an MEOF.
Rule 7.3.3.11:
Although there are multiple methods to detect the Serial FPDP Fiber Frames, the frames SHALL always look like those given in Figure 7-2. The SWDV SHALL always immediately precede the SOF of a “SYNC with Data Fiber Frame.” Additionally, the “SYNC with Data Fiber Frame” SHALL always have exactly one (1) 32-bit data word.
Serial FPDP is designed to be an active link, regardless of the presence of data. Since the status and control bits (part of the Fiber Frame header) may be required to be updated regardless of the availability of actual data the steady state condition for a transmitter should be to send empty Serial FPDP Normal Data Fiber Frames.
In addition, due to the speed of the Serial FPDP Link (especially the 2.5 Gbaud link), there may be occasions when, even during a data transmission sequence (i.e. a Parallel FPDP Data Frame), the transmitter may not see data available for transmission. In this condition, the transmitter should send either IDLE ordered sets or empty Serial FPDP Normal Data Fiber Frames. It should be noted that when the Serial FPDP device detects that no more data is available (even though it occurs in the middle of a data transmission sequence), it must complete the Fiber Frame (CRC if required, FEOF, SEOF, etc.) and start a new Fiber Frame when data is available.
Rule 7.3.3.12:
If no data is available at the Serial FPDP Transmitter, the Transmitter SHALL send either empty Serial FPDP Normal Data Fiber Frames or IDLE ordered sets.
Recommendation 7.3.3.2:
Since the status and control signals are sent as part of the Serial FPDP Frame, the Serial FPDP device SHOULD send Normal Data Fiber Frames when no data is available at the Serial FPDP Transmitter.
Permission 7.3.3.3:
Designers MAY choose to send IDLE ordered sets between Serial FPDP Fiber Frames, especially in the cases where the “no data available” condition at the Serial FPDP Transmitter occurs within a data transmission sequence (i.e. a Parallel FPDP Data Frame).
Suggestion 7.3.3.1:
If a transmitter sends IDLE ordered set rather that empty Serial FPDP Normal Data Fiber Frames when no data is available, it may want to periodically insert an empty Normal Data Fiber Frame. This will guarantee that the control bits are updated at the receive side of the link.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 31 January 30, 2002 Rule 7.3.3.13:
Only IDLE and SWDV (in the very limited situation of directly preceding a Serial FPDP Sync with Data Fiber Frame) ordered sets SHALL be used as padding between Serial FPDP Fiber Frames.
Rule 7.3.3.14:
Ordered sets, including IDLE ordered sets, SHALL NOT occur in the data payload portion of a Serial FPDP Fiber Frame to act as a pad word.
Observation 7.3.3.4:
The control bits are not checked by the CRC. An error on any of them may be detected by an 8B/10B decoding error. If this occurs, the state of that control bit should be ignored. For this reason, sending periodic empty Serial FPDP Normal Data Fiber Frames will guarantee that the control information is kept current, even if link errors should occur.
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 32 January 30, 2002 Chapter 8 - Physical Specifications
8.1 Link Interface
Serial FPDP is designed to operate over a variety of serial media. A representative sample of the available media interfaces is shown in table 8.1. This table is not meant to be all inclusive, but should be used only as a reference.
Media Type Data Rate Connector Cable Maximum Cable Length Copper 1.0625 HSSDC 150 W shielded quad 30 meters with Gbaud HSSDC-2 equalized cable 25 meters with non-equalized cable Copper 1.0625 HSSDC 150 W shielded quad 15 meters with Gbaud HSSDC-2 equalized cable Short 1.0625 Duplex SC 50/125 mm multimode 500 meters Wavelength Gbaud Duplex LC fiber Laser Duplex ST Short 1.0625 Duplex SC 62.5/125 mm multimode 300 meters Wavelength Gbaud Duplex LC fiber Laser Duplex ST Short 2.5 Gbaud Duplex SC 50/125 mm multimode 150 meters Wavelength Duplex LC fiber Laser Short 2.5 Gbaud Duplex SC 62.5/125 mm multimode 100 meters Wavelength Duplex LC fiber Laser Long 1.0625 Duplex SC 9/125 mm single mode 10 kilometers Wavelength Gbaud Duplex LC fiber Laser Long 2.5 Gbaud Duplex SC 9/125 mm single mode 10 kilometers Wavelength Duplex LC fiber Laser
Table 8-1 Media Interfaces
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 33 January 30, 2002 Appendix A - Interoperability Issues
Information Only
One of the key issues underlying this standard is to permit interoperability between products developed by different companies. Due to the variety of optional features in a Serial FPDP design, designers and operators must be aware of potential incompatibility issues. Presented here is a chart of features that should be considered when designing and operation Serial FPDP products.
Feature / Function Choice Choice Baud Rate 1.0625 Gb 2.5 Gb CRC On Off Flow Control On Off Copy Mode (Master Copy Mode) Supported / On Not Supported / Off Copy / Loop Mode Supported / On Not Supported / Off Media Type / Distance Compatible Not Compatible Data Flow Single Direction Bi-Directional
Do not specify or claim conformance to this draft standard
Serial FPDP, VITA 17.1 – 199x/Draft 0.6 34 January 30, 2002