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Ensemble® I/O Series Low-Latency, Wide-Band, Programmable I/O

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Ensemble® I/O Series Low-Latency, Wide-Band, Programmable I/O Ensemble® I/O Series Low-Latency, Wide-Band, Programmable I/O Modules IOM-300 Customizable and Secure I/O Mezzanines FPGA supported XMC I/O mezzanines with programming and in-mission update capabilities for sensor chain and storage data streaming DATASHEET • Twelve channel, front-panel access fiber I/O or eight channel copper I/O ports • Supporting sFPDP (VITA 17.1), 10Gb/s Ethernet, Fibre Channel and unrestricted PCIe Gen 3 data rates • Altera® Stratix V FPGA with second FPGA programing and personalized security capability • Fast, rugged, scalable Open Systems Approach (OSA) for massive streaming I/O applications The Ensemble® IOM-300 is a robust, versatile, fast and secure features. POET has backward compatibility with software protocols embedded streaming I/O Module which is densely packaged including Interprocessor Communication System (ICS™) and Message within an Open Systems Architecture (OSA) XMC package (VITA Passing Interface/Open Fabrics Enterprise Distribution (MPI/OFED). 42). Ensemble IOM-300 mezzanines are ideally suited for mount- I/O Intelligence ing on other Ensemble sensor chain building blocks including the The Ensemble IOM-300 is more than a traditional digital interface: each ™ OpenVPX LDS6523 and LDS6525 carriers. channel can be programmed for data distribution without processor Each Ensemble IOM-300 mezzanine is highly configurable, supporting intervention. Although the data destination is typically a PCIe targeted various switch fabrics and data stream protocols. Protocols include memory, with Mercury’s system focused approach and drivers, destina- PCIe (Gen 2 and 3), serial Front-panel Data Port (sFPDP), Fibre Channel, tions may be anywhere where fabric based connectivity exists, even and 10Gb/s with front-panel I/O in both the fiber (up to 12 onboard when mode changes are called for (e.g. at a Serial RapidIO® destination fiber transceivers) and copper domains. via a POET enabled PCIe bridge). The Ensemble IOM-300’s primary processing resource is Altera’s fast The Ensemble IOM-300 can inspect the input data stream that indicates and highly customizable Stratix V FPGA device. Mercury’s Protocol sensor mode changes and route data appropriately for each different Offload Engine Technology (POET™) resides on this FPGA resource. mode. Each mode can be made to correspond with an application- Uniquely, the Stratix device is supported by a second FPGA which has defined Direct Memory Access (DMA) Command Packet (CP) chain. its own PCIe pipe, enabling the Ensemble IOM-300 to receive mission These command packets cause the channel’s DMA controller to route and upgrade updates in real-time as well as from its onboard RAM. the data toward a predefined destination anywhere within the system’s switch fabric. This data-driven distribution takes advantage of informa- Protocol Offload Engine Technology (POET) tion available at the source. DMA command packets can be chained www.mrcy.com Mercury’s next-generation, low-latency, high-bandwidth FPGA-enabled together to automatically distribute sequential data packets to different POET enables each mezzanine to refresh/upgrade its mission param- processors or endpoints. eters in real-time and has embedded user customization and security Mercury Systems is the better alternative for affordable, secure processing 100101010 100101010 100101010 100101010 100101010 subsystems designed and made in the USA. These capabilities make us the 001101011 001101011 001101011 001101011 001101011 first commercially based defense electronics company built to meet rapidly 110101100 110101100 110101100 110101100 110101100 evolving next-generation defense challenges. ACQUIRE ACQUIREDIGITIZE ACQUIREPROCESDIGITIZES ACQUIRESTORAGEPROCESDIGITIZES ACQUIRESTORAGEPROCESDIGITIZEEXPLOITS DISSEMINAACQUIRESTORAGEPROCESDIGITIZEEXPLOITSTE WARNING: “600 Series” and/or National Security Controls - These commodities, technology, or software are controlled for export from the United States in accordance with the Export Administration Act of 1979 as amended (Title 50 U.S.C.; App. 2401, et seq.), through the Export Administration Regulations (EAR). Transfers to foreign persons requires prior approval from the U.S. Department of Commerce, Bureau of Industry and Security. Synchronization between the sensor I/O XMC and the application pro- Serial FPDP Interface gram can be accomplished by queuing a transfer request that includes Serial FPDP (sFPDP) supports a mapping of the FPDP protocol onto the status information at the desired synchronization point within the DMA Fibre Channel physical layers (FC-0 and FC-1). Serial data is transmit- chain. This block of status information is written to the local memory ted at 2.5 Gbaud over the fiber. of the synchronizing processor. The processor can then poll on the re- ceiving memory location for block of status information. The sensor I/O Data Frame Management (sFPDP) XMC can also be synchronized with a processor, via mailbox interrupts. The Ensemble IOM-300 may be configured to enable the sensor to frame the data into “epochs.” Any sensor can define its own epoch Real-Time Reconfiguration for Mode Changes boundary based on what is most compatible with that type of sensor Mercury’s FPGA technology adds the versatility of rapid reconfigura- and how the data will be used by the processing system. In the case of tion. High-speed reconfiguration facilitates dynamic, system-level radar data, these epochs are likely to be coherent processing inter- changes in mission and operating mode. vals. In the case of images, an epoch is likely to be a line or a frame Parts of the application that are simple, fixed-point computations can of an image. The Ensemble IOM-300 supports the four sFPDP framing run on an FPGA, saving space, power and money. Other parts of the options: Unframed, Single-Frame Data, Dynamic-Size Repeating Frame application can run on the host processor, which is easier to program. Data and Fixed-Size Repeating Frame Data. Accordingly, the overall development time is kept manageable while Data-Driven Frame Processing (sFPDP) the performance is maximized. Many modern sensors change modes during operation. When a sensor The host processor allows better integration, communication and changes modes, the processing system must make the corresponding control with the on-board FCNs through the PCIe interface without mode change at the correct time. The sensor can also use the first interfering with the other GTP and LVDS interfaces. For example, DMA word of each epoch to indicate its current mode. The Ensemble IOM- operations can be managed from the host processor without requir- 300 in “cable header” mode may use this word to index a particular ing additional processor boards in the system. In addition, the host DMA command packet chain, and then initiate the chain without processor can be used to manage the loading of the bit streams and processor intervention. This allows each configuration of the sensor to diagnostics of the FCNs. have a dedicated DMA chain and a completely different data distribu- Ethernet Interface tion from other modes. The Ensemble IO300 may be configured with full 10Gb/s Ethernet When the sensor mode changes are known in advance, the Ensemble I/O. Coupled with an Altera Stratix V FPGA, the Ensemble IOM-300 IOM-300 can be programmed to switch DMA chains for the next mode is well suited to act as an external connection for a signal process- through the use of branching at the end of a SFPDP frame or epoch. ing subsystem. It addresses real-time I/O requests and digital signal This branching capability can also be used for handling errors when processing such as a math co-processor for fixed-point operations used the end of the SFPDP frame occurs before it is expected. in digital image processing. In addition to 10Gb/s Ethernet, the Stratix Recovering From Input Stream Faults (sFPDP) V’s flexible gigabit transceiver blocks allow other high-speed interface protocols to be implemented. With some input interfaces, missing or extra data can cause the interface to lose sync with an input data stream until a processor x1 PCIe 2.1 64 MB intervenes. The Ensemble IOM-300 minimizes the system upset by NOR FC FRU Configuration EEPROM localizing the effects of anomalies in the input stream. To do this, the FPGA 256 MB P15 NOR XMC can re-synchronize its DMA controller to the incoming data at FPP x8 each data frame (epoch boundary). This re-synchronization is done by 2 GB 64 BITS x8 PCIe 3.0 the hardware, with no processor intervention. DDR3-1600 8 In the event that an end-of-epoch marker is lost, due to a media error, www.mrcy.com 1 GB 32 BITS Stratix V GX DDR3-1600 the maximum word count in the DMA CP will prevent data from being X8d+X12d 2 GB 64 BITS 8 written past the end of the buffer. DDR3-1600 8x 10Gb Tx + 8x 10Gb Rx 12 Rx 12 Tx P16 10 GbE x12 10 GbE x12 Sensor I/O XMC Full-Duplex Operation Each interface can operate in full-duplex mode. In addition, there are 12x Rx 12x Tx PRWF TransceiversModule Status LEDs separate DMA controllers for transmit and receive on each channel — Module Front Panel 2 DMA controllers per channel (24 per card). On each channel, transmit Figure 1 - Ensemble IOM-300 Functional Block Diagram and receive can be synchronized. WARNING: “600 Series” and/or National Security Controls - These commodities, technology, or software are controlled for export from the United States in accordance with the Export Administration Act of 1979 as amended (Title 50 U.S.C.; App. 2401, et seq.), through the Export Administration Regulations (EAR). Transfers to foreign persons requires prior approval from the U.S. Department of Commerce, Bureau of Industry and Security. Subsystem Scalability VPX-REDI FPGAs within the PCIe environment become part of a scalable system The VPX (VITA 46) standard defines 6U and 3U board formats with high that can expand to provide as many FPGAs and microprocessors as performance interconnects capable of supporting today’s high speed fab- changing applications demand with minimal application recoding and ric interfaces.
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