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PAT48PG4SRQPONMLKJIHGFEDCBA

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NOTES Contents

Chapter 1 Specifications 1-1

Chapter 2 Hardware Description 2-1 2.1 PAT48PG Motherboard ...... 2-4 2.2 486 Microproccsssor...... 2-4 2.3 Cache Controller and Cache Memory 2-5 2.4 I/O Port Address Map...... 2-6 2.5 Memory Map...... 2-8 2.6 BIOS...... 2-9 2.7 System Timer ...... 2-9 2.8 DMA Channels...... 2- 10 2.9 Interrupt Controllers...... 2- Il 2.10 Real Time Clock and CMOS RAM 2- 12

Chapter 3 Configuring the PAT48PG 3-1 3.1 CPU Related Jumpers...... 3-2 3.1.1 Installing and/or Upgrading the CPU 3-3 3.1.2 Setting CPU Related Jumpers . . 3-4 3.2 Installation Main Memory ...... 3-7 3.3 Cache Memory Installation...... 3-10 3.4 Miscellenous Jumpers...... 3-11KJIHGFEDCBA

Chapter 4 Installation 4-1 4.1 Keyboard Connector: JI . . . 4-2 4.2 External Battery Connector: J3 4-3 4.3 Power Supply Connector: J4 . 4-4 4.4 Power Savings Switch and LED Connector: J5 and J8 . . . .4-5 4.5 Speaker Connector: J7(Pins 1-4) ...... 4-6 4.6 Power LED and Keylock Connector: J7(Pins 11 - 15) . . . .4-7 4.7 Turbo Switch Connector: J7(Pins 7&17) ...... 4-8 4.8 Turbo LED Connector: J7(Pins 8 & 18)...... 4-9 4.9 Reset Switch Connector: J7(Pins 9 & 19)...... 4-10 4.10 HDD LED Connector: J7(Pins 10 & 20), J6...... 4-11

Pageii PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User's Manual HiSRQPONMLKJIHGFEDCBA ContentsSRQPONMLKJIHGFEDCBA Chapter 1 Specifications

NOTES Chapter 1 Specifications

Architecture ISA (Industry Standard Architecture) with VL-Bus implementation VL-Bus compliant

M ain Processor 486SX, 486DX, 486DX2 or 486DX4

Processor Upgrades A ZIF socket for a Pentium OverDrive processor

Cache Memory 8KB of on-chip cache memory 128KB or 256KB of write-back secondary cache memory

M ain Memory Up to 128MB of on board main memory Four 30-pin & Two 72-pin SIMMfSingle In-Line Memory Module) sockets for (256K; 512K, IM, 2M,4M, 8M, 16M, 32M) x 36 or (256K, IM, 4M, 16M)x 9 modules

BIOS Licensed BIOS

Clock/Calendar Battery Backed Real Time Clock(146818 compatible) and 128 bytes of CMOS RAM On board rechargeable battery

DMA Channels Seven DMA channels(8237 compatible)

iv PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 1-1YXWVUTSRQPONMLKJIHGFEDCBA Chapter 1 Specifications Chapter 2 Hardware DescriptionSRQPONMLKJIHGFEDCBA

Interrupts Chapter 2 Hardware Description Sixteen levels of hardware interrupts(dual 8259 compatible) This chapter briefly describes each of the major features of

System Timer the PAT48PG system board. The function block of the board is shown in Figure 1. The layout of the board is shown in Three channels of programmable system timer (8254 compatible) Figure 2 to show the locations of key components. The topics covered in this chapter are as follows: Expansion Slots Seven ISA slots Three VL-Bus slots(two master and one slave) □ 2.1 PAT48PG System Board Connectors □ 2.2 486 M icroprocessor Connectors for: power supply, keyboard, reset switch, □ 2.3 Cache Controller and Cache Memory Power LED, keylock, speaker, turbo switch, turbo LED, external battery and hard disk access LED □ 2.4 I/O Port Address Map □ 2.5 Memory Map Physical Dim ensionsYXWVUTSRQPONMLKJIHGFEDCBA □ 2.6 BIOS 4/5 Baby AT form factor □ 2.7 System Timer

Power Requirement □ 2.8 DMA Channels

+ 5V @ 2 AMPs (Normal Operation) □ 2.9 Interrupt Controllers

+ 5V @ 1 AMP (Power Saving Mode) □ 2.10 Real Time Clock and CMOS RAM

1-2 PAT48PG "Green" 486 VLB Motherboard User's Manual PAT-18 PG "Green" 486 VLB Motherboard User's Manual 2-1 Chapter 2 Hardware Description Chapter 2 Hardware DescriptionYXWVUTSRQPONMLKJIHGFEDCBA

]VL-BUS

AT BUSNMLKJIHGFEDCBA

KBD t OPTi m on CTRL CPU jptrg 82C895

JP3 ■ OPTi 82CG02 pill f>Of> BIOS nil 11 E3 128KB/ W8 yji 256KB 1 - 4 Banks 30 12 Secondary of DRAM awu■ ou caii SRQPONMLKJIHGFEDCBA cache 2MB-128MB 0 OPTi Configurations 78 82C602 JP5 M2 Ml

OPTi | CLOCK 82C895 Figure 1: Function block of the PAT48PG Generator

£ £ KJIHGFEDCBA§ § § *■ CPU JP6, JP7 832 s tXlJLlJUj § § I § uujuqIQ EESES33

Figure 2: Layout and connector locations of the PAT48PG

PAT48PG "Green" 486 VLB Motherboard User's Manual 2-2 PAT48PG "Green" 486 VLB Motherboard User's Manual 2-3 Chapter 2 Hardware Description Chapter 2 Hardware DescriptionKJIHGFEDCBA

2.1 PAT48PG Motherboard 2.3 Cache Controller and Cache Memory

The PAT48PG is designed by implementing a 486 processor The on-chip cache, 8KB in size, is a unified code and data and a highly integrated chipset, the 82C895/602. cache. The cache is used for both instruction and data ac­ R cesses and acts on physical addresses. The 82C895 integrates a write-back cache controller, local

DRAM controller, AT Bus and CPU interface logic. The This cache is organized as 4-way set associative with a line 82C895 also incorporates the DMA controller, System Con­ size of 16 bytes. The on-chip cache memory is logically troller and System Timer. A 146818 RTC is implemented and organized as 128 sets, each containing four lines. provides the Clock/Calendar functions. The 82C602 pro­ vides buffer control logic. For the Pentium OverDrive processor, the cache line size is 32 bytes.

For the secondary cache, the system controller, 82C895, 2.2 486 Microprocesssor supports 486 burst cycles. The PAT48PG can be configured with 128KB or 256KB of write-back secondary cache mem­ The (CPU) of the PAT48PG moth­ ory, greatly enhancing system performance in the event of erboard is a 486 . There are various models in on-chip cache miss cycles. the 486 family: 486SX, 486DX, 486DX2 and 486DX4.

The system controller also provides page mode operations The 486SX is the basic model in the 486 family. The 486DX, for main memory. The main memory also supports burst in additions to the features of the 486SX, provides on-chip mode operations of the 486, further enhancing system per­ 80387 compatible math coprocessor. The 486DX2 has a core formance. frequency two times the bus frequency and provides twice the performance. The 486DX4 has the core frequency that is either two or three times the bus frequency and operates at 3.3V.

The socket on board also supports the OverDrive processor. The OverDrive is an upgrade processor for 486 family. It has Pentium equivalent core with 486 compatible pin-outs. It provides capability of a user to upgrade from a 486 to Pentium performance with a simple processor change.

2-4 PAT48PG "Green" 486 VLB Motherhoard User's Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 2-5YXWVUTSRQPONMLKJIHGFEDCBA Chapter 2 Hardware Description Chapter 2 Hardware DescriptionKJIHGFEDCBA

2.4 I/O Port Address Map Table 3: I/O port addresses of devices on the I/O slotsSRQPONMLKJIHGFEDCBA

The CPU of the PAT48PG communicates via I/O ports. There AddressYXWVUTSRQPONMLKJIHGFEDCBADescription are a total of IK port address space defined. The following IFOh- lF8h Floppy Disk Controller tables list the I/O port addresses used in the PAT48PG and those assigned to other devices that can be used by I/O 200h - 2O7h Game Port expansion cards. 278h - 27Fh Parallel Port #2(LPT2)

2F8h - 2FFh Serial Port #2(COM1)

3OOh-31Fh Prototype Card

Table 2: I/O port addresses of the devices on the PAT48PG 360h - 36Fh Reserved

378h - 3FFh Parallel Port #1 (LPT 1) Address Device Description 380h - 38Fh SDLC #2 OOOh-OlFh DMA Controller # 1 3A0h - 3AFh SDLC #1 020h - 03Fh Interrupt Controller #1 3B0h-3BFh MDA Video Card (including LPTO) 040h - 05Fh Timer 3C0h-3CFh Reserved 060h - 06Fh Keyboard Controller 3D0h - 3DFh CGA Video Card 070h - 07Fh Real Time Clock, NMI 3F0h - 3F7h Hard Disk Controller 080h - 09Fh DMA Page Register 3F8h - 3FFh Serial Port #1 (C0M1) OAhO - OBFh Interrupt Controller #2

OCOh - ODFh DMA Controller #2

OFOh Clear Math Coprocessor Busy Signal

OFlh Reset Math Coprocessor

2-6 PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 2-y Chapter 2 Hardware Description Chapter 2 Hardware DescriptionNMLKJIHGFEDCBA

2.5 Memory Map 2.6 BIOSSRQPONMLKJIHGFEDCBA

The PAT48PG has a maximum memory capacity of 128M B, The PAT48PG contains a 27C512 EPROM that contains the The first megabyte is divided into four blocks with each block system BIOS. The BIOS resides at the upper 64KB of address dedicated to a fixed function. The following table illustrates 2KJIHGFEDCBAspace in the first m egabyte. the memory map for the PAT48PG.

In protected mode, the BIOS is also mapped to the upper 64KB of the 128MB space and can be accessed at either

location. Table 4: Memory map of the PAT48PGYXWVUTSRQPONMLKJIHGFEDCBA

Memory Address Description 0KB OOOOOOh - 09FFFFh Conventional RAM 2.7 System Timer 640KB OAOOOOh - OBFFFFh 128KB of Video RAM

768KB OCOOOOh - OEFFFFh 192KB of I/O Expansion The PAT48PG has three channels of tim er/counter in the ______ROM______82C802G chip, which is 8254 com patible. The function

960KB OFOOOOh - OFFFFFh 64KB of System BIOS of each channel is listed as follows: ROM

1MB lOOOOOh - 7FEFFFFh 127MB of User RAM

128MB 7FFOOOOh - 7FFFFFFh Duplicated 64KB of Table 5: System timer of the PAT48PG System BIOS ROM at OFOOOOh Channel Function

0 System Timer - This timer generates the time base for the system timer. Its output is tied to IRQO.

1 Memory Refresh Request - This timer is used to generate memory refresh requests. It triggers the memory refresh cycle.

2 Tone Generator for Speaker - This timer provides the speaker tone. Various sounds can be generated by programming the timer.

PAT48PG "Green" 486 VLB Motherboard User's Manual 2-8 PAT48PG "Green" 486 VLB Motherboard User's Manual 2-9 Chapter 2 Hardware Description Chapter 2 Hardware DescriptionKJIHGFEDCBA

2.8 DMA Channels 2.9 Interrupt ControllersSRQPONMLKJIHGFEDCBA

The PAT48PG contains the equivalent of two 8237A DMA The PAT48PG contains two Intel 8259A compatible inter­ controllers in the 82C895. rupt controllers in the 82C895. Sixteen channels are parti­ tioned into the cascaded controllers (INTC1,1NTC2) with 8 The 82C895 provides the user with two DMA controllers, inputs each. Of these 16 channels, three are connected inter­ four channels of DMA(DA£4 #1) for 8-bit transfers, and three nally to various devices, allowing 13 user definable channels channels of DMAfDAM #2) for 16 bit transfers.(The first of interrupt. Any or all of these interrupts can be masked. 16-bit DMA channel is used for cascading.)

Level Fu nction Channel FunctionYXWVUTSRQPONMLKJIHGFEDCBA NMI RAM Parity Check Controller #1 Controller #2 IRQO System Timer Output IRQ1 Keyboard 0 DRQO, Reserved IRQ2 Interrupt Cascade

1 DRQ1, SDLC IRQ8 Real Time Clock 2 DRQ2, Floppy Disk Controller IRQ9 Software Redirected to Int OAh 3 DRQ3, Reserved IRQ10 Reserved 4 DRQ4, Cascade for DMA IRQ11 Reserved 5 DRQ5, Reserved IRQ 12 Reserved 6 DRQ6, Reserved IRQ 13 80287 IRQ14 Fixed Disk Controller 7 DRQ7, Reserved IRQ 15 ReservedNMLKJIHGFEDCBA

IRQ3 Serial Port #2 IRQ4 Serial Port #1 IRQ5 Parallel Port #2 1RQ6 Floppy Disk Controller

IRQ7 Parallel Port #1

2-10 PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 2-11 Chapter 2 Hardware Description Chapter 2 Hardware DescriptionKJIHGFEDCBA

2.8 DMA Channels 2.9 Interrupt Controllers

The PAT48PG contains the equivalent of two 8237A DMA controllers in the 82C895. The PAT48PG contains two Intel 8259A compatible inter­ rupt controllers in the 82C895. Sixteen channels are parti­

The 82C895 provides the user with two DMA controllers, tioned into the cascaded controllers (INTC1, INTC2) with 8 four channels of DMAfDMA # 1) for 8-bit transfers, and three inputs each. Of these 16 channels, three are connected inter­ channels of DMAfDA/J H2) for 16 bit transfers.(The first nally to various devices, allowing 13 user definable channels 16-bit DMA channel is used for cascading.) of interrupt. Any or all of these interrupts can be masked.

ChannelYXWVUTSRQPONMLKJIHGFEDCBAFunction Level Fu nction NMI RAM Parity Check Controller #1 Controller #2 IRQO System Timer Output 1RQ1 Keyboard 0NMLKJIHGFEDCBA DRQO, Reserved IRQ2 Interrupt Cascade 1 DRQ1, SDLC

2 DRQ2, Floppy Disk Controller IRQ8 Real Time Clock IRQ9 Software Redirected to Int OAh 3 DRQ3, Reserved IRQ10 Reserved 4 DRQ4, Cascade for DMA IRQ! 1 Reserved 5 DRQ5, Reserved IRQ12 Reserved 6 DRQ6, Reserved IRQ 13 80287

7 DRQ7, Reserved 1RQ14 Fixed Disk Controller IRQ 15 Reserved

IRQ3 Serial Port #2 IRQ4 Serial Port #1 IRQ5 Parallel Port #2 IRQ6 Floppy Disk Controller IRQ7 Parallel Port #1

2-10 PAT48PG "Green" 486 VLB Motherboard User’s Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 2-11 Chapter 2 Hardware DescriptionKJIHGFEDCBA Chapter 3 Configuring the PAT48PG

2.10 Real Time Clock and CMOS RAMSRQPONMLKJIHGFEDCBA Chapter 3 Configuring the PAT48PGYXWVUTSRQPONMLKJIHGFEDCBA

The PAT48PG contains an MCI46818 compatible Real This chapter provides illustrated instruction on configuring Time Clock (RTC) and 128 bytes of CMOS RAM in the the PAT48PG motherboard. 82C206.

This chapter is divided into four major areas. The CMOS RAM stores the system’s configuration informa­ tion entered via the Setup program. The RTC and the CMOS □ 3.1 CPU Related Jum pers/Switches RAM are kept active by a battery when the system power is 3.1.1 Installing the CPU turned off. 3.1.2 Setting CPU Related Jumpers

Note □ 3.2 M ain Memory Configurations/Installation 3.2.1 Installing Memory The Real Time Clock and the CMOS RAM are kept NMLKJIHGFEDCBA active by an on board rechargeable battery. The 3.2.2 Setting Memory Related Jumpers PAT48PG also provides an interface for an external battery. □ 3.3 Cache Memory Configuration/Installation

3.3.1 Installing Cache Memory

3.3.2 Setting Cache Related Jumpers

□ 3.4 Miscellenous Jumpers/Switches

2-12 PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 3-1 Chapter 3 Configuring the PAT48PGNMLKJIHGFEDCBA Chapter 3 Configuring the PAT48PG

3.1 CPU Related Ju mpers and SwitchesYXWVUTSRQPONMLKJIHGFEDCBA3.1.1 Installing and/or Upgrading the CPU

To install a CPU, refer to the following figures. If there is a ZIF socket, lift the lever to its vertical position to install the KBD c 000 FT jPtZ3SRQPONMLKJIHGFEDCBACTRL CPU.

r7

I JP3

CPU Socket

BIOS [ E3 33 WB KJIHGFEDCBA

12 3 OPTi 78 82C602 JP5 Li

M2 Ml I I 1 iiiiiiiiimniiiiiiiiiiiiiii Step 1: Lift the lever OPTi I CLOCK H 82C895 " F’ A I Generator a lU i £ § § § § -*■ CPU JPS, JP7 Step 2: Place the CPU in the socket c c £ a fig o o § EffiEM |X|‘| Pl-hid JP17 F^l L!U1HH*

Step 3: Push the lever down Figure 3: CPU related jumpers to locked position

Figure 4: Installing the CPU

3-2 PAT48PG "Green" 486 VLB Motherboard User’s Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 3-3 Chapter 3 Configuring the PA T48PGKJIHGFEDCBA Chapter 3 Configuring the PAT48PG

3.1.2 Setting CPU Related JumpersSRQPONMLKJIHGFEDCBA 3.1.2b Setting CPU Frequeny Related Jumpers

3.1.2a Setting CPU TypetRNAl - RNA4 & RNB1 - RNB3, JP12: Clock Frequency Selector W8 JP5: Clock Generator Frequency

RNA1-RNA4 W8 CPU Type RNA1 NMLKJIHGFEDCBA JP13: VL Card W rite W ait StateYXWVUTSRQPONMLKJIHGFEDCBA ...... I RNA2 486DX/DX2 ...... RNA3RNA4 RNA1 JP14: CPU Speed Indication for VL Cards RNA2 Intel, AMD RNA3 486DX4 RNA4 5x86 I; CPU Speed JP5 JP12 JP13 JP14 CPU M odels [ RNA1 Over Drive/P24CT _ RNA2 25MHz SX-25 Pentium OverDrive ] RNA3 1 [£3 2 DX2-5O J RNA4 3 a q 4 1 2 P24T-63 3 RNA1 £[■"■] 6 3 RNA2 7 o » 3 I RNA3 486SX 3 RNA4 ] RNA1 33MHz SX-33 ] RNA2 Cyrix 486DX 1 RNA3 3[£=]4 1 2 DX-33 MHBI RNA4 5 □ B DX2-66 7 □ □ B P24T-83 RNB1-RNB3 CPU Type DX4-100 j HMM RNB1 40MHz DX-40 |oooo OOOO I RN B2 1 - . 2 Typical 486 DX2-80 |oooooooo] RNB3 3RT] 4 1 2 5[°~°1 6 DX4-120 |oooo oooo | RNB 1 Intel S-series MM RNB2 AMD Enhance |oooo oooo~| RNB3 Cyrix 5x86 50MHz DX-50 |oooo OOOO I RNB1 3 □ □ 4 1 2 loooooooo] RNB2 Cyrix 486 CPU 5|a °| 6 ■MM RNB3______7 Ip~°1 8 Note: The difference between a typng a typical 486 and S-series 486 is in the power saving mode only. Most of the Intel CPUs shipped in 1994 or later are S-series.

3-4 PAT48PG "Green" 486 VLB Motherboard User’s Manual PAT48PG "Green" 486 VLB Motherboard User's Manna! 3-5 Chapter 3 Configuring the PAT48PGNMLKJIHGFEDCBA Chapter 3 Configuring the PAT48PG

3.1.2c Intel & AMD CPU Internal Cache W.B Selection: 3.2 MainKJIHGFEDCBA Memory InstallingSRQPONMLKJIHGFEDCBA JP15, JP16 1.MemoryYXWVUTSRQPONMLKJIHGFEDCBA cofiguration with RNC1 installed

JP15 JPI6

Intel, AMD 1 2 1 I

W rite Back “1 I I3ank0 Bankl Bank2 Total 1 2 3 1 Ml (single) M2 (single) SIMM Memory Others - 256Kx36 256Kx36 2M

!Mx36 4M

256Kx36 1Mx36 5M

256Kx36 256Kx36 1Mx9 6M

!Mx36 1Mx36 8M

!Mx36 1Mx9 8M

4Mx36 16M

256Kx36 4Mx36 17M

1Mx36 4Mx36 20M

!Mx36 4Mx9 20M

4Mx36 4Mx36 32M

4Mx36 4Mx9 32M

16Mx36 64M

16Mx36 16Mx36 128M

16Mx36 16Mx9 128M

3-6 PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 3-7 Chapter 3 Configuring the PAT-I8PG Chapter YXWVUTSRQPONMLKJIHGFEDCBA3 Configuring the I’. 17A8PG

2.Momory configurations with RNC2 installed 3.Memory configuations with RNC3 installed

MI socket M2 scoket Total BankO Bankl Bank2 Bank3 Memory 5l2Kx36KJIHGFEDCBA 2M BankO Bankl Bank2 Total !Mx36| ----- 4M SIM 1-4 M2 (single) Ml (single) Memory 512Kx36 512Kx36 4M 256Kx9 256Kx36 2MNMLKJIHGFEDCBA _ 512Kx36 1Mx36 1Mx9 4M 2Mx36 " 8M | SRQPONMLKJIHGFEDCBA!M x36| z— 256Kx9 1Mx36 5M !Mx36 8M 512Kx36 2Mx36 JOM 256Kx9 256Kx36 !Mx36 6M _ !Mx36 2Mx36 12M 1Mx9 1Mx36 8M 4Mx36L —- -- I 16M 1Mx9 1Mx36 8M 2Mx36 __ 2Mx36 j6M !Mx36| 4Mx36 ~~ 20M 4Mx9 16M 8Mx36 _ 32M 256Kx9 4Mx36 17M 4Mx36------4Mx36 32M 1Mx9 4Mx36 20M 16Mx36,____ — 64M

1Mx9 4Mx36 20M L _ _ 8Mx36 8Mx36 64M I_ _ 32Mx36 128M 4Mx9 4Mx36 32M ' 16Mx36, I6Mx36 128M 4Mx9 4Mx36 32M

16Mx9 64M

16Mx9 16Mx36 128M Ml socket SIM 1-4 Total BankOBankl Bank 2 Memory 16Mx9 16Mx36 128M 512Kx36 !Mx9 6M !Mx36| ~ !Mx9 8M !Mx36____ - 4Mx9 20M 16Mx36 16Mx9 128M

3-8 PATA8PG "Green" -186 VLB Motherhoard User's Manual PAT48PG "Green" -186 VLB Motherboard User’s Manual 3-9 Chapter 3 Configuring the PAT48PG Chapter 3 Configuring the PAT48PGNMLKJIHGFEDCBA

3.3 InstallingKJIHGFEDCBA Cache Memory 3.4 Miscellenous JumpersYXWVUTSRQPONMLKJIHGFEDCBA

U30 J 32Kx8 ) I I I I U39 >□□□□□□ DOO □□□□□!

U31 3 32Kx8 Video Adapter Selection Jumper: JP1

Ipp 000 0 □□□□□□□□ U32 3 32Kx8 U41 (□ □ □ □ □ □ □ □ DaaaoD JPt FunctionSRQPONMLKJIHGFEDCBA ID UU U DU ULI U UL) U33 32Kx8 I I I I U42 IOOOOPPOPPOPDD o Color 3 8Kx8 U43

Monochrome

jPe’Wj ■ JP7

Figure 5: 128KB of cache memoi'y

Battery Selection Jumper: JP2 U30 3 32Kx8 3 32Kx8 U39

U31 3 32Kx8 32Kx8 U40 JP2 Function 32Kx8 3 32Kx8 U41 U32 3 1 2 3

U33 3 32Kx8 3 32Kx8 U42 12 3 Use the on board memory

316Kx8/32Kx8 U43

2 3 Use an external battery' connected to J3

10 0 1 JP65laaJP7 Figure 6: 256KB of cache memory

3 - 10 PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 4S6 VLB Motherboard User's Manual 3-11 Chapter 3 Configuring the PAT48PGSRQPONMLKJIHGFEDCBA Chapter 4YXWVUTSRQPONMLKJIHGFEDCBA Installation

BIOS ROM Type: JP3 Chapter 4 InstallationKJIHGFEDCBA

The PAT48PG can accommodate a flash ROM or an ( EPROM. Use JP3 to select whether a flash ROM or an This chapter describes the interface that the PAT48PG pro­ EPROM is being used in socket U ll. vides for creating a working system. Refer to Figure 2 for the location of the connectors.

The following items are covered in this chapter. JP3 Function

2 3 Flash ROM

□ 4.1 Keyboard Connector: JI

l-TROM | □ 4.2 External Battery Connector: J3 □ 4.3 Power Supply Connector: J4

□ 4.4 Power Saving Switch and LED Connector: J5 & J8

□ 4.5 Speaker Connector: J7(Pins 1-4)

□ 4.6 Power LED and Keylock Connector: J7(Pins 11 - 15)

□ 4.7 Turbo Switch Connector: J7(Pins 7 & 17)

□ 4.8 Turbo LED Connector: J7(Pins 8 & 18)

□ 4.9 Reset Switch Connector: J7(Pins 9 & 19)

□ 4.10 Hard Disk Access LED Connector: J7(Pins 10 & 20) and J6

c

3- 12 PA T48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 4-1 Chapter 4 InstallationKJIHGFEDCBA Chapter 4 Installation

4.1 Keyboard Connector: J1 4.2 External Battery Connector: J3YXWVUTSRQPONMLKJIHGFEDCBA

The keyboard connector, JI, is a 5-pin DIN connector for This d-pin connector, J3, allows the user to connect an attaching an IBM AT or an IBM Enhanced 101-key compat­ external battery to maintain the information stored in the ible keyboard. CMOS RAM.

J3 Pin #NMLKJIHGFEDCBADescription

i Vcc

2 N. C.

3 Ground

4 Ground

JI Pin # Description

1 Keyboard Clock

2 Keyboard Data

3 N.C.

4 Ground

5 Vcc

0

4-2 PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User’s Manual 4-3 Chapter 4 Installation Chapter 4 InstallationSRQPONMLKJIHGFEDCBA

4.3 Power Supply Connector: J4 4.4 Power Saving Switch and LED Connector: J8 & J5 When using an AT compatible power supply, plug both of YXWVUTSRQPONMLKJIHGFEDCBA the power supply connectors into J4. 1 J8, allows the user to attach a power saving switch located in the system’s front panel. To switch the system into power Make sure the power supply connectors are connected in the saving mode, simply press switch and the LED connected to right orientation. The power supply connectors are connected J5 will be on and the system will immediately go into power in the right orientation if the black wires of each power cable saving mode. Orientation is not required when attaching the are ADJACENT to each other. That is, black wires of each switch to J8. connector should be aligned in the center of the power supply connector, J4, of the PAT48PG To return to normal mode, press switch again or type any key on the keyboard or move the mouse. The following table indicates the pin-out assignments of the power supply connector.

J5 Pin #NMLKJIHGFEDCBADescription

1 Anode J4 Pin # Description W ire Color 2 Cathode 1 -CO Power Good Orange

2 -CO +5V Red A/ofe 3 -co +12V Yellow The PAT48PG can be configured to go into power 4 -co -12V Blue saving mode via the system setup program. Refer to -co 5 Ground Black the system setup screen for details. 6 -co Ground Black

7 -co Ground Black

8 -co Ground Black

9 -co -5V White

10 -co +5V Red

11 -co +5V Red

12 -co +5V RedKJIHGFEDCBA

4-4 PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 4-5 Chapter 4 Installation Chapter 4 InstallationSRQPONMLKJIHGFEDCBA

4.5 Speaker Connector: J7(Pins 1-4)YXWVUTSRQPONMLKJIHGFEDCBA4.6 Power LED and Keylock Connector: J7(Plns 11-15) Pins 1 - 4 of the 20-pin connector, J7, provide an interface to a speaker for audio tone generation. A speaker with 8-0hm Pins 11 - 15 of the 20-pin connector, J7, allow the user to or higher impedence is recommended. connect the power LED and keylock switch of the system’s front panel. The power LED indicates the ON/OFF status of Note the system. The keylock switch, when CLOSED, will disable Orientation is not required when connecting a speaker NMLKJIHGFEDCBA the keyboard function. to pins 1 - 4 of J7.

J8 Pin # Description 1 ______KJIHGFEDCBA10 1 Speaker Out | o o o o | o o 2 N.C. o __ Sffl 3 Ground 20 4 + 5V J7 Pin# Description

1______10 11 Power LED o o [71 [71[71 [71 12 N.C. I O O O O O | O |o | | O I | O I | o| 13 Ground Ti 20~ 14 Keylock

15 Ground

4-6 PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 4-7 Chapter 4 Installation Chapter 4 InstallationKJIHGFEDCBA

4.7 Turbo Switch Connector: J7(Pins 7 & 17) 4.8 Turbo LED Connector: J7(Pins 8 & 18)

Pins 7 & 17 of theYXWVUTSRQPONMLKJIHGFEDCBA 20-pin connector, J7, allow the user to Pins 8 & 18 of the 20-pin connector, J7, provide the user with connect a turbo switch on the front panel of the system an interface for connecting a turbo LED indicator in the chassis. system’s front panel.

A turbo switch is usually a push-on switch. When the switch This LED, when on, indicates the TURBO(/r[/Z,L) speed is on, pins 7 & 17 are SHORTED and the system will be mode of the PAT48PG system. running at FULL(TURBO) speed.

To switch to LOW (NON-TURBO) speed, simply PRESS the switch. To return to turbo speed, press the switch again.

1 ______10 Note I o o o T] O O Orientation is not required when connecting a turbo I o o o o o I o stwSRQPONMLKJIHGFEDCBA switch to pins 7 & 17 of J7. Ti 20

1______10 J7 Pin# Description I o o o o o O I 8NMLKJIHGFEDCBAAnode I o o o o o] o KW 18 Cathode Ti 20

4-8 PAT48PG "Green" 486 VLB Motherboard User's Manual PAT48PG "Green" 486 VLB Motherboard User’s Manual 4-9 Chapter 4 Installation Chapter 4 InstallationKJIHGFEDCBA

4.9 Reset Switch Connector: J7(Pins 9 &NMLKJIHGFEDCBA 19) 4.10 Hard Disk LED Connector: J7(Pins 10 & 20), J6 Pins 9 & 19 of the 20-pin connector, J7, provide an interface for a reset switch. The reset switch allows the user to reset These connectors allow the user to connect the hard disk the system without turning the power switch off and on. access LED on the system’s front panel. The LED will be on whenever the system is accessing the hard drive. To reset the PAT48PG based system, SHORT pins 9 and 19 of J7 by pressing the reset switch of the system chassis. Connect the 2-pin connector from the system chassis to pins 10 & 20 of J7. Also, make a connection from J6 to the hard Note disk controller’s LED interface. Orientation is not required when connecting a reset switch pins 9 and 19 of J7.YXWVUTSRQPONMLKJIHGFEDCBA Note

1 ______10 You may also connect HDD LED on the system's front panel directly to the hard disk controller's LED interface [ o o o without using these connectors. I o o oSRQPONMLKJIHGFEDCBAMW Ti 20

1 10

I o o o o I o o I o o o o T| o i Ti 20

Pin# Description J7(Pins 10&20) LED In

J6 LED Out

4-10 PAT48PG "Green" 486 VLB Motherboard User’s Manual PAT48PG "Green" 486 VLB Motherboard User's Manual 4-11 Chapter 4 InstallationYXWVUTSRQPONMLKJIHGFEDCBA

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4-12 PAT48PG "Green" 486 VLB Motherboard User's Manual