DOCSLIB.ORG

Lecture 34: Designing Amplifiers, Biasing, Frequency Response Context

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Lecture 34: Designing Amplifiers, Biasing, Frequency Response Context EECS 105 Spring 2004, Lecture 34 Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will do a review of the approximate frequency analysis of circuits which have a single dominant pole. Department of EECS University of California, Berkeley 1 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Reading z Chapter 9, multi-stage amplifiers. The frequency analysis is in the first section of chapter 10, but we won’t go farther into chapter 10 for a while. z The Lectures on Wednesday and Friday will be given by Joe and Jason, respectively. They will be doing several example problems. Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Lecture Outline z Example 1: Cascode Amp Design z Example 2; CS NMOS->CS PMOS z Review of frequency analysis (with a dominant pole) Department of EECS University of California, Berkeley 2 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Amplifier Schematic Note that the backgate connection for M2 is not specified: ignore gmb Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Complete Amplifier Schematic Bias voltages derived from Goals: gm1 = 1 mS, transistors under Rout =10 MΩ similar operating conditions to Cascode current source the transistors For high roc they supply CG output CS input, with low voltage gain Department of EECS University of California, Berkeley 3 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Current Supply Design High impedance current source means all of the small signal current goes to the load resistance, giving more SS voltage gain Output resistance goal requires large roc for high gainÆ so we used a cascode current source Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Totem Pole Voltage Supply DC voltages must be set for the cascode current supply transistors M3 and M4, as well as the gate of M2. M2B supplies the Bias quiescent voltage For the CG stage Department of EECS University of California, Berkeley 4 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Miller Capacitance of Input Stage Find the Miller capacitance for Cgd1 Cgd Input resistance to common-gate second stage is low Æ gain across Cgd1 is small. Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Two-Port Model with Capacitors Miller capacitance: C = (1− A )C M vCgd 1 gd1 g A ≅ − m1 vCdg1 gm2 Department of EECS University of California, Berkeley 5 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Schematic Goals: gm1 = 1 mS, Rout =10 MΩ Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Device Sizes M1: select (W/L)1 = 200/2 to meet specified gm1 = 1 mS Æ find VBIAS = 1.2 V Cascode current supply devices: select VSG = 1.5 V (W/L)4= (W/L)4B= (W/L)3= (W/L)3B = 64/2 Department of EECS University of California, Berkeley 6 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Device Sizes M2: select (W/L)2 = 50/2 to meet specified Rout =10 MΩ Æ find VGS2 = 1.4 V Match M2 with diode-connected device M2B. Assuming perfect matching and zero input voltage, what is VOUT? Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Output (Voltage) Swing Maximum VOUT Minimum VOUT Department of EECS University of California, Berkeley 7 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Two-Port Model Find output resistance Rout -1 -1 λn = (1/20) V , λn = (1/50) V at L = 2 µm Æ -1 -1 ron = (100 µA / 20 V ) = 200 kΩ, rop = 500 kΩ 2I D2 2(100µA) gm2 = = = 500µS VGS 2 −VTn 1.4V −1V 2(−I D3 ) 2(100µA) gm3 = = = 400µS VSG3 +VTp 1.5V −1V Rout = roc || ro2 ()1+ gm2 RS 2 = ro3 (1+ gm3RS 3 )|| ro2 (1+ gm2ro1 ) Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Voltage Transfer Curve Open-circuit voltage gain: Av = vout / vin = - gm1Rout 3 7 dv vOUT = −10 ×10 = out dv 4 in Q ≈ −10,000 3 2 1 0 1 2 34vIN Department of EECS University of California, Berkeley 8 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Multistage Amplifier Design Example Start with basic two-stage transconductance amplifier: Why do this combination? Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Quiescent level shifts NMOS PMOS CS ⇑ ⇓ (typical) (typical) CG ⇑ ⇓ CD ⇓ ⇑ (known shift) (known shift) Source follower Department of EECS University of California, Berkeley 9 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith CS→CS Amplifier Direct DC connection: use NMOS then PMOS Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Current Supply Design Assume that the reference is a “sink” set by a resistor Must mirror the reference current and generate a sink for iSUP 2 Department of EECS University of California, Berkeley 10 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Use Basic Current Supplies Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Complete Amplifier Topology What’s missing? The device dimensions, the bias voltage and reference resistor Department of EECS University of California, Berkeley 11 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith DC Bias: Find Operating Points Find VBIAS such that VOUT = 0 V Device parameters: 2 2 µnCox = 50 µA/V µ pCox = 25 µA/V VTn = 1 V VTp = -1 V -1 -1 λn = 0.05 V λp = 0.05 V Device dimensions (for “lecture” design): (W/L)n = 50/2 (W/L)p = 80/2 Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Finding RREF + V Require IREF = - ID3 = 50 µA M3 − 2I D3 VSG3 = −VTp + µ pCox (W / L)3 RREF − 2×50µA 4 VSG3 = −(−1)V + =1+ =1.32V - 25µA(80 / 2) 40 V + − [V −VSG3 ]− [V ] I REF = 50µA = Rref [2.5 −1.32]− [− 2.5] 50µA = ⇒ Rref = 74kΩ Rref Department of EECS University of California, Berkeley 12 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith DC Operating Point IREF = 50 µA 2I D1 100µA 9 VBIAS = VGS1 = Vtn + =1+ −2 ≈ V µnCox (W / L) 50(µA/V )(50 / 2) 7 Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Small-Signal Device Parameters Transistors M1 and M2 gm1 = 350 µS ro1 = 400 kΩ gm2 = 315 µS ro2 = 400 kΩ Current supplies iSUP1 and iSUP2 roc1 = ro4 =400 kΩ roc2 = ro6 =400 kΩ Department of EECS University of California, Berkeley 13 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Two-Port Model Find Gm = iout / vin Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Output Voltage Swing Transistors M2 and M6 will limit the output swing Department of EECS University of California, Berkeley 14 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Limits to Output Voltage M6 will leave saturation when vOUT drops to: − 2I D6 vOUT ,MIN = V +VDS 6,sat = −2.5 + µnCox ()W / L 6 vOUT,MIN = -2.5 + 0.28 = - 2.22 V M2 will leave saturation when vOUT rises to: + 2(−I D2 ) vOUT ,MAX = V −VSD2,sat = 2.5 − µ pCox ()W / L 2 vOUT,MAX = 2.5 - 0.32 = 2.18 V What about M4? Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Output Current Swing Load resistor: pick RL = 25 kΩ Output current: iOUT = −vOUT / RL iOUT = iD6 − (− iD2 ) iOUT Limits: asymmetrical M2: can increase - iD2 vOUT M6: can’t increase iD6 Department of EECS University of California, Berkeley 15 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Output Current Limits • Positive output current (negative vOUT) iOUT ,MAX = iD6 − (0) = 50µA = −vOUT ,MIN / RL vOUT ,MIN = −(50µA)(25kΩ) = −1.25V (less negative than limit set by saturation of M6) • Negative output current (positive vOUT) No limit on current from M2, so voltage swing sets current limit iOUT ,MIN = −vOUT ,MAX / RL = − (2.18V / 25kΩ) = −87.2µA Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Transfer Curves (for RL = 25 kΩ) Loaded voltage gain = vout/vin = (gm1Rout1)(gm2Rout||RL) = 490 Loaded transconductance = iout/vin = (-gm1Rout1)(gm2)(Rout/(Rout + RL) = -19.5 mS iOUT [µA] vOUT 2 100 1 50 1 1 -2 -1 0 2 vIN -2 -1 0 2 vIN -1 -50 -2 -100 Department of EECS University of California, Berkeley 16 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Review: Frequency Resp of Multistage Amplifiers • We have a systematic technique to study amplifier performance (derive transfer function, study poles/zeros/Bode pltos). • In most cases, the systematic approach is too cumbersome. • We have a good qualitative understanding of circuit performance (e.g., CS suffers from Miller effect, CD andd CG are wideband stages …) • Open Circuit Time Constants: Analytical technique is capable of estimating only the dominant (lowest) pole …for a restricted class of amplifiers.
Load more

Recommended publications
  • Valve Biasing
    VALVE AMP BIASING Biased information How have valve amps survived over 30 years of change? Derek Rocco explains why they are still a vital ingredient in music making, and talks you through the mysteries of biasing N THE LAST DECADE WE HAVE a signal to the grid it causes a water as an electrical current, you alter the negative grid voltage by seen huge advances in current to flow from the cathode to will never be confused again. When replacing the resistor I technology which have the plate. The grid is also known as your tap is turned off you get no to gain the current draw required. profoundly changed the way we the control grid, as by varying the water flowing through. With your Cathode bias amplifiers have work. Despite the rise in voltage on the grid you can control amp if you have too much negative become very sought after. They solid-state and digital modelling how much current is passed from voltage on the grid you will stop have a sweet organic sound that technology, virtually every high- the cathode to the plate. This is the electrical current from flowing. has a rich harmonic sustain and profile guitarist and even recording known as the grid bias of your amp This is known as they produce a powerful studios still rely on good ol’ – the correct bias level is vital to the ’over-biased’ soundstage. Examples of these fashioned valves. operation and tone of the amplifier. and the amp are most of the original 1950’s By varying the negative grid will produce Fender tweed amps such as the What is a valve? bias the technician can correctly an unbearable Deluxe and, of course, the Hopefully, a brief explanation will set up your amp for maximum distortion at all legendary Vox AC30.
    [Show full text]
  • Bias Circuits for RF Devices
    Bias Circuits for RF Devices Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul A lot of RF schematics mention: “bias circuit not shown”; when actually one of the most critical yet often overlooked aspects in any RF circuit design is the bias network. The bias network determines the amplifier performance over temperature as well as RF drive. The DC bias condition of the RF transistors is usually established independently of the RF design. Power efficiency, stability, noise, thermal runway, and ease to use are the main concerns when selecting a bias configuration. A transistor amplifier must possess a DC biasing circuit for a couple of reasons. • We would require two separate voltage supplies to furnish the desired class of bias for both the emitter-collector and the emitter-base voltages. • This is in fact still done in certain applications, but biasing was invented so that these separate voltages could be obtained from but a single supply. • Transistors are remarkably temperature sensitive, inviting a condition called thermal runaway. Thermal runaway will rapidly destroy a bipolar transistor, as collector current quickly and uncontrollably increases to damaging levels as the temperature rises, unless the amplifier is temperature stabilized to nullify this effect. Amplifier Bias Classes of Operation Special classes of amplifier bias levels are utilized to achieve different objectives, each with its own distinct advantages and disadvantages. The most prevalent classes of bias operation are Class A, AB, B, and C. All of these classes use circuit components to bias the transistor at a different DC operating current, or “ICQ”. When a BJT does not have an A.C.
    [Show full text]
  • Chapter 4 BJT BIASING CIRCUIT Introduction – Biasing the Analysis Or Design of a Transistor Amplifier Requires Knowledge of Both the Dc and Ac Response of the System
    Chapter 4 BJT BIASING CIRCUIT Introduction – Biasing The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of the system. In fact, the amplifier increases the strength of a weak signal by transferring the energy from the applied DC source to the weak input ac signal The analysis or design of any electronic amplifier therefore has two components: •The dc portion and •The ac portion During the design stage, the choice of parameters for the required dc levels will affect the ac response. What is biasing circuit? Biasing: Application of dc voltages to establish a fixed level of current and voltage. Purpose of the DC biasing circuit • To turn the device “ON” • To place it in operation in the region of its characteristic where the device operates most linearly . •Proper biasing circuit which it operate in linear region and circuit have centered Q-point or midpoint biased •Improper biasing cause Improper biasing cause •Distortion in the output signal •Produce limited or clipped at output signal Important basic relationship IECB= II + I β = C I B IE =+≅ (β 1) IIBC VVVCB= CE − BE Operating Point •Active or Linear Region Operation Base – Emitter junction is forward biased Base – Collector junction is reverse biased Good operating point •Saturation Region Operation Base – Emitter junction is forward biased Base – Collector junction is forward biased •Cutoff Region Operation Base – Emitter junction is reverse biased BJT Analysis DC AC analysis analysis Calculate gains of the Calculate the DC Q-point amplifier
    [Show full text]
  • Transistor Biasing
    Transistor Biasing Transistor Biasing is the process of setting a transistors DC operating voltage or current conditions to the correct level so that any AC input signal can be amplified correctly by the transistor Transistor Biasing- S.Gayathri Priya 1 Need for Biasing A transistors steady state of operation depends a great deal on its base current, collector voltage, and collector current and therefore, if a transistor is to operate as a linear amplifier, it must be properly biased to have a suitable operating point. Establishing the correct operating point requires the proper selection of bias resistors and load resistors to provide the appropriate input current and collector voltage conditions. Transistor Biasing- S.Gayathri Priya 2 Q Point The correct biasing point for a bipolar transistor, either NPN or PNP, generally lies somewhere between the two extremes of operation with respect to it being either “fully-ON” or “fully- OFF” along its load line. This central operating point is called the “Quiescent Operating Point”, or Q-point for short. Transistor Biasing- S.Gayathri Priya 3 BJT Biasing methods The various types of biasing methods are: • Fixed Bias • Collector to base bias • Voltage divider bias Transistor Biasing- S.Gayathri Priya 4 Fixed Bias The transistors base current, IB remains constant for given values of Vcc, and therefore the transistors operating point must also remain fixed.Hence referred as fixed biasing Transistor Biasing- S.Gayathri Priya 5 Fixed Bias This two resistor biasing This type of transistor network is used to establish biasing arrangement is also the initial operating region of beta dependent biasing as the transistor using a fixed the steady-state condition of current bias.
    [Show full text]
  • The MOS Tetrode Transistor Is Studied in This Project
    AN ABSTRACT OF THE THESIS OF Thawee Limvorapun for the Master of Science (Name) (Degree) in Electrical and Electronics Engineering (Major) 4; -- 7 -- presented on . (Date) Title: THE MOS TETROD.° mr""TcTcm"" Redacted for Privacy Abstract approved: James C. Lodriey The MOS tetrode transistor is studied in this project. This device is ideally suited for high frequency and switching application. In effect it is the solid state analogy of a multigrid vacuum tube performing a very useful multigrid function. A new structure is developed for p-channel 10 ohm-cm. silicon substrate of (111) crystal orientation. This structure consists of an aluminum con- trol gate G1 buried in the pyrolytic SiO2, or E-gun evapo- ration SiO with thermal oxide for the control gate in- 2' sulator. An offset gate G2 produces another channel L2 and causes a longer pinchoff region in the device. The drain breakdown can be maximized so as to approach bulk breakdown as the result of the redistribution of the surfacefield. is very low, ap- The Miller feedback capacitance CGl-D proaching values similar to those of the vacuum pentodes. This paper describes the design, artwork, pyrolytic SiO and E-gun evaporation SiO process. The V-I 2 2 characteristics, dynamic drain resistance, capacitance, small signal equivalent circuit and large signal limitation, and drain breakdown voltage are also discussed. THE MOS TETRODE TRANSISTOR by Thawee Limvorapun A THESIS submitted to Oregon State University in partial fulfillment of the requirements for the degree of Master of Science June 1973 APPROVED: Redacted for Privacy Associa e rofessor of Electrical andEleC-E-Anics Engineering in charge of major Redacted for Privacy Head of Department of Electrical and Electronics Engineering Redacted for Privacy Dean of Graduate School Date thesis is presented 6- 7- 7 2 Typed by Erma McClanathan for Thawee Limvorapun ACKNOWLEDGMENTS I wish to express my sincere appreciation to my advisor, Professor James C.
    [Show full text]
  • Biasing Techniques for Linear Power Amplifiers Anh Pham
    Biasing Techniques for Linear Power Amplifiers by Anh Pham Bachelor of Science in Electrical Engineering and Economics California Institute of Technology, June 2000 Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degree of Engineering and Computer Science Master of Engineering in Electrical 8ARKER at the &UASCHUSMrSWi#DTE OF TECHNOLOGY MASSACHUSETTS INSTITUTE OF TECHNOLOGY JUL 3 12002 May 2002 LIBRARIES @ Massachusetts Institute of Technology 2002. All right reserved. Author Department of Electrical Engineering and Computer Science May 2002 Certified by _ Charles G. Sodini Professor of Electrical Engineering and Computer Science Thesis Supervisor Accepted by Arthuf-rESmith, Ph.D. Chairman, Committee on Graduate Students Department of Electrical Engineering and Computer Science 2 Biasing Techniques for Linear Power Amplifiers by Anh Pham Submitted to the Department of electrical Engineering and Computer Science on May 10, 2002 in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering and Computer Science Abstract Power amplifiers with conventional fixed biasing attain their best efficiency when operate at the maximum output power. For lower output level, these amplifiers are very inefficient. This is the major shortcoming in recent wireless applications with an adaptive power design; where the desired output power is a function of the bit-error rate, channel characteristics, modulation schemes, etc. Such applications require the power amplifier to have an optimum performance not only at the peak output level, but also across the adaptive power range. An adaptive biasing topology is proposed and implemented in the design of a power amplifier intended for use in the WiGLAN (Wireless Gigabits per second Local Area Network) project.
    [Show full text]
  • Lecture09-MOSFET(2)
    EE105 – Fall 2014 Microelectronic Devices and Circuits Prof. Ming C. Wu [email protected] 511 Sutardja Dai Hall (SDH) Lecture 9: MOSFET (2): Scaling, DC bias 1 NMOS Transistor Capacitances: Saturation Region • Drain no longer connected to channel 2 C = C +C W C = C W GS 3 GC GSO GD GDO Lecture 9: MOSFET (2): Scaling, DC bias 2 1 SPICE Model for NMOS Transistor Typical default values used by SPICE: 2 KP = 50 or 20 µA/V γ = 0 λ = 0 VTO = 1 V 2 µn or µp = 500 or 200 cm /V-s 2ΦF = 0.6 V CGDO = CGSO = CGBO = CJSW = 0 Tox= 100 nm Lecture 9: MOSFET (2): Scaling, DC bias 3 MOS Transistor Scaling • All physical dimensions shrinks by a factor of α • All voltages (including threshold voltage) reduced by α also – Constant field scaling • Drain current: * εox W α " vGS VTN vDS % vDS iD iD = µn $ − − ' = Tox α L α # α α 2α & 2α α * !W $! L $ C • Gate Capacitance: * " * * εox GC CGC = (Cox ) W L = # &# & = Tox α " α %"α % α • Circuit delay in a logic circuit. * * * ΔV CGC ΔV /α τ τ = CGC * = = iD α iD /α α Lecture 9: MOSFET (2): Scaling, DC bias 4 2 MOS Transistor Scaling Scale Factor α (cont.) • Circuit and Power Densities: V i P P* = V * i* = DD D = DD D α α α 2 P* P* P α 2 P = = = extremely important result! A* W *L* W L A ( α)( α) • Power-Delay Product: P τ PDP PDP* P* * € = τ = 2 = 3 α α α • Cutoff Frequency: gm µn € ω = = V −V T C L2 ( GS TN ) GC – fT improves with square of channel length reduction € Lecture 9: MOSFET (2): Scaling, DC bias 5 Impact of Velocity Saturation • At low electric field, electron velocity is proportional to field • At high electric field, the velocity reaches a maximum called saturation velocity, vSAT " CoxW iD = (vGS −VTN )vSAT 2 • The drain current is proportional to (vGS – VTN) rather than its square • There are (many) other corrections to the basic model when the channel become very short – Interested, take EE130 Lecture 9: MOSFET (2): Scaling, DC bias 6 3 NMOSFET in OFF State • We had previously assumed that there is no channel current when vGS < VTN.
    [Show full text]
  • Getting the Best out of Photodiode Detectors
    Getting the best out of photodiode detectors Advanced Technology Development Group Gray Cancer Institute A great number of biomedical and analytical applications require the detection of light; this includes chemiluminescence, bioluminescence, and fluorescence as well as many others. These applications require the use of a detector to convert light into an electrical signal, and to accomplish this there are three basic technologies: photomultiplier tubes (PMTs), avalanche photodiodes (APDs), and photodiodes. Photomultipliers are discussed in a separate document. When to use a particular detector is not always that straightforward to determine. A photodiode is suitable in applications where there is plenty of light available. In applications with very weak signals, a photomultiplier is the best choice. But there are applications where the choice is not clear. Focusing on solid-state options, this note reviews solid-state detector characteristics and the criteria for detector and amplifier selection. The silicon photodiode A silicon photodiode is essentially a P-N junction consisting of a positively doped P region and a negatively doped N region. Between these two regions exists an area of neutral charge known as the depletion region. When light enters the device, electrons in the structure become excited. If the energy of the light is greater than the bandgap energy of the material, electrons will move into the conduction band. The result is creation of holes throughout the device in the valence band where the electrons were originally located. Electron-hole pairs generated in the depletion region drift to their respective electrodes: N for electrons and P for holes, resulting in a positive charge build-up in the P layer and a negative charge build-up in the N layer.
    [Show full text]
  • Linear Amplifier Basics; Biasing
    6.012 - Microelectronic Devices and Circuits Lecture 17 - Linear Amplifier Basics; Biasing - Outline • Announcements Announcements - Stellar postings on linear amplifiers Design Problem - Will be coming out next week, mid-week. • Review - Linear equivalent circuits LECs: the same for npn and pnp; the same for n-MOS and p-MOS; all parameters depend on bias; maintaining a stable bias is critical • Biasing transistors Current source biasing Transistors as current sources Current mirror current sources and sinks • The mid-band concept Dealing with charge stores and coupling capacitors • Linear amplifiers Performance metrics: gains (voltage, current, power) input and output resistances power dissipation bandwidth Multi-stage amplifiers and two-port analysis Clif Fonstad, 11/10/09 Lecture 17 - Slide 1 The large signal models: A qAB q : Excess carriers on p-side plus p-n diode: IBS AB excess carriers on n-side plus junction depletion charge. B qBC C BJT: npn q : Excess carriers in base plus E- !FiB’ BE (in F.A.R.) iB’ B junction depletion charge B qBC: C-B junction depletion charge IBS qBE E D q : Gate charge; a function of v , MOSFET: qDB G GS qG v , and v . n-channel DS BS iD qDB: D-B junction depletion charge G B qSB: S-B junction depletion charge S qSB Clif Fonstad, 11/10/09 Lecture 17 - Slide 2 Reviewing our LECs: Important points made in Lec. 13 We found LECs for BJTs and MOSFETs in both strong inversion and sub-threshold. When vbs = 0, they all look very similar: in iin Cm iout out + + v in gi gmv in go v out C C - i o - common common Most linear circuits are designed to operate at frequencies where the capacitors look like open circuits.
    [Show full text]
  • Lecture #3 BJT Biasing Circuits Instructor
    Banna Benha University - Faculty of Engineering at Shoubra © Ahmad El ECE-312 Electronic Circuits (A) Lecture #3 BJT Biasing Circuits Instructor: Dr. Ahmad El-Banna October 2014 Banna Agenda - Operating Point © Ahmad El Transistor DC Bias Configurations Design Operations Various BJT Circuits 312 2014 Lec#3 , Oct , Troubleshooting Techniques & Bias Stabilization - ECE Practical Applications 2 Banna Introduction - • Any increase in ac voltage, current, or power is the result of a transfer of energy from the applied dc supplies. © Ahmad El • The analysis or design of any electronic amplifier therefore has two components: a dc and an ac portion. • Basic Relationships/formulas for a transistor: 312 2014 Lec#3 , Oct , - • Biasing means applying of dc voltages to establish a fixed level of ECE current and voltage. >>> Q-Point 3 Banna Operating Point - • For transistor amplifiers the resulting dc current and voltage establish an operating point on the characteristics that define the © Ahmad El region that will be employed for amplification of the applied signal. • Because the operating point is a fixed point on the characteristics, it is also called the quiescent point (abbreviated Q-point). Transistor Regions Operation: 1. Linear-region operation: Base–emitter junction forward-biased Base–collector junction reverse-biased 312 2014 Lec#3 , Oct , 2. Cutoff-region operation: - Base–emitter junction reverse-biased Base–collector junction reverse-biased ECE 3.Saturation-region operation: Base–emitter junction forward-biased 4 Base–collector junction forward-biased Banna - © Ahmad El • Fixed-Bias Configuration • Emitter-Bias Configuration • Voltage-Divider Bias Configuration • Collector Feedback Configuration • Emitter-Follower Configuration 312 2014 Lec#3 , Oct , • Common-Base Configuration - • Miscellaneous Bias Configurations ECE TRANSISTOR DC BIAS CONFIGURATIONS 5 Banna Fixed-Bias Configuration - • • Fixed-bias circuit.
    [Show full text]
  • Photodiode Amplifiers
    Photodiode Amplifiers Changing Light to Electricity 1 Paul Rako Strategic Applications Engineer Amplifier Group 2 The Photodiode: Simple? 2 Volts Tiny current flows here (10 nanoAmperes) Light Big Resistor (1 Meg) Makes about a 10 millivolts here 3 © 2004 National Semiconductor Corporation The Photodiode: Dark Current No, not really 2 Volts (diode leakage) simple: flows too and is Light worse with temp. Big resistors make noise 10 millivolts is not very useful. 4 © 2004 National Semiconductor Corporation The Photodiode: Worse yet: 2 Volts High impedance point difficult to interface with. Light Diodes are capacitors too, so fast signals And the capacitance are difficult. changes with voltage across the diode. 5 © 2004 National Semiconductor Corporation The Photodiode: Still Worse: 2 Volts Light To make the diode more And that big junction sensitive to light has even more you make the P-N capacitance. junction big. 6 © 2004 National Semiconductor Corporation Inside the Photodiode: A cap and a current source: The bigger the voltage across the diode the further the junction boundaries are pushed apart and the lower the capacitance. 7 © 2004 National Semiconductor Corporation Inside the Photodiode: (And a really big resistor) There is also a bulk resisistivity to the diode but it is usually very high (100 M!). This represents the “Dark Current”. 8 © 2004 National Semiconductor Corporation Photodiode Amplifier Types: Two ways to use the diode: 1) The Photovoltaic Mode: - Light + Note ground– no voltage 9 across diode. © 2004 National Semiconductor Corporation Photodiode Amplifier Types: The Photovoltaic Mode: No voltage across diode means no current though the big resistor ~ • No dark current.
    [Show full text]
  • Lecture 12: Photodiode Detectors
    Lecture 12: Photodiode detectors Background concepts p-n photodiodes Photoconductive/photovoltaic modes p-i-n photodiodes Responsivity and bandwidth Noise in photodetectors References: This lecture partially follows the materials from Photonic Devices, Jia-Ming Liu, Chapter 14. Also from Fundamentals of Photonics, 2nd ed., Saleh & Teich, Chapters 18. 1 Electron-hole photogeneration Most modern photodetectors operate on the basis of the internal photoelectric effect – the photoexcited electrons and holes remain within the material, increasing the electrical conductivity of the material Electron-hole photogeneration in a semiconductor • absorbed photons generate free electron- h hole pairs h Eg • Transport of the free electrons and holes upon an electric field results in a current 2 Absorption coefficient Bandgaps for some semiconductor photodiode materials at 300 K Bandgap (eV) at 300 K Indirect Direct Si 1.14 4.10 Ge 0.67 0.81 - 1.43 kink GaAs InAs - 0.35 InP - 1.35 GaSb - 0.73 - 0.75 In0.53Ga0.47As - 1.15 In0.14Ga0.86As - 1.15 GaAs0.88Sb0.12 3 Absorption coefficient E.g. absorption coefficient = 103 cm-1 Means an 1/e optical power absorption length of 1/ = 10-3 cm = 10 m Likewise, = 104 cm-1 => 1/e optical power absorption length of 1 m. = 105 cm-1 => 1/e optical power absorption length of 100 nm. = 106 cm-1 => 1/e optical power absorption length of 10 nm. 4 Indirect absorption Silicon and germanium absorb light by both indirect and direct optical transitions. Indirect absorption requires the assistance of a phonon so that momentum and energy are conserved.
    [Show full text]