EECS 105 Spring 2004, Lecture 34

Lecture 34: Designing , , frequency response

Prof J. S. Smith

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Context

We will figure out more of the design parameters for the we looked at in the last lecture, and then we will do a review of the approximate frequency analysis of circuits which have a single dominant pole.

Department of EECS University of California, Berkeley

1 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Reading

z Chapter 9, multi-stage amplifiers. The frequency analysis is in the first section of chapter 10, but we won’t go farther into chapter 10 for a while.

z The Lectures on Wednesday and Friday will be given by Joe and Jason, respectively. They will be doing several example problems.

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Lecture Outline

z Example 1: Cascode Amp Design

z Example 2; CS NMOS->CS PMOS

z Review of frequency analysis (with a dominant pole)

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2 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Amplifier Schematic

Note that the backgate

connection for M2 is not specified: ignore gmb

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EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Complete Amplifier Schematic

Bias voltages derived from Goals: gm1 = 1 mS, under Rout =10 MΩ similar operating conditions to Cascode current source the transistors For high roc they supply CG output

CS input, with low voltage gain

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3 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Current Supply Design

High impedance current source means all of the small signal current goes to the load resistance, giving more SS voltage gain

Output resistance goal requires large

roc for high gainÆ so we used a cascode current source

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Totem Pole Voltage Supply DC voltages must be set for the cascode current

supply transistors M3 and M4, as well as the gate of M2.

M2B supplies the Bias quiescent voltage For the CG stage

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4 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Miller Capacitance of Input Stage

Find the Miller capacitance for Cgd1

Cgd

Input resistance to common-gate second stage is low Æ gain across

Cgd1 is small.

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Two-Port Model with Capacitors

Miller capacitance: C = (1− A )C M vCgd 1 gd1

g A ≅ − m1 vCdg1 gm2

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5 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Schematic

Goals: gm1 = 1 mS, Rout =10 MΩ

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Device Sizes

M1: select (W/L)1 = 200/2 to meet specified gm1 = 1 mS

Æ find VBIAS = 1.2 V

Cascode current supply devices: select

VSG = 1.5 V (W/L)4= (W/L)4B= (W/L)3= (W/L)3B = 64/2

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6 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Device Sizes

M2: select (W/L)2 = 50/2 to meet specified Rout =10 MΩ Æ find VGS2 = 1.4 V

Match M2 with -connected device M2B.

Assuming perfect matching and zero input voltage,

what is VOUT?

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Output (Voltage) Swing

Maximum VOUT

Minimum VOUT

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7 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Two-Port Model

Find output resistance Rout

-1 -1 λn = (1/20) V , λn = (1/50) V at L = 2 µm Æ -1 -1 ron = (100 µA / 20 V ) = 200 kΩ, rop = 500 kΩ

2I D2 2(100µA) gm2 = = = 500µS VGS 2 −VTn 1.4V −1V

2(−I D3 ) 2(100µA) gm3 = = = 400µS VSG3 +VTp 1.5V −1V

Rout = roc || ro2 ()1+ gm2 RS 2 = ro3 (1+ gm3RS 3 )|| ro2 (1+ gm2ro1 )

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Voltage Transfer Curve

Open-circuit voltage gain: Av = vout / vin = - gm1Rout

3 7 dv vOUT = −10 ×10 = out dv 4 in Q ≈ −10,000 3 2 1

0 1 2 34vIN

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8 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Multistage Amplifier Design Example

Start with basic two-stage amplifier:

Why do this combination?

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Quiescent level shifts

NMOS PMOS

CS ⇑ ⇓ (typical) (typical)

CG ⇑ ⇓

CD ⇓ ⇑ (known shift) (known shift) Source follower

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9 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith CS→CS Amplifier

Direct DC connection: use NMOS then PMOS

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EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Current Supply Design

Assume that the reference is a “sink” set by a

Must mirror the reference current and generate a sink for

iSUP 2

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10 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Use Basic Current Supplies

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Complete Amplifier Topology

What’s missing? The device dimensions, the bias voltage and reference resistor

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11 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith DC Bias: Find Operating Points

Find VBIAS such that VOUT = 0 V Device parameters:

2 2 µnCox = 50 µA/V µ pCox = 25 µA/V

VTn = 1 V VTp = -1 V -1 -1 λn = 0.05 V λp = 0.05 V Device dimensions (for “lecture” design):

(W/L)n = 50/2 (W/L)p = 80/2

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith

Finding RREF

+ V Require IREF = - ID3 = 50 µA

M3 − 2I D3 VSG3 = −VTp + µ pCox (W / L)3

RREF − 2×50µA 4 V = −(−1)V + =1+ =1.32V SG3 25µA(80 / 2) 40 V-

+ − [V −VSG3 ]− [V ] I REF = 50µA = Rref [2.5 −1.32]− [− 2.5] 50µA = ⇒ Rref = 74kΩ Rref

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12 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith DC Operating Point

IREF = 50 µA

2I D1 100µA 9 VBIAS = VGS1 = Vtn + =1+ −2 ≈ V µnCox (W / L) 50(µA/V )(50 / 2) 7

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Small-Signal Device Parameters

Transistors M1 and M2 gm1 = 350 µS ro1 = 400 kΩ

gm2 = 315 µS ro2 = 400 kΩ

Current supplies iSUP1 and iSUP2

roc1 = ro4 =400 kΩ

roc2 = ro6 =400 kΩ

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13 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Two-Port Model

Find Gm = iout / vin

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EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Output Voltage Swing

Transistors M2 and M6 will limit the output swing

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14 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Limits to Output Voltage

M6 will leave saturation when vOUT drops to:

− 2I D6 vOUT ,MIN = V +VDS 6,sat = −2.5 + µnCox ()W / L 6

vOUT,MIN = -2.5 + 0.28 = - 2.22 V

M2 will leave saturation when vOUT rises to:

+ 2(−I D2 ) vOUT ,MAX = V −VSD2,sat = 2.5 − µ pCox ()W / L 2

vOUT,MAX = 2.5 - 0.32 = 2.18 V

What about M4?

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Output Current Swing

Load resistor: pick RL = 25 kΩ

Output current: iOUT = −vOUT / RL

iOUT = iD6 − (− iD2 ) iOUT

Limits: asymmetrical

M2: can increase - iD2 vOUT

M6: can’t increase iD6

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15 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Output Current Limits

• Positive output current (negative vOUT)

iOUT ,MAX = iD6 − (0) = 50µA = −vOUT ,MIN / RL

vOUT ,MIN = −(50µA)(25kΩ) = −1.25V (less negative than limit set by saturation of M6)

• Negative output current (positive vOUT)

No limit on current from M2, so voltage swing sets current limit

iOUT ,MIN = −vOUT ,MAX / RL = − (2.18V / 25kΩ) = −87.2µA

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith

Transfer Curves (for RL = 25 kΩ)

Loaded voltage gain = vout/vin = (gm1Rout1)(gm2Rout||RL) = 490

Loaded transconductance = iout/vin = (-gm1Rout1)(gm2)(Rout/(Rout + RL) = -19.5 mS

iOUT [µA] vOUT 2 100 1 50

1 1 -2 -1 0 2 vIN -2 -1 0 2 vIN -1 -50 -2 -100

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16 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Review: Frequency Resp of Multistage Amplifiers

• We have a systematic technique to study amplifier performance (derive transfer function, study poles/zeros/Bode pltos). • In most cases, the systematic approach is too cumbersome. • We have a good qualitative understanding of circuit performance (e.g., CS suffers from Miller effect, CD andd CG are wideband stages …) • Open Circuit Time Constants: Analytical technique is capable of estimating only the dominant (lowest) pole …for a restricted class of amplifiers.

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith The Special Case The transfer function can have no zeroes and must

have a dominant pole ω1 << ω2, ω3, …, ωn

H o H ( jω) = 2 3 ()1+ jωb1 + ( jω) b2 + ( jω) b3 +...

Factor denominator: H H ( jω) = o ()()()1+ jω /ω1 1+ jω /ω2 ... 1+ jω /ωn

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17 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Approximating the Transfer Function Multiply out denominator: H H ( jω) = o ()()()1+ jω /ω1 1+ jω /ω2 ... 1+ jω /ωn H ≈ o ⎛ 1 1 1 ⎞ 1+ jω⎜ + +...+ ⎟ ⎝ ω1 ω2 ωn ⎠

Since ω1 << ω2, ω3, …, ωn Æ 1 1 1 1 b1 = + +...+ ≈ ω1 ω2 ωn ω1

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith

How to Find b1? See P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits (EE 140) for derivation

Result: b1 is the sum of open-circuit time constants τi which can be found by considering each capacitor Ci in the amplifier separately and finding the Thévenin resistance RTi of the network from the capacitor’s point of

viewÆ τi = RTi Ci

n 1 b = R C ⎯⎯→ ω ≈ 1 ∑i=1 Ti i 1 n R C ∑i=1 Ti i

Department of EECS University of California, Berkeley

18 EECS 105 Spring 2004, Lecture 34 Prof. J. S. Smith Finding the Thévenin Resistance

1. Open-circuit all capacitors (i.e.; remove them)

2. For capacitor Ci, find the resistance RTi across its terminals with all independent sources removed (voltages shorted, currents opened) … might need to apply a test voltage and find the current in some cases. Insight for design: the bandwidth of the amplifier will be limited by the capacitor that contributes the largest

τi = RTi Ci Æ not necessarily the largest Ci

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