EE105 – Fall 2014 Microelectronic Devices and Circuits Prof. Ming C. Wu
[email protected] 511 Sutardja Dai Hall (SDH) Lecture 9: MOSFET (2): Scaling, DC bias 1 NMOS Transistor Capacitances: Saturation Region • Drain no longer connected to channel 2 C = C +C W C = C W GS 3 GC GSO GD GDO Lecture 9: MOSFET (2): Scaling, DC bias 2 1 SPICE Model for NMOS Transistor Typical default values used by SPICE: 2 KP = 50 or 20 µA/V γ = 0 λ = 0 VTO = 1 V 2 µn or µp = 500 or 200 cm /V-s 2ΦF = 0.6 V CGDO = CGSO = CGBO = CJSW = 0 Tox= 100 nm Lecture 9: MOSFET (2): Scaling, DC bias 3 MOS Transistor Scaling • All physical dimensions shrinks by a factor of α • All voltages (including threshold voltage) reduced by α also – Constant field scaling • Drain current: * εox W α " vGS VTN vDS % vDS iD iD = µn $ − − ' = Tox α L α # α α 2α & 2α α * !W $! L $ C • Gate Capacitance: * " * * εox GC CGC = (Cox ) W L = # &# & = Tox α " α %"α % α • Circuit delay in a logic circuit. * * * ΔV CGC ΔV /α τ τ = CGC * = = iD α iD /α α Lecture 9: MOSFET (2): Scaling, DC bias 4 2 MOS Transistor Scaling Scale Factor α (cont.) • Circuit and Power Densities: V i P P* = V * i* = DD D = DD D α α α 2 P* P* P α 2 P = = = extremely important result! A* W *L* W L A ( α)( α) • Power-Delay Product: P τ PDP PDP* P* * € = τ = 2 = 3 α α α • Cutoff Frequency: gm µn € ω = = V −V T C L2 ( GS TN ) GC – fT improves with square of channel length reduction € Lecture 9: MOSFET (2): Scaling, DC bias 5 Impact of Velocity Saturation • At low electric field, electron velocity is proportional to field • At high electric field, the velocity reaches a maximum called saturation velocity, vSAT " CoxW iD = (vGS −VTN )vSAT 2 • The drain current is proportional to (vGS – VTN) rather than its square • There are (many) other corrections to the basic model when the channel become very short – Interested, take EE130 Lecture 9: MOSFET (2): Scaling, DC bias 6 3 NMOSFET in OFF State • We had previously assumed that there is no channel current when vGS < VTN.