MT-020: ADC Architectures I: the Flash Converter
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SSB Exciter Circuits Using a New Beam-Deflection Tube
8/24/2008 7360 Circuits SSB Exciter Circuits Using a New Beam-Deflection Tube Practical Circuit Data for Modulation, Frequency Conversion and Detection BY H. C. VANCE K2FF Extracted from QST March 1960 The new beam deflection tube described here appears to be a bulb-full of versatility, with more applications than were visualized when the tube was under development as an improved type of balanced modulator. This article tells how the 7360 can be put to work in a number of ways in the amateur field, particularly in SSB transmission and reception. A new beam-deflection tube, the RCA-7360, incorporates novel design features which, with suitable circuits, allow it to be used in many kinds of applications with improved performance at frequencies at least as high as 100 megacycles. The tube was originally developed to provide a high degree of stable carrier suppression when used as a balanced modulator in single-sideband service. More than 60 dB of carrier suppression has been obtained with it as a balanced modulator in SSB exciters of both the filter and phasing types. It is of course equally valuable in double-sideband suppressed carrier service. Frequency conversion, product detection, synchronous detection, single-ended to push-pull phase inversion, switching circuits, fader circuits and compressor- expander-limiter circuits are among the many other interesting applications in which the unique properties of this new tube have been found to be valuable. In this article circuits will be described which make use of the 7360 as a balanced modulator, a frequency mixer and a product detector. -
Brookhaven National Laboratory
BROOKHAVEN NATIONAL LABORATORY quarterly Progress Report April 1 - June 30~ 1950 Associated Universities Inc. under contract with the United States Atomic Energy Commission. BROOKHAVEN NATIONAL LABORATORY QUARTERLY PROGRESS REPORT April 1 - June 30, 1950 Associated Universities, Inc~ under contract with the United States Atomic Energy Commission Printed at Upton, New York, for distribution to individuals and organizations associated with the national atomic energy program. July, 1950 7.00 copies FOREWORD This is the second of a series of Quarterly Progress Re ports. While most of the departments have summarized their work or used a form comparable to abstracts, the Chemistry Department has given both abstracts and complete reports on its work. The major part of the progress in the Reactor Science and Engineer ing Department is being presented simultaneously in a separate classified report. iii CONTENTS Foreword • • • iii· Physics Department • 1 Instrumentation and Health Physics Department 15 Accelerator Projeot • • 22 Chemistry Department • 28 Reactor Science and Engineering Department • 91 Biology Department • • 96 Medioal Department • • 107 PHYSICS DEPARTMENT The research progress of the Physics Department is described under five subdivisions: 1) dynamic properties of atomic nuclei, 2) stationary proper ties of nuclei, 3) high energy particle physics, 4) research in other branches of physics carried out with the use of neutrons or other nuclear techniques, and 5) theoretical topics not included under the above headings. Under sub division (1) are included investigations of radioactivity and nuclear reac tions induced by gamma rays, neutrons, and particles accelerated in the cyqlotron or Van de Graaff accelerator. Under (2) are the measurements of nuclear mass and moment. -
Dynamic MOS Sigmoid Array Folding Analog-To-Digital Conversion
182 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 Dynamic MOS Sigmoid Array Folding Analog-to-Digital Conversion Roman Genov and Gert Cauwenberghs Abstract—A dynamic, saturating difference circuit for large-scale parallel folding analog-to-digital conversion is presented. The circuit comprises a subthreshold nMOS transistor source-coupled to a capacitor, implementing a log-domain integrator. The output current is a logistic sigmoidal function of the change in voltage on the gate. Offset and gain of the differential sigmoid are controlled by timing of global clock signals and are independent of transistor mismatch. Folding operation for analog-to-digital conversion is obtained by differentially combining and integrating currents from a bank of sigmoid units. A 128-channel parallel bank of 4-bit Gray-code folding analog-to-digital converters measures 0.75 mm 2 mm in 0.5 m CMOS and delivers 768 Msps at 82-mW power dissipation. Index Terms—Charge-mode comparator, correlated double sampling, diode integrator, folding analog-to-digital converter (ADC), interpolating ADC, sigmoid. I. INTRODUCTION (a) High-performance data conversion can be achieved either by ex- pending power and area to achieve high precision in a single analog architecture or by distributing the architecture over multiple low-reso- lution quantization tasks, each implemented with relatively imprecise analog circuits, and combined in the digital domain. Delta-sigma mod- ulation has proven to be superior in attaining very high precision by distributing the quantization process over time [1]. Both high speed and high resolution can be achieved by distributing the quantization process in space [2]. -
An Experimental Investigation of a Low Distortion Mixer
AN EXPERIMENTAL INVESTIGATION OF A LOW DISTORTION MIXER USING A BEAM-DEFLECTION TUBE A THESIS Presented to the Faculty of the Graduate Division By Guy Herbert Smith, Jr. In Partial. Fulfillment of the Requirements for the Degree Master of Science in Electrical Engineering Georgia Institute of Technology June, I96I "In presenting the dissertation as a partial fulfillment of the requirements for an advanced degree from the Georgia Institute of Technology, I agree that the Library of the Insti tution shall make it available for inspection and circulation in accordance with its regulations governing materials of this type. I agree that permission to copy from, or to publish from, this dissertation may be granted by the professor under whose di rection it was written, or,, in his .absence, by the dean, of the Graduate Division when such copying or publication is solely for scholarly purposes and does not involve potential financial gain. It is understood that any copying from, or publication of, this dissertation which involves potential financial gain will not be allowed without written permission. " /y~ J* AN EXPERIMENTAL INVESTIGATION OF A LOW DISTORTION MIXER USING A BEAM-DEFLECTION TUBE Approved: - \ A . \ h T T - / /) l Date Approved by Chairman: 11 PREFACE This study is an experimental investigation of a low distortion mixer using a beam-deflection tube as the active circuit element. The material herein is limited in its scope in that the investigation covers only one of several basic circuit configurations that are suitable for use with beam-deflection tubes. It is also limited because only one type of beam-deflection tube has been considered. -
Design and IMPLEMENTATION of a Novel Flash Adc for Ultra Wide Band Applications
Design AND IMPLEMENTATION OF a Novel flash adc for ultra wide band applications A Thesis report submitted in partial fulfillment of the requirement for the degree of Doctor of Philosophy In ELECTRONICS AND COMMUNICATION ENGINEERING By GEORGE TOM VARGHESE (Roll no: 511EC102) Under the guidance of Prof. KAMALAKANTA MAHAPATRA 2014 Design AND IMPLEMENTATION OF a Novel flash adc for ultra wide band applications A Thesis report submitted in partial fulfillment of the requirement for the degree of Doctor of Philosophy In ELECTRONICS AND COMMUNICATION ENGINEERING By GEORGE TOM VARGHESE (Roll no: 511EC102) Under the guidance of Prof. KAMALAKANTA MAHAPATRA 2014 Department of Electronics and Communication Engineering National Institute of Technology Rourkela-769008 CERTIFICATE This is to certify that the thesis entitled “Design and Implementation of a Novel Flash ADC for Ultra Wide Band Applications” submitted by Mr. George Tom Varghese in partial fulfillment of the requirements for the award of Doctor of Philosophy Degree in Electronics and Communication Engineering with specialization in “VLSI Design and Embedded Systems” during the session 2011- 2014 at National Institute of Technology, Rourkela is an authentic work carried out by him under my supervision and guidance. To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other University/Institute for the award of any Degree or Diploma. Date: Prof. Kamalakanta Mahapatra Place: Department of Electronics & Communication Engineering National Institute of Technology, Rourkela Dedicated To Chachen, Amma &Achu ACKNOWLEDGEMENTS This project is by far the most significant accomplishment in my life and it would have been impossible without the people who supported me and believed in me. -
A New Miniature Beam-Deflection Tube (7360)
BEAM-DEFLECTION TUBE 267 of the returned electrons are undesired coupling from grid No. 3 to grid No. 1 and variations of input loading of grid No. 1. The degree of influence of grid-No.3 voltage upon cathode current is a good indi- cator of the magnitude of these adverse effects. In conventional NEW MINIATURE A BEAM-DEFLECTION TUBE* pentodes, such as the 6ASG, grid No. 3 has about one-third the con- BY trol over cathode current that it has over plate current. The effect is reduced to about one twentieth in pentagrid converters, which are M B KNIGHT - . designed to return electrons along different paths as much as practical. RCA Electron Tube Division, always away Harrison, N. J. In the beam-deflection tube, the electrons move from the cathode; thus, the major cause of interaction with the control grid Summary—A new method for beam-deflection control of plate current is eliminated. Furthermore, balanced operation of the deflecting elec- has been developed and applied to a tube design that uses beam-deflection trodes minimizes the influence of the deflecting electrode signal voltage control in addition to conventional grid control. The new tube, the 7860, is - a nine-pin miniature type especially suitable for use in modulators, demod- on the electric fleld near the cathode, and tends to neutralize capaci- ulators, and converters. It has an uelectron gun” that comprises a cathode, tance coupling between deflecting electrodes and control grid. An- a control grid, and a screen grid ; a deflection structure that includes two other advantage is that both plates may be used for output signals in grid like deflecting electrodes; and two plates. -
Dictionary of Video and Television Technology Newnes Is an Imprint of Elsevier Science
Dictionary of Video and Television Technology Newnes is an imprint of Elsevier Science. Copyright © 2002, Elsevier Science (USA). All rights reserved. [This page intentionally left blank.] No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher. Recognizing the importance of preserving what has been written, Elsevier Science prints its books on acid-free paper whenever possible. Library of Congress Cataloging-in-Publication Data ISBN: 1-878707-99-X British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library. The publisher offers special discounts on bulk orders of this book. For information, please contact: Manager of Special Sales Elsevier Science 225 Wildwood Avenue Woburn, MA 01801-2041 Tel: 781-904-2500 Fax: 781-904-2620 For information on all Newnes publications available, contact our World Wide Web home page at: http://www.newnespress.com 10 9 8 7 6 5 4 3 2 1 Printed in the United States of America Dictionary of Video and Television Technology Keith Jack Vladimir Tsatsulin An imprint of Elsevier Science Amsterdam Boston London New York Oxford Paris San Diego San Francisco Singapore Sydney Tokyo [This is a blank page.] CONTENTS Preface ............................................................................................................. vii About the Authors ..................................................................................... -
Imans, Dept. Committee an Uate Students V 6•
A BINARY QUANTIZER itITH A RESOLUTION OF ONE PART IN A THOUSAND by JULIAN E. GROSS B.S,. Masusachusetts Institute of Technology 1951 SUBMITTED IN PARTIAL FULFILLMEWT OF THE E~QUIREM~VTS FOR THE DEGREE OF MASTER OF SCIENCE at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY (1951) Signature of Author .. u ofv lev-.-.0 0 . 0. 1 18*5a....1...... a.* . of Elect, Eng. May 18, 1951 Certified by 'I, IAL,~l ~CIIIIII~t~~Y / r' ........ ........ imans, Dept. Committee an uate Students v 6• 4 6 p +"p~`·r i ab Y·? B 5.6 INST. AUG 6 1951) ABSTRACT A BINARY QUATTIZER WITH A RESOLUTION OF ONE PART IN A THOUSAND by JULIAN E. GROSS Submitted for the degree of Master of Science in the Department of Electrical Engineering May 18, 1951. A logical design for a binary quantizer with a resolution of one part in one thousand and a sempling rate of one thousand times per second has been developed. The proposed system is all electronic and may be classified as a 2n/2+1 -step device as contrasted with the more commno n-step and 2n-step quantizers. The design developed employs a voltage comparator to transform the voltage to be coded into a time interval. A certain number of fixed time intervals are subtracted from the main interval and the remainder is essentially multiplied by 32. The intervals subtracted and the multi- plied remainder are used to activate gate circuits which gate pulses into a binary counter. In evolving the design for a circuit to meet the specifications chosen, emphasis was placed on the development of those parts of the circuit which had not been sufficiently developed for application to this problem. -
Charge to Mass of Electron
Nobel Prize Exp. 1, e/m of Electron 1 THE DISCOVERY OF THE ELECTRON THE J. J. THOMSON EXPERIMENT TABLE OF CONTENTS Historical Background 2 Pre-Lab Home Work 9 Experiment 1 11 Experiment 2 15 Nobel Prize Exp. 1, e/m of Electron 2 THE DISCOVERY OF THE ELECTRON NOTE: The following text was taken from "From Alchemy To Quarks" by Sheldon L. Glashow, pp. 423-429. HISTORICAL BACKGROUND Roentgen set out to study cathode rays but was rewarded, on or about Christmas 1895, with the discovery of X-rays. Becquerel searched for a suspected but nonexistent link between Roentgen's rays and phosphorescence. Instead, he found something totally unexpected: radioactivity. In January 1896, Ernest Rutherford, a young scientist who was working at the renowned Cavendish Laboratory in Cambridge, England, wrote to his fiancée: The Professor [his advisor, J.J. Thomson] has been very busy lately over the new method of photography discovered by Professor Roentgen. [Thomson] is trying to find out the real cause and nature of the waves, and the great object is to find the theory of matter before anyone else, for nearly every Professor in Europe is now on the warpath. The professor and his assistant would find the parts of the atom. Thomson was about to discover the electron. Sixteen years later, Rutherford would discover the nucleus of the atom. The first of the Nobel prizes was awarded to Roentgen for his discovery of X-rays. Two years later, the Prize was split between Becquerel and the Curies. Joseph John Thomson, J.J., as he was universally known, was director of the Cavendish Laboratories at Cambridge University from 1884 to 1918. -
Data Converter Architectures
DATA CONVERTER ARCHITECTURES ANALOG-DIGITAL CONVERSION 1. Data Converter History 2. Fundamentals of Sampled Data Systems 3. Data Converter Architectures 3.1 DAC Architectures 3.2 ADC Architectures 3.3 Sigma-Delta Converters 4. Data Converter Process Technology 5. Testing Data Converters 6. Interfacing to Data Converters 7. Data Converter Support Circuits 8. Data Converter Applications 9. Hardware Design Techniques I. Index ANALOG-DIGITAL CONVERSION DATA CONVERTER ARCHITECTURES 3.1 DAC ARCHITECTURES CHAPTER 3 DATA CONVERTER ARCHITECTURES SECTION 3.1: DAC ARCHITECTURES James Bryant, Walt Kester Introduction Those unfamiliar with DACs regard them simply as devices with digital input and analog output. But the analog output depends on the presence of that analog input known as the reference, and the accuracy of the reference is almost always the limiting factor on the absolute accuracy of a DAC. We shall consider the various architectures of DACs, and the forms which the reference may take, later in this section. Some DACs use external references (see Figure 3.1) and have a reference input terminal, while others have an output from an internal reference. The simplest DACs, of course, have neither—the reference is on the DAC chip and has no external connections. (ANALOG) REFERENCE V DD INPUT VREF DIGITAL INPUT DAC ANALOG OUTPUT V SS GROUND (MAY BE INTERNALLY CONNECTED TO VSS) Figure 3.1: Basic DAC with External Reference If a DAC has an internal reference, the overall accuracy of the DAC is specified when using that reference. If such a DAC is used with a perfectly accurate external reference, its absolute accuracy may actually be worse than when it is operated with its own internal reference. -
Data Converter Architectures
DATA CONVERTER ARCHITECTURES ANALOG-DIGITAL CONVERSION 1. Data Converter History 2. Fundamentals of Sampled Data Systems 3. Data Converter Architectures 3.1 DAC Architectures 3.2 ADC Architectures 3.3 Sigma-Delta Converters 4. Data Converter Process Technology 5. Testing Data Converters 6. Interfacing to Data Converters 7. Data Converter Support Circuits 8. Data Converter Applications 9. Hardware Design Techniques I. Index ANALOG-DIGITAL CONVERSION DATA CONVERTER ARCHITECTURES 3.1 DAC ARCHITECTURES CHAPTER 3 DATA CONVERTER ARCHITECTURES SECTION 3.1: DAC ARCHITECTURES James Bryant, Walt Kester Introduction Those unfamiliar with DACs regard them simply as devices with digital input and analog output. But the analog output depends on the presence of that analog input known as the reference, and the accuracy of the reference is almost always the limiting factor on the absolute accuracy of a DAC. We shall consider the various architectures of DACs, and the forms which the reference may take, later in this section. Some DACs use external references (see Figure 3.1) and have a reference input terminal, while others have an output from an internal reference. The simplest DACs, of course, have neither—the reference is on the DAC chip and has no external connections. (ANALOG) REFERENCE V DD INPUT VREF DIGITAL INPUT DAC ANALOG OUTPUT V SS GROUND (MAY BE INTERNALLY CONNECTED TO VSS) Figure 3.1: Basic DAC with External Reference If a DAC has an internal reference, the overall accuracy of the DAC is specified when using that reference. If such a DAC is used with a perfectly accurate external reference, its absolute accuracy may actually be worse than when it is operated with its own internal reference. -
Research Background of the Project
CORE Metadata, citation and similar papers at core.ac.uk Provided by UTHM Institutional Repository i 4-bits 0.25 µm CMOS LOW POWER FLASH ADC RAYED AWAD ABBAS AL-SAHLANEE A thesis report submitted in partial fulfilment of the requirement for the award of the Degree of Master of Electrical Engineering Faculty of Electrical and Electronic Engineering Universiti Tun Hussein Onn Malaysia January, 2015 v ABSTRACT The analogue to digital converters are the key components in modern electronic systems. Signal processing is very important in many of the system on-a-chip applications. Analogue to digital converters (ADCs) are a mixed signal device that converts analogue signals which are real world signals to digital signals for processing the information. As the digital signal processing industry grows the ADC design with new techniques and methods are extensively sought after. This increases the requirements on ADC design concerning for high speed, low power and small area. A flash ADC is the best solution, not only for its fast data conversion rate but also it becomes part of other types of ADC. However main problem with a flash ADC is its power consumption, which increases in number of bits. In this project a 4- bits flash ADC is designed with a 1.5V power supply and 1.5 GHz clock using 0.25 µm CMOS technology. The software used for this ADC design is Tanner EDA’s S- EditTM and T-SpiceTM which is utilized to simulate the three blocks of flash ADC with input frequency of 250 MHz. The ADC is successfully designed with a power consumption of 5.18 mW.