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High Speed Flash Analog to Digital Converters

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High Speed Flash Analog to Digital Converters ECE 551, Analog Integrated Circuit Design, High Speed Flash ADCs, Dec 2005 1 High Speed Flash Analog to Digital Converters Alireza Mahmoodi Different methods have been introduced in order to achieve Abstract — Flash analog-to-digital converters, also known as higher speed with lower power consumption. Next sections parallel ADCs, are the fastest way to convert an analog signal to will discuss some of these methods. At the end, simulation a digital signal. They are suitable for high speed applications. results will be presented. However, flash converters consume a lot of power, have relatively low resolution, and can be quite expensive. In this article we are going to discuss the methods to increase the II. TIMING ISSUES performance of Flash ADCs. Clock generation and distribution is an important issue in high speed circuits. Since an uncertainty in clock (jitter) Index Terms — Flash, ADC, Analog-to-digital conversion. directly translates into reduction of the resolution of the system, Jitter has to be kept as small as possible [1]. Therefore I. INTRODUCTION an on chip low-jitter sampling clock source internally should ODAY’S high rate signal processing in various be used. And The clock signal is distributed by means of an T applications such as the read channels of hard disks, H-tree structure [1]. Gigabit Ethernet or optical communications rely on digital signal processing circuitry. These circuits require high speed III. REDUCING MISMATCH BY DIGITALLY AVERAGIN ADCs to provide the interface between the analog and digital Designing the comparator is the most difficult part. And all parts of the system. Flash ADCs are so faster than the other types of ADCs. For example a Flash ADCs can achieve 4GS/s of the devices, especially in the first stage of the comparators with 6 bit resolution in a 0.13µm standard CMOS technology should be sized accordingly to reduce mismatch in the input of [1,2]. The main drawback of Flash ADC is its power the comparators. Device mismatch, because of process consumption. In this report we will discuss different issues in variation, causes an input offset in comparators. First stage of designing a Flash ADC and find out how to improve its every comparator is made up of a differential amplifier. As performance. figure (2a) shows Variation in W/L of each transistor causes a In a Flash ADC a resistive divider with 2N resistors deviation of the electrical parameters such as Vth and the provides 2N-1 reference voltage. For an "N" bit converter, the other parameters. Therefore the output of differential amplifier circuit employs 2N-1 comparators. The comparator will would have an offset. This offset limits the resolution of Flash compare the input signal to a reference level and will calculate ADCs and causes IDL error. The easiest way to mitigate this the output bit [3]. The output of the comparators is known as issue is to increase W/L .It means decreasing the speed of thermometer code. The thermometer code is then decoded to comparator, and consuming more area and power. the appropriate digital output code. Figure (1) shows the structure of a flash ADC. Figure 2. Illustration of the deviation in CMOS parameters. Figure 1. Structure of a Flash ADC Another way of decreasing this effect is by averaging in digital domain. In this method, larger number of comparators as would be necessary for the aspired resolution of the flash ECE 551, Analog Integrated Circuit Design, High Speed Flash ADCs, Dec 2005 2 ADC will be used [1]. The statistical averaging of the In this method output of the comparator is no longer comparator results is then performed in the digital domain. determined by its decision alone, but, through the averaging This architecture does not reduce the total area of the resistors is also influenced by its adjacent comparators. comparator bench or reduce its power consumption, but that Consequently the input offset of comparators will be reduced higher sampling speeds can be realized with smaller sized by a factor of three. This method has been used in most of the comparators. Figure (2b) shows the effect of this method. flash ADCs. The main drawback with this method is that we The comparator schematic for this method is depicted in need over-range comparators to maintain the linearity at the figure (3). It consists of a preamplifier, a transconductance edges. amplifier a latch and a memory cell. V. CAPACITIVE INTERPOLATION Another strategy of reducing the mismatch effect is capacitive interpolation.[5] As figure(5) shows this method uses a capacitive averaging network between the outputs of adjacent amplifiers. Using SC circuits the difference between the input and the threshold level is determined. To achieve high resolution, in the next stage one comparator will be added between every two comparators. And the input of this comparator is determined from the result of the averaging between the two comparators in the last stage. The main Figure 3. Structure of the comparator in Flash ADC. advantage of this method is that it doesn’t need any extra comparators or any static averaging termination. But still it is Output of the comparator bank is converted into a binary complex. Capacitive interpolation combined with distributed code. By averaging in digital domain, redundant bits will be front-end sample-and-hold can increase the performance of deleted. Table 1 shows performance of this ADC.[1] this method [5]. Although, this ADC works at high speed, this method is not suitable since it uses a lot of power in its digital part. Table 1. Measured Performance of ADC IV. RESISTIVE AVERAGING Figure 5. Comparator with capacitive interpolation Averaging is a well known method to reduce the input offset of the comparators. Resistive averaging uses some VI. TIME INTERLEAVING [2] resistors between the output of adjacent amplifiers [4]. Figure Another way to realize higher sampling rate with respect of (4) shows the structure of comparator with resistive averaging. low power consumption is to use two identical flash ADC operating in a time interleaved way [6]. Each flash ADC contains several comparators and requires two clock cycles to complete the conversion. Figure (6) shows block diagram of this ADC. Using two converters with three bit resolution, the output would have 6 bit resolution. In the first clock three MSBs of output are determined. During the second clock period input signal will be compared with the new threshold levels to determine the next three bits. Since the clock frequency is twice as input rate, this method is not suitable for at ultra high frequencies. Figure 4. Resistive averaging in the comparator ECE 551, Analog Integrated Circuit Design, High Speed Flash ADCs, Dec 2005 3 Figure 6. ADC block schematic So every two clocks each comparator provides 6 bits. This structure has the latency of one clock. Switched capacitor and multiplexers are used to perform the function of sample and hold, subtraction and comparison. Table (2) shows the performance of this ADC. Process 0.13 µm Figure 8. Block diagram of ADC made up of MCML. Resolution 6bit Sampling Rate 1GS/s Table 3 shows the post-simulation results of MCML Flash Power supply 1.5 v Power Dissipation 11mW ADC. Also the simulation shows that DNL max and INL max INL <0.5 LSB are 0.13-LSB and 0.27-LSB, when standard deviation of IDL <1 LSB SFDR@f=200MHZ 38dBc input offset is 0.5-LSB. Results show that this method Area 2 0.075 mm dissipates much power and area. Table 2. Performance of a time interleaved ADC VII. USING MCML CIRCUITS Using MCML circuits can improve performance of Flash ADCs. [7] Figure (7) show the basic structure of a MCML circuit and a MCML latch. The main motivation of using MCML is that its switching speed is independent of the supply voltage as opposed to CMOS circuit. The second motivation is Table.3 simulation results for MCML Flash ADC its low dissipation at high frequency ranges. Since MCML dissipate static power, it is independent of operating VIII. USING DIFFERENTIAL AMPLIFIER frequency. Another way to reduce the input offset of comparator is to use differential amplifier to average the input offset by each of pairs [8]. The structure of the proposed ADC is shown in figure (9). This structure also uses resistor averaging. Figure 7. (a) MCML circuit (b) MCML latch structure Figure (8) shows general block diagram of this ADC. Also MCML circuit is used in comparators and encoders. The Figure 9. Architecture of ADC using differential amp. resistive ladder provides a reference voltage for 83 preamplifiers where 20 of them are used to provide averaging Using differential signaling also has other advantages. It requirements. 63 MCML comparators are used in the next will ensure the immunity of the system to the common mode stage. The output of the comparators are sent to MCML noise. Since all of the tail currents are reused in each phase, encoders to be converted to binary codes. and none of the current sources are turned off. Supply noise due to switching is minimized. Comparator consists of 4 stages. Figure (10) shows the first stage in comparator which ECE 551, Analog Integrated Circuit Design, High Speed Flash ADCs, Dec 2005 4 is a differential amplifier. The next three stages are latching IX. SIMULATION RESULTS stages. The simulation was done in two parts; in the first part, the goal was to evaluate the effect of W/L variation on the input offset of the comparator. First stage of the comparator in figure (3) with PMOS loads was used in this part. Figure (13) shows the simulation results.
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