DOCSLIB.ORG

3T Gain Cell Embedded Dram Based on Gate Diffusion Technique (Gdi) in Low Power Applications

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
3T Gain Cell Embedded Dram Based on Gate Diffusion Technique (Gdi) in Low Power Applications International Journal of Pure and Applied Mathematics Volume 118 No. 20 2018, 4915-4921 ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu Special Issue ijpam.eu 3T GAIN CELL EMBEDDED DRAM BASED ON GATE DIFFUSION TECHNIQUE (GDI) IN LOW POWER APPLICATIONS P.SUJITHA1, M.DEIVAKANI2 1 PG Scholar, (dept of ECE,PSNA CET, DINDIGUL E-mail id-sujitha020594@gmail com) 2 Assistant professor, (dept of ECE, PSNA CET,DINDIGUL) ABSTRACT: main memory. There are some other types of DRAM in the industry. They are, Recently, the Gain cell Embedded DRAM plays a vital role than SRAM. So, GC-e DRAM which has some 1. Conventional DRAM features that includes high balance, low out flow, low 2. Fast Page Mode DRAM (FPM DRAM) voltage and 2 fixated conclusion. The time permits 3. Enhanced DRAM (EDRAM) periodic power hungry renew cycles. The drawbacks to 4. Extended Data out DRAM (EDO DRAM) be strengthen at ascend inventions, when expanding sub 5. Burst Extended Data out DRAM (BEDO DRAM) threshold leakage currentsand further it is minimized. A 6. Synchronous DRAM (SDRAM) 4T GC-e DRAM bit cell produces the feedback which is 7. Enhanced Synchronous DRAM (ES DRAM) internally contracted to improve the data retention 8. Double Data- Rate DRAM (DDR DRAM) time.The retention time of 3TGC-eDRAM cell is 9. Synchronous Link DRAM (SL DRAM) significantly more than that of 4T Gain cell and 3T gain 10. Rambus DRAM (RDRAM) cell. Retention time tends to decrease as the supply 11. Embedded DRAM (Em DRAM) voltage increases. To improve the performance and data 12. Direct Rambus DRAM (DR DRAM) retention time a new technique named GDI (Gate 13. Video RAM (VRAM). Diffusion Input Technique). Some of them were below described as, Keywords: Embedded DRAM, Single event upset (SEU), Gate Diffusion Input Technique (GDI), data retention A. CONVENTIONAL DRAM: time, Error Correction Codes (ECC), Low Power Applications. In DRAM industry, The Column Address and the Row Address were first send to the Memory Array by using the I.INTRODUCTION earlier method of standard memory address. In Conventional DRAM, Multiplexing canbe achieved. TheMost energetic and efficient method of the RAM Memory is that the Dynamic Random Access B.FAST PAGE MODE DRAM :( FPM DRAM) Memory(DRAM).The Binary data storage technique is done by reducing a Single transistor-Capacitor. The Leak aging or The Conventional DRAM is slower than FPM DRAM. This emission method in this DRAM cell which needs the FPM DRAM needs both the row address and the column capacitor to simulate the requirement of the Data retention address in the same page address. It is used to improve time time which is shortly indicated by the word and reduce power dissipation. ‘DYNAMIC’.The DRAM cell was first materialised in 1970 C.ENHANCED DRAM :( EDRAM) with some capacitor of 1kb size. As Astounding result in the DRAM Capacity, the memory cell area been reduced to 60 It is the combination of both SRAM and SRAM. It supports percent at the same time the die size has increased by 50 speed and performance of SRAM and also the density and percent. the cost of DRAM. TYPES OF DRAM: F.SYNCHRONOUS DRAM: (SDRAM) DRAM plays a vital role in the main memory which reserves The System clock of the processor controls the DRAM data and programs.90percent of DRAM were included in architectures. 4915 International Journal of Pure and Applied Mathematics Special Issue J.RAMBUS DRAM :( RDRAM) A cost-effective gain cell for memory embedded in logic LSIs. The new cell consists of two conventional bulk Packets were transported within both command and address transistors and one MOS capacitor. It can be fabricated using by the Rambus DRAM which acts as the bidirectional link. the pure logic process with a few additional process steps.[7]. The fabrication cost of this cell is lower than that L. EMBEDDED DRAM (EmDRAM): of DRAM or SRAM at a memory density in the 1-100Mbit range. To enhance the System performance in System on chip (SOC), the indispensable approach. The most advantage of To achieve power optimization and trade-offs, a single edge Embedded DRAM is high bandwidth, lower power triggered and double edge triggered flip flops were used by consumption, and customized memory sizes and higher the new GDI technique.[16] It is also used to calculate the consumption. aspect ratio and the frequency. This technique is to analyse the few delay [11] of the circuit when compared with the II.RELATED WORKS some other CMOS configuration. A replica technique for automatically tracking the retention time of a gain cell-embedded dynamic-random- This Gate Clocking Dissipation Input Technique [17] access-memory macro cell according to process variations consists of EX-OR &AND gates were included in the and operating statistics, thereby reducing the data retention circuit. It decreases the power dissipation.The Design of the power of the array.[2] A 2-kb array was designed and digital combinatorial circuit with the GDI technique fabricated in a mature 0.18-μm CMOS process, decreases power consumption, propagation delay and area appropriate for integration in ultralow power applications, [13]. This GDI cell is implemented with some complex logic such as biomedical sensors.Measurements show efficient function and also it improves the power characteristics of the retention time tracking across arrange of supply voltages circuit. and access statistics, lowering the refresh frequency by more than 5×, as compared with traditional III.PROPOSED METHOD worstcasedesign. Recently, the Gain cell Embedded DRAM plays a vital role A boosted 3Tgain cell utilizes Read Word-line (RWL) than SRAM. So, GC-e DRAM which has some features that preferential boosting to increase read margin and improve includes high balance, low out flow, low voltage and 2 data retention time. Read speedis enhanced with a hybrid fixated conclusion. The time permits periodic power hungry current/voltage sense amplifier that allowsthe Read Bit-line renew cycles. The drawbacks to be strengthen at ascend (RBL) to remain close to VDD.[3]The proposedboosted 3T inventions, when expanding sub threshold leakage gain cell can provide a stronger coupling effect withonly currentsand further it is minimized. A 4T GC-e DRAM bit three transistors, increasing data retention time, cell produces the feedback which is internally contracted to enhancingthe RBL margin and improving read improve the data retention time. The retention time of performance[3]. 3TGC-eDRAM cell is significantly more than that of 4T Gain cell and 3T gain cell. Retention time tends to decrease An asymmetric 2T gain cell utilizesa half-swing write bit- as the supply voltage increases. To improve the performance line (WBL) scheme is adopted to improve the WBLspeed and data retention time a new technique named GDI (Gate and reduce its power dissipation duringwrite-back operation Diffusion Input Technique). with no effect on retention time.[4] A stepped right word- line (WWL) driver reduces the current drawn fromthe W R boosted high and low supplies. A 192 kb eDRAM test chip B with 512 cells-per-BL implemented in a 65 nm low-power W W (LP) CMOS process shows a random cycle frequency and L B L latencyof 667 MHz and 1.65 ns, respectively, at 1.1 V and B S 85 C[4]. Themeasured refresh period at a bit yield condition N P was 110swhich is comparable to that of recently published L S N 1T1C eDRAMdesigns. P G R D C A 5.42nW/ kB Retention Power Logic-Compatible F S Embedded DRAM with 2T Dual- Vt Gain Cell for Low R N Power Sensing Applications. A logic-compatible 2T dual-Vt embedded DRAM (e DRAM) is proposed for ultra-small W sensing systems to achieve 8× longer retention time, 5× L lower refresh power and reduced area compared with the lowest power e DRAM previously reported.[5] With an area-efficient single inverter sensing scheme designed for FIG 1: STRUCTURE OF4T GC-e DRAM R/W speed compatibility with ultralow power processors, array efficiency is maintained for memories as small as 2kb The method presented that the data ‘0’ is to be achieved to and for as few as 32 bits per bit line. improve the bit cell’s retention time. The Proposed circuit can be identified using some buffer nodes like (BN, SN).SN 4916 International Journal of Pure and Applied Mathematics Special Issue is linked to the feedback device (PF) which suites to MITIGATION TECHNIQUES: discharge (BN) according to the data. The concluded 4T bit cell is constructed separately with (VT) Sub-threshold I. Triple Modular Redundancy(TMR) voltage. It is fully compatible with the normal inverter. The II. Dual Modular Redundancy(DMR) 4T cell is resolved in a same manner as like normal 2T cell. III. Multiple redundancies with voting IV. EDAC(Error Detection And Correction coding) While write operation is in process, the WWL is connected to PW and PB nodes which is pressed to a negative voltage It can reduce up to the accepted level of some radiation to discharge SN. While read operation is in process to pre- effects such as Total Ionization Dose(TID) and Single event discharge RBL to ground and charge RWL to VDD. To latch up(SEL).But they do not completely discard upset bring efficient area and power, a sense inverter is used on effects such as SEU’s & SET.In Low volume Production the read path. Sometimes, other sense amplifiers were used very few techniques were adopted and also, it is very to get improved readperformance. The method presented expensive. The threshold LET values of ‘SOI’ is nearly that the data ‘0’ is to be achieved to improve the bit cell’s same as bulk/epi process.
Load more

Recommended publications
  • Nanotechnology ? Nram (Nano Random Access
    International Journal Of Engineering Research and Technology (IJERT) IFET-2014 Conference Proceedings INTERFACE ECE T14 INTRACT – INNOVATE - INSPIRE NANOTECHNOLOGY – NRAM (NANO RANDOM ACCESS MEMORY) RANJITHA. T, SANDHYA. R GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE 13. containing elements, nanotubes, are so small, NRAM technology will Abstract— NRAM (Nano Random Access Memory), is one of achieve very high memory densities: at least 10-100 times our current the important applications of nanotechnology. This paper has best. NRAM will operate electromechanically rather than just been prepared to cull out answers for the following crucial electrically, setting it apart from other memory technologies as a questions: nonvolatile form of memory, meaning data will be retained even What is NRAM? when the power is turned off. The creators of the technology claim it What is the need of it? has the advantages of all the best memory technologies with none of How can it be made possible? the disadvantages, setting it up to be the universal medium for What is the principle and technology involved in NRAM? memory in the future. What are the advantages and features of NRAM? The world is longing for all the things it can use within its TECHNOLOGY palm. As a result nanotechnology is taking its head in the world. Nantero's technology is based on a well-known effect in carbon Much of the electronic gadgets are reduced in size and increased nanotubes where crossed nanotubes on a flat surface can either be in efficiency by the nanotechnology. The memory storage devices touching or slightly separated in the vertical direction (normal to the are somewhat large in size due to the materials used for their substrate) due to Van der Waal's interactions.
    [Show full text]
  • Solid State Drives Data Reliability and Lifetime
    Solid State Drives Data Reliability and Lifetime White Paper Alan R. Olson & Denis J. Langlois April 7, 2008 Abstract The explosion of flash memory technology has dramatically increased storage capacity and decreased the cost of non-volatile semiconductor memory. The technology has fueled the proliferation of USB flash drives and is now poised to replace magnetic hard disks in some applications. A solid state drive (SSD) is a non-volatile memory system that emulates a magnetic hard disk drive (HDD). SSDs do not contain any moving parts, however, and depend on flash memory chips to store data. With proper design, an SSD is able to provide high data transfer rates, low access time, improved tolerance to shock and vibration, and reduced power consumption. For some applications, the improved performance and durability outweigh the higher cost of an SSD relative to an HDD. Using flash memory as a hard disk replacement is not without challenges. The nano-scale of the memory cell is pushing the limits of semiconductor physics. Extremely thin insulating glass layers are necessary for proper operation of the memory cells. These layers are subjected to stressful temperatures and voltages, and their insulating properties deteriorate over time. Quite simply, flash memory can wear out. Fortunately, the wear-out physics are well understood and data management strategies are used to compensate for the limited lifetime of flash memory. Floating Gate Flash Memory Cells Flash memory was invented by Dr. Fujio Masuoka while working for Toshiba in 1984. The name "flash" was suggested because the process of erasing the memory contents reminded him of the flash of a camera.
    [Show full text]
  • Embedded DRAM
    Embedded DRAM Raviprasad Kuloor Semiconductor Research and Development Centre, Bangalore IBM Systems and Technology Group DRAM Topics Introduction to memory DRAM basics and bitcell array eDRAM operational details (case study) Noise concerns Wordline driver (WLDRV) and level translators (LT) Challenges in eDRAM Understanding Timing diagram – An example References Slide 1 Acknowledgement • John Barth, IBM SRDC for most of the slides content • Madabusi Govindarajan • Subramanian S. Iyer • Many Others Slide 2 Topics Introduction to memory DRAM basics and bitcell array eDRAM operational details (case study) Noise concerns Wordline driver (WLDRV) and level translators (LT) Challenges in eDRAM Understanding Timing diagram – An example Slide 3 Memory Classification revisited Slide 4 Motivation for a memory hierarchy – infinite memory Memory store Processor Infinitely fast Infinitely large Cycles per Instruction Number of processor clock cycles (CPI) = required per instruction CPI[ ∞ cache] Finite memory speed Memory store Processor Finite speed Infinite size CPI = CPI[∞ cache] + FCP Finite cache penalty Locality of reference – spatial and temporal Temporal If you access something now you’ll need it again soon e.g: Loops Spatial If you accessed something you’ll also need its neighbor e.g: Arrays Exploit this to divide memory into hierarchy Hit L2 L1 (Slow) Processor Miss (Fast) Hit Register Cache size impacts cycles-per-instruction Access rate reduces Slower memory is sufficient Cache size impacts cycles-per-instruction For a 5GHz
    [Show full text]
  • A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, and Chris H
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 6, JUNE 2011 1495 A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, and Chris H. Kim, Senior Member, IEEE Abstract—Circuit techniques for enabling a sub-0.9 V logic-com- for achieving low static power and high operating speed. patible embedded DRAM (eDRAM) are presented. A boosted 3T SRAMs have been the embedded memory of choice due to gain cell utilizes Read Word-line (RWL) preferential boosting to their logic compatibility and fast access time. Recently, em- increase read margin and improve data retention time. Read speed is enhanced with a hybrid current/voltage sense amplifier that al- bedded DRAMs (eDRAMs) have been gaining popularity in lows the Read Bit-line (RBL) to remain close to VDD. A regu- the research community due to features such as small cell size, lated bit-line write scheme for driving the Write Bit-line (WBL) is low cell leakage, and non-ratioed circuit operation. There have equipped with a steady-state storage node voltage monitor to over- been a number of successful eDRAM designs based on tradi- come the data ‘1’ write disturbance problem of the PMOS gain cell without introducing another boosted supply for the Write Word- tional 1T1C DRAM cells as well as logic-compatible gain cells line (WWL) over-drive. An adaptive and die-to-die adjustable read [2]–[9]. 1T1C cells are denser than gain cells, but at the cost of a reference bias generator is proposed to cope with PVT variations.
    [Show full text]
  • SRAM Edram DRAM
    Technology Challenges and Directions of SRAM, DRAM, and eDRAM Cell Scaling in Sub- 20nm Generations Jai-hoon Sim SK hynix, Icheon, Korea Outline 1. Nobody is perfect: Main memory & cache memory in the dilemma in sub-20nm era. 2. SRAM Scaling: Diet or Die. 6T SRAM cell scaling crisis & RDF problem. 3. DRAM Scaling: Divide and Rule. Unfinished 1T1C DRAM cell scaling and its technical direction. 4. eDRAM Story: Float like a DRAM & sting like a SRAM. Does logic based DRAM process work? 5. All for one. Reshaping DRAM with logic technology elements. 6. Conclusion. 2 Memory Hierarchy L1$ L2$ SRAM Higher Speed (< few nS) Working L3$ Better Endurance eDRAM Memory (>1x1016 cycles) Access Speed Access Stt-RAM Main Memory DRAM PcRAM ReRAM Lower Speed Bigger Size Storage Class Memory NAND Density 3 Technologies for Cache & Main Memories SRAM • 6T cell. • Non-destructive read. • Performance driven process Speed technology. eDRAM • Always very fast. • 1T-1C cell. • Destructive read and Write-back needed. • Leakage-Performance compromised process technology. Standby • Smaller than SRAM and faster than Density Power DRAM. DRAM • 1T-1C cell. • Destructive read and Write-back needed. • Leakage control driven process technology. • Not always fast. • Smallest cell and lowest cost per bit. 4 eDRAM Concept: Performance Gap Filler SRAM 20-30X Cell Size Cell eDRAM DRAM 50-100X Random Access Speed • Is there any high density & high speed memory solution that could be 100% integrated into logic SoC? 5 6T-SRAM Cell Operation VDD WL WL DVBL PU Read PG SN SN WL Icell PD BL VSS BL V SN BL BL DD SN PD Read Margin: Write PG PG V Write Margin: SS PU Time 6 DRAM’s Charge Sharing DVBL VS VBL Charge Sharing Write-back VPP WL CS CBL V BL DD 1 SN C V C V C C V S DD B 2 DD S B BL 1/2VDD Initial Charge After Charge Sharing DVBL T d 1 1 V BL SS DVBL VBL VBL VDD 1 CB / CS 2 VBBW Time 1 1 I t L RET if cell leakage included Cell select DVBL VDD 1 CB / CS 2 CS 7 DRAM Scalability Metrics BL Cell WL CS • Cell CS.
    [Show full text]
  • Hereby the Screen Stands in For, and Thereby Occludes, the Deeper Workings of the Computer Itself
    John Warnock and an IDI graphical display unit, University of Utah, 1968. Courtesy Salt Lake City Deseret News . 24 doi:10.1162/GREY_a_00233 Downloaded from http://www.mitpressjournals.org/doi/pdf/10.1162/GREY_a_00233 by guest on 27 September 2021 The Random-Access Image: Memory and the History of the Computer Screen JACOB GABOURY A memory is a means for displacing in time various events which depend upon the same information. —J. Presper Eckert Jr. 1 When we speak of graphics, we think of images. Be it the windowed interface of a personal computer, the tactile swipe of icons across a mobile device, or the surreal effects of computer-enhanced film and video games—all are graphics. Understandably, then, computer graphics are most often understood as the images displayed on a computer screen. This pairing of the image and the screen is so natural that we rarely theorize the screen as a medium itself, one with a heterogeneous history that develops in parallel with other visual and computa - tional forms. 2 What then, of the screen? To be sure, the computer screen follows in the tradition of the visual frame that delimits, contains, and produces the image. 3 It is also the skin of the interface that allows us to engage with, augment, and relate to technical things. 4 But the computer screen was also a cathode ray tube (CRT) phosphorescing in response to an electron beam, modified by a grid of randomly accessible memory that stores, maps, and transforms thousands of bits in real time. The screen is not simply an enduring technique or evocative metaphor; it is a hardware object whose transformations have shaped the ma - terial conditions of our visual culture.
    [Show full text]
  • Design and Comparative Analysis of Low Power Dynamic Random Access Memory Array Strucyure
    International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 04, April-2015 Design and Comparative Analysis of Low Power Dynamic Random Access Memory Array Strucyure Mr. K. Gavaskar Mr. E. Kathikeyan, Ms. S. Rohini, Assistant professor/ECE, Mr. S. Kavinkumar Kongu Engineering College UG scholar/ECE, Erode, India Kongu Engineering College Erode, India Abstract- Memory plays an essential role in the design of structure is simplicity [8] and it is used in high densities. electronic systems where storage of data is required. In this DRAM is used in main memories in personal computers paper comparative analysis of different DRAM (Dynamic and in mainframes [7]. Random Access Memory) cell based memory array structure In modern day processor power dissipation plays a major has been carried out in nanometer scale memories. Modern advanced processor use DRAM cells for chip and program role because of the miniaturization of the chip memory. But the major drawback of DRAM is the power design. So this stack technique can be used in future for dissipation. The major contribution of power dissipation in reducing the power consumption. Further enhancement can DRAM is off-state leakage current. Also the improvement of also be made in the design in future to reduce the delay, power efficiency is difficult in DRAM cells. This paper because stacking of transistors increases delay and this investigates the power dissipation analysis in DRAM cells. DRAM cell can be used effectively. Since the cost and size Here 1T1C dram cell, 3T dram cell, 4T dram cell has been of DRAM cells are less when compared to SRAM cells and designed using TANNER EDA Tool.
    [Show full text]
  • On the Scaling of Electronic Charge-Storing Memory Down to the Size of Molecules
    On the Scaling of Electronic Charge-Storing Memory Down to the Size of Molecules Jacob S. Burnim November 2001 MP 01W0000319 MII TRE McLean, Virginia Submitted to the 2001-02 Intel Science Talent Search Contest On the Scaling of Electronic Charge-Storing Memory Down to the Size of Molecules Jacob S. Burnim November 2001 MP 01W0000319 Sponsor MITRE MSR Program Project No. 51MSR89G Dept. W062 Approved for public release; distribution unlimited. Copyright © 2001 by The MITRE Corporation. All rights reserved. SUMMARY This investigation quantitatively explores the possibility of shrinking electronic, charge-storing, random access memory to the molecular-scale. The results suggest that quantum effects may hinder the operation of electronic memory on such small scales, but this effect is not pronounced enough to prevent its functioning. Thus, it should be possible to build and operate such memory at densities 10,000 to 100,000 times greater than present-day memory. ABSTRACT This paper presents an analysis of the performance impact of scaling present-day micrometer-scale, charge-storing random-access memory (RAM) down to the scale of proposed molecular electronic memory. As a part of this analysis, the likely performance is determined for arrays of molecular-scale memory 10,000 to 100,000 times denser than present-day memory. A combination of classical and quantum mechanical methods are employed to calculate the properties of nanometer-scale devices and memory systems. These calculations suggest that quantum mechanics and other small-scale effects should decrease the capacitance and increase the resistance of molecular-scale circuit components. However, these trends are not pronounced enough to prevent the operation of charge-storing memory on that scale.
    [Show full text]
  • CSCI 4717/5717 Computer Architecture Basic Organization
    Basic Organization CSCI 4717/5717 Memory Cell Operation Computer Architecture • Represent two stable/semi-stable states representing 1 and 0 Topic: Internal Memory Details • Capable of being written to at least once • Capable of being read multiple times Reading: Stallings, Sections 5.1 & 5.3 CSCI 4717 – Computer Architecture Memory Details – Page 1 of 34 CSCI 4717 – Computer Architecture Memory Details – Page 2 of 34 Random Access Memory Semiconductor Memory Types • Random Access Memory (RAM) • Misnomer (Last week we learned that the term • Read Only Memory (ROM) Random Access Memory refers to accessing • Programmable Read Only Memory (PROM) individual memory locations directly by address) • Eraseable Programmable Read Only Memory • RAM allows reading and writing (electrically) of (EPROM) data at the byte level • Electronically Eraseable Programmable Read •Two types Only Memory (EEPROM) –Static RAM – Dynamic RAM • Flash Memory • Volatile CSCI 4717 – Computer Architecture Memory Details – Page 3 of 34 CSCI 4717 – Computer Architecture Memory Details – Page 4 of 34 Read Only Memory (ROM) ROM Uses • Sometimes can be erased for reprogramming, but might have odd requirements such as UV light or • Permanent storage – nonvolatile erasure only at the block level • Microprogramming • Sometimes require special device to program, i.e., • Library subroutines processor can only read, not write • Systems programs (BIOS) •Types • Function tables – EPROM • Embedded system code – EEPROM – Custom Masked ROM –OTPROM –FLASH CSCI 4717 – Computer Architecture
    [Show full text]
  • An EEPROM Cell for Automotive Applications in PD-SOI
    51. IWK Internationales Wissenschaftliches Kolloquium International Scientific Colloquium PROCEEDINGS 11-15 September 2006 FACULTY OF ELECTRICAL ENGINEERING AND INFORMATION SCIENCE INFORMATION TECHNOLOGY AND ELECTRICAL ENGINEERING - DEVICES AND SYSTEMS, MATERIALS AND TECHNOLOGIES FOR THE FUTURE Startseite / Index: http://www.db-thueringen.de/servlets/DocumentServlet?id=12391 Impressum Herausgeber: Der Rektor der Technischen Universität llmenau Univ.-Prof. Dr. rer. nat. habil. Peter Scharff Redaktion: Referat Marketing und Studentische Angelegenheiten Andrea Schneider Fakultät für Elektrotechnik und Informationstechnik Susanne Jakob Dipl.-Ing. Helge Drumm Redaktionsschluss: 07. Juli 2006 Technische Realisierung (CD-Rom-Ausgabe): Institut für Medientechnik an der TU Ilmenau Dipl.-Ing. Christian Weigel Dipl.-Ing. Marco Albrecht Dipl.-Ing. Helge Drumm Technische Realisierung (Online-Ausgabe): Universitätsbibliothek Ilmenau Postfach 10 05 65 98684 Ilmenau Verlag: Verlag ISLE, Betriebsstätte des ISLE e.V. Werner-von-Siemens-Str. 16 98693 llrnenau © Technische Universität llmenau (Thür.) 2006 Diese Publikationen und alle in ihr enthaltenen Beiträge und Abbildungen sind urheberrechtlich geschützt. Mit Ausnahme der gesetzlich zugelassenen Fälle ist eine Verwertung ohne Einwilligung der Redaktion strafbar. ISBN (Druckausgabe): 3-938843-15-2 ISBN (CD-Rom-Ausgabe): 3-938843-16-0 Startseite / Index: http://www.db-thueringen.de/servlets/DocumentServlet?id=12391 51st Internationales Wissenschaftliches Kolloquium Technische Universität Ilmenau September 11 – 15, 2006 D. Kirsten / S. Richter / Dr. D. Nuernbergk / St. Richter An EEPROM cell for automotive applications in PD-SOI 1. ABSTRACT The feasibility of EEPROM memories in SOI process technologies has been proven [1]. It has also been shown that known data retention problems at high temperatures caused by leakage currents can be solved without extra circuitry [2].
    [Show full text]
  • 16 X 1 Nmos STATIC RANDOM ACCESS MEMORY DESIGN
    16 x 1 nMOS STATIC RANDOM ACCESS MEMORY DESIGN W. David Dougherty 5th Year Microelectronic Engineering Student Rochester Institute of Technology ABSTRACT A Static Random Access Memory (SRAM) was designed using a 2 micron minimum geometry, nMOS fabrication process on an Apollo design station. In addition to the SRAN integrated circuit, test structures were included to help characterize the process and design. The chip contained over 200 transistors on a die size of 800 square microns. Simulation results predicted an access time of 50 nano—seconds. The pads were configured to fit a 20 pin probe card to facilitate automatic testing. INTRODUCTION The design of any complex integrated circuit needs to be reduced into its component parts. A hierarchical approach can be used in which circuits are built from the bottom up. Cells are made to represent the commonly used parts and combined to form the final circuit. *MentorGraphics is a design software company that has implemented this approach to VLSI design. As shown in Figure 1, the first phase of any hierarchical design is the creation of the basic cells. These schematics are then entered into the computer through the NETED software package. NETED is a schematic capture program which converts circuit diagrams into nodelists. These nodelists, in conjunction with a transistor Models file, define the circuit, interconnections, and the device characteristics of the nMOS transistors. Circuit simulations are performed with the MSIMON software package. This program is similar to SPICE but optimized for MOS devices. For each cell, input waveforms had to be determined in order to provide thorough simulation of all combinations of inputs.
    [Show full text]
  • First Progress Report on a Multi-Channel Magnetic Drum Inner
    KL'ECTRONIC CQ^^^^tmR PROJECT INSTITUTE FOR/ADVANCED SUDY PRINCETON, NEW JERSEY FIRST PROGRESS REPORT ON A MULTI- CHANNEL MAGNETIC DRUM INNER MEMORY FOR USE IN ELECTRONIC DIGITAL COMPUTING INSTRUMENTS by J. H. Bigelow P. Panagos M. Rubinoff W. H. Ware Institute for Advanced Study Electronic Computer Project Princeton, New Jersey 1 July 1948 04S3 First Progress Report on a Multi-Channel Magnetic Drum Inner Memory for use in Electronic Digital Computing Instruments by J. H. Bigelow P. Panagos M. Rubinoff W. H. 'Ware Institute for Advanced S^udy Electronic Computer Project Princeton, New Jersey 1 July 1948 ii P R S F ACE The ensuing report has been prepared in accordance with the terms of Contract K6-ord-139, Task Order II, between Office of Naval Research, U. S. Navy, and the Institute for Advanced Study. The express purpose of this report is to furnish contemporary advice to the Service regarding steps taken and contemplated toward the realization of an electronic computing instrument embodying the principles outlined in the following Institute for Advanced Study reports: (1) "Preliminary Discussion of the Logical Design of an Electronic Computing Instrument", by Burks, Goldstine, and von Neumann. 28 June 1946. (2) "Interim Progress Report on the Physical Realization of an Electronic Computing Instrument", by Bigelow, Pomerene, Slutz, and Ware, 1 January 1947. (3) "Planning and Coding of Problems for an Electronic Computing Instrument", by Goldstine and von Neumann. 1 April 1947- (4) "Second Interim Progress Report on the Physical Realization of an Electronic Computing Instrument", by Bigelow, Hildebrandt, Pomerene, Snyder, Slutz, and V/are.
    [Show full text]