International Journal of Pure and Applied Mathematics 118 No. 20 2018, 4915-4921 ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu Special Issue ijpam.eu

3T GAIN CELL EMBEDDED DRAM BASED ON GATE DIFFUSION TECHNIQUE (GDI) IN LOW POWER APPLICATIONS

P.SUJITHA1, M.DEIVAKANI2 1 PG Scholar, (dept of ECE,PSNA CET, DINDIGUL E-mail id-sujitha020594@gmail com) 2 Assistant professor, (dept of ECE, PSNA CET,DINDIGUL)

ABSTRACT: main memory. There are some other types of DRAM in the industry. They are, Recently, the Gain cell Embedded DRAM plays a vital role than SRAM. So, GC-e DRAM which has some 1. Conventional DRAM features that includes high balance, low out flow, low 2. Fast Page Mode DRAM (FPM DRAM) voltage and 2 fixated conclusion. The time permits 3. Enhanced DRAM (EDRAM) periodic power hungry renew cycles. The drawbacks to 4. Extended out DRAM (EDO DRAM) be strengthen at ascend inventions, when expanding sub 5. Burst Extended Data out DRAM (BEDO DRAM) threshold leakage currentsand further it is minimized. A 6. Synchronous DRAM (SDRAM) 4T GC-e DRAM cell produces the feedback which is 7. Enhanced Synchronous DRAM (ES DRAM) internally contracted to improve the data retention 8. Double Data- Rate DRAM (DDR DRAM) time.The retention time of 3TGC-eDRAM cell is 9. Synchronous Link DRAM (SL DRAM) significantly more than that of 4T Gain cell and 3T gain 10. Rambus DRAM (RDRAM) cell. Retention time tends to decrease as the supply 11. Embedded DRAM (Em DRAM) voltage increases. To improve the performance and data 12. Direct Rambus DRAM (DR DRAM) retention time a new technique named GDI (Gate 13. Video RAM (VRAM). Diffusion Input Technique). Some of them were below described as, Keywords: Embedded DRAM, Single event upset (SEU), Gate Diffusion Input Technique (GDI), data retention A. CONVENTIONAL DRAM: time, Error Correction Codes (ECC), Low Power Applications. In DRAM industry, The Column Address and the Row Address were first send to the Memory Array by using the I.INTRODUCTION earlier method of standard memory address. In Conventional DRAM, Multiplexing canbe achieved. TheMost energetic and efficient method of the RAM Memory is that the Dynamic Random Access B.FAST PAGE MODE DRAM :( FPM DRAM) Memory(DRAM).The Binary technique is done by reducing a Single -. The Leak aging or The Conventional DRAM is slower than FPM DRAM. This emission method in this DRAM cell which needs the FPM DRAM needs both the row address and the column capacitor to simulate the requirement of the Data retention address in the same page address. It is used to improve time time which is shortly indicated by the word and reduce power dissipation. ‘DYNAMIC’.The DRAM cell was first materialised in 1970 C.ENHANCED DRAM :( EDRAM) with some capacitor of 1kb size. As Astounding result in the DRAM Capacity, the memory cell area been reduced to 60 It is the combination of both SRAM and SRAM. It supports percent at the same time the size has increased by 50 speed and performance of SRAM and also the density and percent. the cost of DRAM.

TYPES OF DRAM: F.SYNCHRONOUS DRAM: (SDRAM)

DRAM plays a vital role in the main memory which reserves The System clock of the controls the DRAM data and programs.90percent of DRAM were included in architectures.

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J.RAMBUS DRAM :( RDRAM) A cost-effective gain cell for memory embedded in logic LSIs. The new cell consists of two conventional bulk Packets were transported within both command and address and one MOS capacitor. It can be fabricated using by the Rambus DRAM which acts as the bidirectional link. the pure logic process with a few additional process steps.[7]. The fabrication cost of this cell is lower than that L. EMBEDDED DRAM (EmDRAM): of DRAM or SRAM at a memory density in the 1-100Mbit range. To enhance the System performance in System on chip (SOC), the indispensable approach. The most advantage of To achieve power optimization and trade-offs, a single edge Embedded DRAM is high bandwidth, lower power triggered and double edge triggered flip flops were used by consumption, and customized memory sizes and higher the new GDI technique.[16] It is also used to calculate the consumption. aspect ratio and the frequency. This technique is to analyse the few delay [11] of the circuit when compared with the II.RELATED WORKS some other CMOS configuration. A replica technique for automatically tracking the retention time of a gain cell-embedded dynamic-random- This Gate Clocking Dissipation Input Technique [17] access-memory macro cell according to process variations consists of EX-OR &AND gates were included in the and operating statistics, thereby reducing the data retention circuit. It decreases the power dissipation.The Design of the power of the array.[2] A 2-kb array was designed and digital combinatorial circuit with the GDI technique fabricated in a mature 0.18-μm CMOS process, decreases power consumption, propagation delay and area appropriate for integration in ultralow power applications, [13]. This GDI cell is implemented with some complex logic such as biomedical sensors.Measurements show efficient function and also it improves the power characteristics of the retention time tracking across arrange of supply voltages circuit. and access statistics, lowering the refresh frequency by more than 5×, as compared with traditional III.PROPOSED METHOD worstcasedesign. Recently, the Gain cell Embedded DRAM plays a vital role A boosted 3Tgain cell utilizes Read Word-line (RWL) than SRAM. So, GC-e DRAM which has some features that preferential boosting to increase read margin and improve includes high balance, low out flow, low voltage and 2 data retention time. Read speedis enhanced with a hybrid fixated conclusion. The time permits periodic power hungry current/voltage sense that allowsthe Read Bit-line renew cycles. The drawbacks to be strengthen at ascend (RBL) to remain close to VDD.[3]The proposedboosted 3T inventions, when expanding sub threshold leakage gain cell can provide a stronger coupling effect withonly currentsand further it is minimized. A 4T GC-e DRAM bit three transistors, increasing data retention time, cell produces the feedback which is internally contracted to enhancingthe RBL margin and improving read improve the data retention time. The retention time of performance[3]. 3TGC-eDRAM cell is significantly more than that of 4T Gain cell and 3T gain cell. Retention time tends to decrease An asymmetric 2T gain cell utilizesa half-swing write bit- as the supply voltage increases. To improve the performance line (WBL) scheme is adopted to improve the WBLspeed and data retention time a new technique named GDI (Gate and reduce its power dissipation duringwrite-back operation Diffusion Input Technique). with no effect on retention time.[4] A stepped right word- line (WWL) driver reduces the current drawn fromthe W R boosted high and low supplies. A 192 kb eDRAM test chip B with 512 cells-per-BL implemented in a 65 nm low-power W W (LP) CMOS process shows a random cycle frequency and L B L latencyof 667 MHz and 1.65 ns, respectively, at 1.1 V and B S 85 C[4]. Themeasured refresh period at a bit yield condition N P was 110swhich is comparable to that of recently published L S N 1T1C eDRAMdesigns. P G R D C A 5.42nW/ kB Retention Power Logic-Compatible F S R Embedded DRAM with 2T Dual- Vt Gain Cell for Low N Power Sensing Applications. A logic-compatible 2T dual-Vt embedded DRAM (e DRAM) is proposed for ultra-small W sensing systems to achieve 8× longer retention time, 5× L lower refresh power and reduced area compared with the lowest power e DRAM previously reported.[5] With an area-efficient single inverter sensing scheme designed for FIG 1: STRUCTURE OF4T GC-e DRAM R/W speed compatibility with ultralow power processors, array efficiency is maintained for memories as small as 2kb The method presented that the data ‘0’ is to be achieved to and for as few as 32 per bit line. improve the bit cell’s retention time. The Proposed circuit can be identified using some buffer nodes like (BN, SN).SN

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is linked to the feedback device (PF) which suites to MITIGATION TECHNIQUES: discharge (BN) according to the data. The concluded 4T bit cell is constructed separately with (VT) Sub-threshold I. Triple Modular Redundancy(TMR) voltage. It is fully compatible with the normal inverter. The II. Dual Modular Redundancy(DMR) 4T cell is resolved in a same manner as like normal 2T cell. III. Multiple redundancies with voting IV. EDAC(Error Detection And Correction coding) While write operation is in process, the WWL is connected to PW and PB nodes which is pressed to a negative voltage It can reduce up to the accepted level of some radiation to discharge SN. While read operation is in process to pre- effects such as Total Ionization Dose(TID) and Single event discharge RBL to ground and charge RWL to VDD. To latch up(SEL).But they do not completely discard upset bring efficient area and power, a sense inverter is used on effects such as SEU’s & SET.In Low volume Production the read path. Sometimes, other sense were used very few techniques were adopted and also, it is very to get improved readperformance. The method presented expensive. The threshold LET values of ‘SOI’ is nearly that the data ‘0’ is to be achieved to improve the bit cell’s same as bulk/epi process. But from the fabrication, there is retention time. The Proposed circuit can be identified using some little improvement in SEU Sensitivity. some buffer nodes (BN).The another term (SN) is linked to the feedback device (PF) which suites to discharge (BN) B. ERROR DETECTION AND CORRECTION according to the data. The concluded 4T bit cell is constructed separately with (VT) sub threshold voltage .It is A Single bit of DRAM is caused inside a system fully compatible with the normal inverter. This 4T cell is by the electrical /magnetic interference to flip to the opposite resolved in a same manner as like normal 2T cell. While state. The Result of back ground radiation occur in write operation is in process, the (WWL) is connected to the accordance with the majority of soft errors in DRAM. It PW and PB nodes which is pressed to a negative voltage to changes the contents of one or more memory cells. The Error discharge (SN). While Read operation is in process to pre rates of single event upset with over seven order includes discharge RBL to ground and charge RWL to VDD. To magnitude differences ranging from roughly one bit per bring efficient area and power, a sense inverter is used on error, per century, per giga byte of memory.Redundant read out path. Sometimes, other sense amplifier was used to memory bits and some additional circuitry can cause some get improved read performance. mitigation problems. And also some soft errors were detected and corrected. These detection and correction 3T GC-e DRAM CELL: method was performed by the memory controller. The memory bits are used to record parity and to be constructed by error correcting codes (ECC).

C.GATE DIFFUSION INPUT TECHNIQUE (GDI):

The Gate Diffusion Input cell having 4 nodes in it, which includes G, P, N and the D nodes. Where G, P and N were the input nodes and D is acting as the output nodes. P

FIG 2: STRUCTURE OF 3T GC-e DRAM D A.SEU MITIGATION METHODS G

The Single event upset (SEU), which is one of the unintentional changes of state. The ionized radiation of an integrated circuits like ASIC, ASSP, FPGA, memory, Logic & mixed signal device causes this kind of upset called Single event upset (SEU).It is rare and fully recoverable only in N Xilinx devices. The Basic information of Xilinx, which provides the system reliability, availability. So, that it provides the comprehensive solution for SEU mitigation. FIG 3:BASIC GDI CELL This method is used for spacecraftshielding and also, it reduces the flux at the least level, but it doesn’t thoroughly The Combinations of the P, N and G nodes were the inputs eliminate it. It is enough to avoid an error which is caused of the circuits. There are some logic functions in the GDI by radiation effects. Due to the fabrication technology cell. circuits are becoming sensitive to radiating particles.The Particles which are charged to be negligible to cause errors. Many SEU mitigation techniques to remove a fault which includes faults in Programmable logic.

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N P G D FUNCTION ‘0’ B A ~AB F1 B ‘1’ A ~A+B F2 ‘1’ B A A+B OR B ‘0’ A AB AND C B A ~AB+AC MUX ‘0’ ‘1’ A ~A NOT TABLE 1:Some Logic function that can be implemented with a single GDI cell

FUNCTIONS OF GDI CELL:

This Function indicates from the above Table 1.The Functions F1 and F2 are the two possible input functions.F1 indicates the general P well CMOS due to some equally biased NMOS.While the input ‘N’ hassome high level input and the ‘P’ has low level input the two were getting polarised and it concludes some static power consumption.There is also some drawbacks for three functions of logic gates ‘OR’, ‘AND’ and ‘MUX’. It decreases the floating values of huge SOI technologies.

D.SEQUENTIAL DIAGRAM DEPICTION:

A Sequential diagram demonstrates the error detection and algorithm. The input write address was written as (DI) & its complementary (DIB). The Parity of the original value (DI) is calculated and stored. The two values were compared according to the bitwise. If the bits were equal, then the error will be occurred.The erroneous data are then corrected to provide an errorless output. The N-bit word does not apply to multiple bit upset, which is to be induced through energetic cosmic ray particles.Resulting in a parasitic bipolar conduction, potentially flipping numerous bits in a single well. To account for more than one error per every set of bits that includes parity, bit interleaving techniques can FIG 4: SEQUENTIAL DIAGRAM FOR ERROR DETECTION AND be used. However, for single-ended readout storage CORRECTION architectures, half-select susceptibility is a problem that must be addressed, if column multiplexing or byte masking is required. This can easily be solved by either writing entire words at a time, or by performing a read-modify-write operation, when byte masking is required. In addition, parity can be applied to every k < N bits for additional protection. IV. SIMULATION RESULT

FIG 5: LAYOUT DESIGN OF 4T GC-e DRAM

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FIG 9: SIMULATION RESULT FOR SEU=0

FIG 6: SIMULATION RESULT FOR 4T GC-e DRAM

FIG 10: SIMULATION RESULT FOR SEU=1

FIG 7: LAYOUT DESIGN OF 3T GC-e DRAM

FIG 11:SIMULATION RESULT FOR GDI OF THE CIRCUIT

FIG 8:SIMULATION RESULT OF 3T GC-e DRAM

FIG 12: COMPARISON RESULT

TABLE I

COMPARISON OF VARIOUS PARAMETERS

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S.NO PARAMETER PROPOSED [3] Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, and Chris 01. POWER 100ns H. Kim.”A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On- 02. SLICE 1 Die Caches” 2014 IEEE 28-th Convention of Electrical and Electronics Engineers in Israel. 03. LUT 4 [4] Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, and Chris H. Kim,” A 667 MHz Logic-Compatible EmbeddedDRAM Featuring an Asymmetric 2T Gain Cellfor High Speed On- PERFORMANCE ANALYSIS Die Caches” IEEE Trans.CircuitsSyst.II,Exp.Brief Vol.61,no.4,2014.

The Diagram represents the reduction of time and area [5] Yoonmyung Lee, Mao-Ter Chen, Junsun Park, which has implemented by using TINA. This Paper proposes Dennis Sylvester, DavidBlaauw,”5.42nW/kB Retention the method to reduce the area and power dissipation than the Power Logic-Compatible Embedded DRAM with 2T Dual- previous method. Vt Gain Cell for Low Power Sensing Applications” ,J. Eng.,vol.1,no.1,pp.1-3,2014.

[6] N.Ikeda, T.Terano, H.Moriya, T.Emorid, T.Kobayashi ,”A Novel Logic Compatible gain cell with two transistors and one capacitor,”in Symp.VLSI 6 TechnolDig.Tech.Papers.,2000,pp.168-169. 4 [7] P.Meinerzhagen ,A.Teman, a.Fish and A.Burg,”Impact of body biasing on the retention time of 2 gain cell memories”,J. Eng.,vol.1,no.1,pp.1-3,2013.

0 [8] R. Giterman, A. Teman, P. Meinerzhagen, L. Atias, Existing Proposed A. Burg, and A. Fish, “Single-supply 3T gain-cell for low- voltage low-power applications,” IEEE Trans. Very Large slice Lut Scale Integr. (VLSI) Syst., vol. 24, no. 1, pp. 358–362, Jan.

2016. FIG 13: PERFORMANCE ANALYSIS [9] P.divya, M.Jayashree,”3T Gain cell EDRAM for V. CONCLUSION Low Power Application,” International Journal on application in information and communication engineering The Conventional SRAM has some alternative method in volume 2:Issue 4:April 2016. case of issues, embedded DRAM is used. While, GC-e DRAM is logic Compatible, it is immune to other faults or [10] Arcady Morgenshtein, Alexander Fish, and Israel errors at low supply voltages. The high out flow currents A. Wagner,”Gate-Diffusion Input (GDI): A Power-Efficient characterizes the CMOS nodes in this GC-e DRAM. The bit Method for Digital Combinatorial Circuits,”IEEE cell design protects the weak data level (‘0’) by a transactions on very large scale integration (VLSI) systems, conditional, cell-internal feedback path, while the feedback vol. 10, no. 5, October 2002. is disabled for the strong data level (‘1’).The retention time of 3TGC-eDRAM cell is significantly more than that of 4T [11] Padmanabhan Balasubramanian and Johince Gain cell and 3T gain cell. Retention time tends to decrease John,”Low Power Digital design using modified GDI as the supply voltage increases. The 20% of power method “,IEEE Trans. Nucl. Sci., vol.NS-4,no 6, May dissipated in 3T gain cell than 4T gain cell and the area 5%of 2006,pp.7803-9727. has reduced in 3T GC-e DRAM cell.To improve the performance and data retention time a newtechnique named [12] Sujatha Hire math, Deepali Koppad,”Low Power GDI (Gate Diffusion Input Technique). Circuits using Modified Gate Diffusion Input(GDI)”,IOSR Journal of VLSI and Signal Processing(IOSR-JVSP) REFERENCES Volume 4, Issue 5, Ver.II(Sep-Oct.2014),PP 70-76 e ISSN No.:2319-4197. [1]R.Gilterman, L.Atlias and A.Teman, ”Area and energy-efficient complementary Dual-Modular [13] Arkadiy Morgenshtein, M Moreinis and R Ginosar, Redundancy Dynamic Memory for space applications. “Asynchronous Gate-Diffusion-Input (GDI) Circuits” IEEE Transactions on VLSI Systems, vol. 12, no. 8, pp.847-856, [2]R.Gilterman, A. Fish, and A. Burg,”Replica technique August 2004. for adaptive refresh timing of gain- cell-embedded DRAM”,IEEE Trans.CircuitsSyst.II,Exp.BriefVol.61,no.4,2014

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