3T Gain Cell Embedded Dram Based on Gate Diffusion Technique (Gdi) in Low Power Applications

3T Gain Cell Embedded Dram Based on Gate Diffusion Technique (Gdi) in Low Power Applications

International Journal of Pure and Applied Mathematics Volume 118 No. 20 2018, 4915-4921 ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu Special Issue ijpam.eu 3T GAIN CELL EMBEDDED DRAM BASED ON GATE DIFFUSION TECHNIQUE (GDI) IN LOW POWER APPLICATIONS P.SUJITHA1, M.DEIVAKANI2 1 PG Scholar, (dept of ECE,PSNA CET, DINDIGUL E-mail id-sujitha020594@gmail com) 2 Assistant professor, (dept of ECE, PSNA CET,DINDIGUL) ABSTRACT: main memory. There are some other types of DRAM in the industry. They are, Recently, the Gain cell Embedded DRAM plays a vital role than SRAM. So, GC-e DRAM which has some 1. Conventional DRAM features that includes high balance, low out flow, low 2. Fast Page Mode DRAM (FPM DRAM) voltage and 2 fixated conclusion. The time permits 3. Enhanced DRAM (EDRAM) periodic power hungry renew cycles. The drawbacks to 4. Extended Data out DRAM (EDO DRAM) be strengthen at ascend inventions, when expanding sub 5. Burst Extended Data out DRAM (BEDO DRAM) threshold leakage currentsand further it is minimized. A 6. Synchronous DRAM (SDRAM) 4T GC-e DRAM bit cell produces the feedback which is 7. Enhanced Synchronous DRAM (ES DRAM) internally contracted to improve the data retention 8. Double Data- Rate DRAM (DDR DRAM) time.The retention time of 3TGC-eDRAM cell is 9. Synchronous Link DRAM (SL DRAM) significantly more than that of 4T Gain cell and 3T gain 10. Rambus DRAM (RDRAM) cell. Retention time tends to decrease as the supply 11. Embedded DRAM (Em DRAM) voltage increases. To improve the performance and data 12. Direct Rambus DRAM (DR DRAM) retention time a new technique named GDI (Gate 13. Video RAM (VRAM). Diffusion Input Technique). Some of them were below described as, Keywords: Embedded DRAM, Single event upset (SEU), Gate Diffusion Input Technique (GDI), data retention A. CONVENTIONAL DRAM: time, Error Correction Codes (ECC), Low Power Applications. In DRAM industry, The Column Address and the Row Address were first send to the Memory Array by using the I.INTRODUCTION earlier method of standard memory address. In Conventional DRAM, Multiplexing canbe achieved. TheMost energetic and efficient method of the RAM Memory is that the Dynamic Random Access B.FAST PAGE MODE DRAM :( FPM DRAM) Memory(DRAM).The Binary data storage technique is done by reducing a Single transistor-Capacitor. The Leak aging or The Conventional DRAM is slower than FPM DRAM. This emission method in this DRAM cell which needs the FPM DRAM needs both the row address and the column capacitor to simulate the requirement of the Data retention address in the same page address. It is used to improve time time which is shortly indicated by the word and reduce power dissipation. ‘DYNAMIC’.The DRAM cell was first materialised in 1970 C.ENHANCED DRAM :( EDRAM) with some capacitor of 1kb size. As Astounding result in the DRAM Capacity, the memory cell area been reduced to 60 It is the combination of both SRAM and SRAM. It supports percent at the same time the die size has increased by 50 speed and performance of SRAM and also the density and percent. the cost of DRAM. TYPES OF DRAM: F.SYNCHRONOUS DRAM: (SDRAM) DRAM plays a vital role in the main memory which reserves The System clock of the processor controls the DRAM data and programs.90percent of DRAM were included in architectures. 4915 International Journal of Pure and Applied Mathematics Special Issue J.RAMBUS DRAM :( RDRAM) A cost-effective gain cell for memory embedded in logic LSIs. The new cell consists of two conventional bulk Packets were transported within both command and address transistors and one MOS capacitor. It can be fabricated using by the Rambus DRAM which acts as the bidirectional link. the pure logic process with a few additional process steps.[7]. The fabrication cost of this cell is lower than that L. EMBEDDED DRAM (EmDRAM): of DRAM or SRAM at a memory density in the 1-100Mbit range. To enhance the System performance in System on chip (SOC), the indispensable approach. The most advantage of To achieve power optimization and trade-offs, a single edge Embedded DRAM is high bandwidth, lower power triggered and double edge triggered flip flops were used by consumption, and customized memory sizes and higher the new GDI technique.[16] It is also used to calculate the consumption. aspect ratio and the frequency. This technique is to analyse the few delay [11] of the circuit when compared with the II.RELATED WORKS some other CMOS configuration. A replica technique for automatically tracking the retention time of a gain cell-embedded dynamic-random- This Gate Clocking Dissipation Input Technique [17] access-memory macro cell according to process variations consists of EX-OR &AND gates were included in the and operating statistics, thereby reducing the data retention circuit. It decreases the power dissipation.The Design of the power of the array.[2] A 2-kb array was designed and digital combinatorial circuit with the GDI technique fabricated in a mature 0.18-μm CMOS process, decreases power consumption, propagation delay and area appropriate for integration in ultralow power applications, [13]. This GDI cell is implemented with some complex logic such as biomedical sensors.Measurements show efficient function and also it improves the power characteristics of the retention time tracking across arrange of supply voltages circuit. and access statistics, lowering the refresh frequency by more than 5×, as compared with traditional III.PROPOSED METHOD worstcasedesign. Recently, the Gain cell Embedded DRAM plays a vital role A boosted 3Tgain cell utilizes Read Word-line (RWL) than SRAM. So, GC-e DRAM which has some features that preferential boosting to increase read margin and improve includes high balance, low out flow, low voltage and 2 data retention time. Read speedis enhanced with a hybrid fixated conclusion. The time permits periodic power hungry current/voltage sense amplifier that allowsthe Read Bit-line renew cycles. The drawbacks to be strengthen at ascend (RBL) to remain close to VDD.[3]The proposedboosted 3T inventions, when expanding sub threshold leakage gain cell can provide a stronger coupling effect withonly currentsand further it is minimized. A 4T GC-e DRAM bit three transistors, increasing data retention time, cell produces the feedback which is internally contracted to enhancingthe RBL margin and improving read improve the data retention time. The retention time of performance[3]. 3TGC-eDRAM cell is significantly more than that of 4T Gain cell and 3T gain cell. Retention time tends to decrease An asymmetric 2T gain cell utilizesa half-swing write bit- as the supply voltage increases. To improve the performance line (WBL) scheme is adopted to improve the WBLspeed and data retention time a new technique named GDI (Gate and reduce its power dissipation duringwrite-back operation Diffusion Input Technique). with no effect on retention time.[4] A stepped right word- line (WWL) driver reduces the current drawn fromthe W R boosted high and low supplies. A 192 kb eDRAM test chip B with 512 cells-per-BL implemented in a 65 nm low-power W W (LP) CMOS process shows a random cycle frequency and L B L latencyof 667 MHz and 1.65 ns, respectively, at 1.1 V and B S 85 C[4]. Themeasured refresh period at a bit yield condition N P was 110swhich is comparable to that of recently published L S N 1T1C eDRAMdesigns. P G R D C A 5.42nW/ kB Retention Power Logic-Compatible F S Embedded DRAM with 2T Dual- Vt Gain Cell for Low R N Power Sensing Applications. A logic-compatible 2T dual-Vt embedded DRAM (e DRAM) is proposed for ultra-small W sensing systems to achieve 8× longer retention time, 5× L lower refresh power and reduced area compared with the lowest power e DRAM previously reported.[5] With an area-efficient single inverter sensing scheme designed for FIG 1: STRUCTURE OF4T GC-e DRAM R/W speed compatibility with ultralow power processors, array efficiency is maintained for memories as small as 2kb The method presented that the data ‘0’ is to be achieved to and for as few as 32 bits per bit line. improve the bit cell’s retention time. The Proposed circuit can be identified using some buffer nodes like (BN, SN).SN 4916 International Journal of Pure and Applied Mathematics Special Issue is linked to the feedback device (PF) which suites to MITIGATION TECHNIQUES: discharge (BN) according to the data. The concluded 4T bit cell is constructed separately with (VT) Sub-threshold I. Triple Modular Redundancy(TMR) voltage. It is fully compatible with the normal inverter. The II. Dual Modular Redundancy(DMR) 4T cell is resolved in a same manner as like normal 2T cell. III. Multiple redundancies with voting IV. EDAC(Error Detection And Correction coding) While write operation is in process, the WWL is connected to PW and PB nodes which is pressed to a negative voltage It can reduce up to the accepted level of some radiation to discharge SN. While read operation is in process to pre- effects such as Total Ionization Dose(TID) and Single event discharge RBL to ground and charge RWL to VDD. To latch up(SEL).But they do not completely discard upset bring efficient area and power, a sense inverter is used on effects such as SEU’s & SET.In Low volume Production the read path. Sometimes, other sense amplifiers were used very few techniques were adopted and also, it is very to get improved readperformance. The method presented expensive. The threshold LET values of ‘SOI’ is nearly that the data ‘0’ is to be achieved to improve the bit cell’s same as bulk/epi process.

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