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California State University, Northridge an Error CALIFORNIA STATE UNIVERSITY, NORTHRIDGE AN ERROR DETECTING AND CORRECTING SYSTEM FOR MAGNETIC STORAGE DISKS A project submitted in partial satisfaction of the requirements for the degree of Master of Science in Engineering by David Allan Kieselbach June, 1981 The project of David Allan Kieselbach is approved: Nagi M. Committee Chairman California State University, Northridge ii ACKNOWLEDGMENTS I wish to thank Professor Nagi El Naga who helped in numerous ways by suggesting, reviewing and criticizing the entire project. I also wish to thank my employer, Hughes Aircraft Company, who sponsored my Master of Science studies under the Hughes Fellowship Program. In addition the company prov~ded the services of the Technical Typing Center to aid in the preparation of the project manuscript. Specifically I offer my sincere gratitude to Sharon Scott and Aiko Ogata who are responsible for the excellent quality of typing and art work of the figures. For assistance in proof reading and remaining a friend throughout the long ordeal my special thanks to Christine Wacker. Finally to my parents, Dulcie and Henry who have always given me their affection and encouragement I owe my utmost appreciation and debt of gratitude. iii TABLE OF CONTENTS CHAPTER I. INTRODUCTION Page 1.1 Introduction . 1 1.2 Objectives •••••.• 4 1.3 Project Outline 5 CHAPTER II. EDCC CODES 2.1 Generator Matrix 11 2.1.1 Systematic Generator Matrix •. 12 2.2 Parity Check Matrix 16 2.3 Cyclic Codes .• . 19 2.4 Analytic Methods of Code Construction . 21 2.4.1 Hamming Codes • • 21 2.4.2 Fire Codes 21 2.4.3 Burton Codes- 24 2.4.4 BCH Codes • • . 25 CHAPTER III. ENCODING 3.1 The Mathematics of Encoding a Cyclic Code 26 3.2 Encoding Via the Generator Matrix 32 3.3 Encoding Implementation for Cyclic Codes . 36 3.3.1 Encoding With an (n-k) Stage Shift Register • 38 3.3.1.1 Multiplier Circuit Encoder • • . 38 3.3.1.2 Divider Circuit Encoder (Unmodified) 38 3.3.1.3 Divider Circuit En~oder (Modified) • 40 3.3.2 Encoding With a k Stage Shift Register 43 3.4 Shortened Cyclic Codes • 49 iv TABLE OF CONTENTS (Continued) CHAPTER IV. DECODING Page 4.1 Error Detection 51 4.2 Decoding Procedures 55 4.2.1 Table Look-up Decoding 56 4.2.2 Meggitt Decoding Technique • • • • 57 4.2.3 Error Trapping • • . • 61 4.2.4 Trial and Error Decoding . • . 64 4.2.5 Majority Logic Decoding ••...•... 66 4.2.6 Algebraic Procedures . • . 68 4.3 Examples of Practical Burst Error Correcting Decoders • . 68 4.4 Decoding Shortened Codes • 76 4.5 Encoder/Decoders • 78 CHAPTER V. INTERLEAVING 5.1 Symbol Interleaving 82 5 .1.1 Interleaving Via Code Expansion . • 82 5 .1.2 Interleaving Via Manipulation of Code Vectors .. • • . • • . • 83 5.1.2.1 I-Encoder Interleaving • . • 87 5.1.2.2 Array Manipulation Interleaving 87 5.2 Block Interleaving •.•..••••.••.•• 90 CHAPTER VI. EDCC SYSTEM DESIGN 6.1 Introduction • • • • • 92 6.2 Code and Interleaving Degree Selection • 96 6.2.1 Determination of G(X) for the EDC • 96 6.2.2 Determination of tne Interleaving Degree (EDCC) • . • • • • . 97 6.2.3 Determination of G(X) for the EDCC 105 6.3 Encoding Process .•. 107 6.3.1 EDC Encoding 107 6.3.2 EDCC Encoding . • • . 107 6.3.3 Combined EDC and EDCC Encoding 110 6.4 Decoding and Error Correction 114 6.4.1 EDCC Decoding .••••• 114 6.4.1.1 Premultiplication Polynomial 117 v TABLE OF CONTENTS (Continued) CHAPTER VI (Continued)' Page 6.4.2 Error Correction Algorithm 118 6.4.3 EDC Decoding 120 6.4.4 Combined EDCC and EDC Decoding 121 6.5 Interleaving . 127 6.6 System Control 132 CHAPTER VII. EDCC SYSTEM SIMULATION 7.1 Description of the Simulation Program 144 7. 1 .1 Program Structure • . • . 146 7.1.1.1 Program Subroutines 147 7.2 Execution of the Simulation Program 149 7.3 Results of the Simulation Program 150 CHAPTER VIII. PERFORMANCE MEASUREMENTS 8.1 Undetectability 152 8.2 Mistakability 156 8.3 Unreliability 159 8.4 Evaluation of the EDC System Parameters 159 8.5 Conclusions 162 REFERENCES 164 APPENDIX A - Flowcharts of Simulation Program and Subroutines • 165 APPENDIX B - Source Code for EDCC Simulation Program 178 APPENDIX C - Results from EDCC Simulation Program . • . 186 vi LIST OF FIGURES CHAPTER I Page 1.1 Block diagram of a general data communication or storage system 3 CHAPTER II 2.1 Block diagram of a one-way data communication system employing an error correcting code • . 7 2.2 Block diagram of a two-way data communication system using error detection and retransmission • 7 2.3 Classes of codes 10 2.4 Encoding circuit for a convolutional code 10 2.5 Matrix constructed of code vectors 14 2.6 Systematic code format 14 CHAPTER III 6 5 3.1 A circuit for dividing by x + x + x4 + x3 + 1 (internal XOR) . 39 6 5 4 3 3.2 A circuit for dividing by x + x + x + x + 1 (external XOR) . 39 3 3.3 Unmodified encoder, G(X) = X +X+ 1 .•. 40 3.4 General circuit for a modified (n-k) stage encoder • • • . • . 41 3.5 Modified encoder for a (15,9) code 44 3.6 General circuit for a k stage encoder • 48 3.7 k stage encoding circuit for (7,4) cyclic code 48 3.8 An (n,k) code shortened by S bits ...• 50 vii LIST OF FIGURES (Continued) CHAPTER IV Page 4.1 The impact of the error polynomial 12 13 14 E(X) = X + X + X on a (15,9) code • • • • • • • 54 4.2 Process of shifting the syndrome until I the degree of the error polynomial is less than that of G(X) 54 I 4.3 Look-up table decoder for an (n,k) code . 58 4.4 A Meggitt decoder for an (n,k) cyclic code 60 4.5 Error trapping decoder for a burst EDCC . 63 4.6 Format of end around burst of length t 65 4. 7 (a) Unmodified error trapping decoder for a (15,9) code .•.••..••.... 70 4.7(b) Corrector/buffer circuit for the unmodified decoder of figure 4.7(a) .••• 71 4.8 Modified error trapping decoder for a (15,9) code • . • . • . • • • • .••••.•• 72 4.9 Modified error trapping decoder for a (15,9) code shortened by 2 bits 79 4.10 Modified error trapping encoder/decoder for a general (n,k) code • • . • • • . 80 CHAPTER V 5.1 Symbol interleaving the (15, 9) code to degree 5 . 86 5.2 Interleaving via I encoders . • . 86 5.3 Interleaving via array manipulation 88 5.4 A symbol interleaved data stream, I = 2 88 CHAPTER VI -I 6.1 Block diagram of a disk system 94 6.2 Error detecting and correcting system • 95 6.3 EDC format (n,k) = (380,360) 98 6.4 EDCC combined data field for code length 98 6.5 Relationship between code rate and burst correction capability . 103 viii LIST OF FIGURES (Continued) CHAPTER VI (Continued) Page 6.6 Relationship between code rate and interleaving degree • • • 104 6.7 Format for system base EDCC . • 106 6.8 Irreducible polynomials of determination of G (X) • • • • • • • .. • • • • • • • • • 106 6.9 Feedback pattern for G(X) = 1 + x2 + x5 + x9 + x11 + x14 • 108 3 20 6.10 EDC generation circuit, G(X) = 1 +X +X . • • . • 109 6.11 EDCC generation circuit • 111 6.12 Combined encoding circuit • • 112 6.13 Flow chart of encoding process • 113 6.14 EDCC decoding and error correction circuit 116 6.15 Format of the shortened Fire Code . 117 6.16 Fortran program calculation of T(X) for the EDCC • 119 6.17 Subdivisions of the syndrome register • . 118 6.18 EDC decoding circuit . 122 6.19 Combined decoding and error correction circuit 123 6.20 Flowchart of decoding process • • • • • • 125 6.21 The affect of interleaving a (33,19) EDCC to degree I = 20 • • • . • • • • • • • . 128 6.22 Interleaving circuit block diagram 129 6.23 Interleaving circuit 131 6.24 Alternative vertical address generator 133 6.25 EDC encoder/decoder circuit • • • ••• 135 6.26 EDCC encoder/decoder circuit • 136 6.27 Block diagram of the EDCC system 138 6.28 Timing diagram for the WRITE cycle 140 6.29 Timing diagram for the READ cycle • 141 ix LIST OF FIGURES (Continued) CHAPTER VII Page 7.1 EDCC computer simulation block diagram • 143 . I CHAPTER VIII 8.1 Graphic representation of an error detection system . • • . • . .. • . • . 153 8.2 Graphic representation of an EDCC system • • 156 8.3 Code domain of the EDCC system designed with dual codes • . • . • • • • . • • 160 X LIST OF TABLES CHAPTER II Page 2.1 Burst error correcting Fire Codes with b < 10 . • • . • • 23 2.2 A comparison of code construction techniques 25 CHAPTER III 3.1 A (7,4) cyclic code generated by 3 G(X) = X + X + 1 . • . 27 3.2 A (7,4) systematic cyclic code generated 3 by G(X) = x + X + 1 . • • • • . 31 3.3 Internal operation of a modified encoder 45 3.4 Comparison of the encoding techniques • • . 45 CHAPTER IV 4.1 Syndrome generation of an error free received word • • • • • . • • • • • 73 4.2 Syndrome generation of a corrupted received word • • . • • . • • • . 74 4.3 Unmodified decoding versus modified decoding 75 CHAPTER VI 6.1 Possible code lengths and interleave degrees with 380 data bits • • . • . • • 99 6.2 Code selection process for a sector of 380 bits and b > 100 • . • . 102 xi ABSTRACT AN ERROR DETECTING AND CORRECTING SYSTEM FOR MAGNETIC STORAGE DISKS by David Allan Kieselbach Master of Science in Engineering This project presents an error detecting and correcting system for a magnetic disk storage device.
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