High Performance SoC Design Using Magnetic Logic and Memory Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafiné Ravelosona, Claude Chappert, Weisheng Zhao, Lionel Torres, Luís Vitório Cargnini, Raphael Martins Brum, Yue Zhang, et al. To cite this version: Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafiné Ravelosona, Claude Chappert, et al.. High Performance SoC Design Using Magnetic Logic and Memory. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2011, Hong Kong, China. pp.10-33, 10.1007/978-3-642-32770- 4_2. hal-01519767 HAL Id: hal-01519767 https://hal.inria.fr/hal-01519767 Submitted on 9 May 2017 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Distributed under a Creative Commons Attribution| 4.0 International License High Performance SoC Design using Magnetic Logic and Memory Weisheng Zhao1, Lionel Torres3, Luís Vitório Cargnini3, Raphael Martins Brum3, Yue Zhang1, Yoann Guillemenet3, Gilles Sassatelli3, Yahya Lakys1, Jacques-Olivier Klein1, Daniel Etiemble2, Dafiné Ravelosona1, and Claude Chappert1 1 IEF - Université Paris-Sud 11 / CNRS 2 LRI - Université Paris-Sud 11 / CNRS
[email protected] 3 LIRMM - Université Montpellier 2 / CNRS
[email protected] Abstract As the technolody node shrinks down to 90nm and below, high standby power becomes one of the major critical issues for CMOS highspeed computing circuits (e.g.