Df6808 Lattice
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DF6808 8-bit Fast Microcontroller COMPANY OVERVIEW CPU FEATURES FAST architecture – 3.2 times faster than the original DCD-SEMI is a leading IP Core provider and a System-on-Chip implementation design house. The company was founded in 1999 and since Software compatible with 68HC08 industry standard the very beginning has been focused on IP Core architecture Configurable Harvard or Von Neumann architectures improvements. Our innovative, silicon proven solutions have 11 times faster multiplication been employed by over 300 customers and with more than 64 bytes of System Function Registers space (SFRs) 500 hundred licenses sold to companies like Intel, Siemens, Up to 64K bytes of Data Memory Philips, General Electric, Sony and Toyota. Based on more Up to 64K bytes of Code Memory than 70 different architectures, starting from serial interfaces De-multiplexed Address/Data Bus to allow easy memory to advanced microcontrollers and SoCs, we are designing connection solutions tailored to your needs. Two power saving modes: STOP, WAIT Ready pin allows Core to operate with slow program and IP CORE OVERVIEW data memories. Fully synthesizable The DF6808 is an advanced, 8-bit, MCU IP Core with highly Static synchronous design sophisticated, on-chip peripheral capabilities. The DF6808 soft No internal reset generator or gated clock core is binary-compatible with the industry standard Positive edge clocking and no internal tri-states Motorola 68HC08 8-bit microcontroller. It can achieve a Scan test ready performance of 45 – 100 million instructions per second. The 800 MHz of virtual clock frequency compared to original implementation DF6808 has a FAST architecture that is3.2 times USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card faster comparing to the original implementation. In the interfaces available standard configuration the core has major peripheral functions integrated on-chip. The DF6808 Microcontroller Core contains a full-duplex UART – Asynchronous Serial PERIPHERALS Communication Interface (SCI) and Synchronous Serial Peripheral Interface (SPI). The main 16-bit, free-running timer The peripherals listed below are implemented in the standard system has two input capture lines and two output-compare configuration of D68HC11. lines. Self-monitoring circuitry is included on-chip, to protect against system errors. The Computer Operating Properly DoCD™ On-Chip Debugger Processor execution control (COP) watchdog system protects against software failures. An Read, write all processor contents illegal opcode detection circuit provides a non-maskable Hardware execution breakpoints interrupt if illegal opcode is detected. Two software- Three wire communication interface controlled power-saving modes – WAIT and STOP are Four 8-bit I/O Ports available to preserve additional power. These modes make Interrupt Controller the DF6808 IP Core especially attractive for automotive and 7 interrupt sources battery-driven applications. The DF6808 is fully 7 priority levels customizable – it is delivered in the exact configuration to Dedicated Interrupt vector for each interrupt source meet your requirements. There is no need to pay extra for Main16-bit timer/counter system unused features and wasted silicon. It includes fully 16 bit free running counter automated test bench with complete set of tests, Timer clocked by internal source allowing easy package validation, at each stage of SoC design 16-bit Compare/Capture Unit flow. Each DCD’s DF68XX Core has a built-in support for a Two independent input-capture functions proprietary Hardware Debug System calledDoCD™ . It’s Two output-compare channels a real-time hardware debugger which provides debugging Events capturing capability of a whole System-on-Chip (SoC). Unlike the other Pulses generation on-chip debuggers theDoCD™ enables non-intrusive Digital signals generation debugging of a running application. It can halt, run, step into Gated timers or skip an instruction, read/write any contents of Sophisticated comparator microcontroller, including all registers, SFRs, including user Pulse width modulation defined peripherals, data and program memories. Pulse width measuring SPI – Master&Slave Serial Peripheral Interface DESIGN FEATURES Supports speeds up ¼ of system clock Software selectable polarity and phase of serial clock One global system clock SCK Synchronous reset System errors detection All asynchronous input signals are synchronized before Allows operation from a wide range of system clock internal use frequencies (build-in 5-bit timer) Copyright © 1999 - 2021 DCD - DCD-SEMI. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. Interrupt generation the global interrupt mask bit (I) in the CCR is cleared. Full-duplex UART – SCI Maskable interrupts are prioritized, according to default Standard non-return-to-zero format (NRZ) arrangement established during reset. When interrupt 8 or 9 bit data transfer condition occurs, an interrupt status flag is set, to indicate the Integrated baud rate generator condition. Noise, Overrun and Framing error detection I/O Ports – All ports are 8-bit general-purpose bi-directional IDLE and BREAK characters generation I/O system. The PORTA, PORTB, PORTC, PORTD data registers Wake-up block to recognize UART wake-up from IDLE have their corresponding data direction registers DDRA, condition DDRB, DDRC, DDRD, to control ports data flow. It assures that Three SCI related interrupts all DF6808’s ports have full I/O selectable registers. Writes to any ports pins cause data to be stored in the data registers. OPTIONAL PERIPHERALS If any port pins are configured as output, then data registers are driven out of those pins. Reads from port pins configured Optional peripherals (not included in the presented DF6808 as input, causes that input pin is read. If port pins Core) are also available. The optional peripherals can be is configured as output, during read data register is read. implemented upon customer’s request. Writes to any ports pins, not configured as outputs, do not cause data to be driven out of those pins, but the data is I2C bus controller – Master stored in the output registers. Thus, if the pins later become 7-bit and 10-bit addressing modes outputs, the last data written to port will be driven out NORMAL, FAST, HIGH speeds the port pins. Multi-master systems supported Timer & Compare – The programmable timer is based on Clock arbitration and synchronization free-running 16-bit counter, with a fixed divide by four User defined timings on I2C lines prescaler, plus input capture/output compare circuitry. The Wide range of system clock frequencies timer can be used for many purposes, including measuring Interrupt generation pulse length of two input signals and generating two output I2C bus controller – Slave signals. The timer has 16-bit architecture hence each specific NORMAL speed 100 kbs functional segment is represented by two 8-bit registers. FAST speed 400 kbs These registers contain the high and low byte of that HIGH speed 3400 kbs functional block. Accessing the low byte of a specific timer Wide range of system clock frequencies function, allows full control of that function, however, an User defined data setup time on I2C lines access of the high byte inhibits that specific timer function, Interrupt generation until the byte is also accessed. Each of the input-capture PWM – Pulse Width Modulation Timer channel has its own 16-bit time capture latch (input-capture Fixed-Point arithmetic coprocessor register) and each of the output-compare channel, has its own Floating-Point arithmetic coprocessor IEEE-754 16-bit compare register. Additional control bits permit standard single precision software to control the edge(s), that trigger each input- capture function and the automatic actions that result from UNITS SUMMARY output-compare functions. Although hardwired logic is included to automate many timer activities, this timer Control Unit – Performs the core synchronization and data architecture is mainly a software-oriented system. This flow control. This module manages execution ofstructure all is easily adaptable to a very wide range of instructions. The Control Unit also manages execution of STOP applications, although for some specific timing applications, it instruction and wakes the processor up from the STOP mode. is not as efficient, as a dedicated hardware. 13 Opcode Decoder – Performs an instruction opcode decoding Watchdog Timer – Consist of a free running Timer CLK/2 and the control functions for all other blocks. and control logic. It can be enabled by software, by writing ‘1’ ALU – Arithmetic Logic Unit performs the arithmetic and logic to the WDOG bit in MISC register ($000C). Once enabled, the operations, during execution of an instruction. It contains WDT Timer cannot be disabled by software. In addition, accumulator (A), Condition Code Register (CCREG), Index the WDOG bit acts as a reset mechanism for the WDT Timer. registers (X) and related logic like arithmetic unit, logic unit Writing logic one ‘1’ to the WDOG bit, clears Watchdog and multiplier. counter and inhibits Watchdog timeout. Bus Controller – Program Memory, Data Memory & SFR’s SCI – A full-duplex UART type, asynchronous system, using (Special Function Register) interface – controls access into the standard non return to zero (NRZ) format: 1 start bit, 8 or 9 program and data memories and special registers. It contains data bits and a 1 stop bit. The DF6805 resynchronizes the Program Counter (PC), Stack Pointer (SP) register and related receiver bit clock on all one to zero transitions in the bit logic. stream. Therefore, differences in baud rate, between Interrupt Controller – DF6808 extended IC has the sending device and the SCI, are not as likely to cause implemented 7-level interrupt priority control. The interrupt reception errors. Three logic samples are taken near requests may come from external pin (IRQ), as well as from the middle of data bit time and majority logic decides the particular peripherals. The DF6805 peripheral systems sense for the bit. For the start and stop bits, seven logic generate maskable interrupts, which are recognized only if samples are taken.