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Microsoft and Wind River Are Currently in a "Dead Heat" For
Microsoft and Wind River are currently in a "dead heat" for the top position in sales of embedded operating system software and toolkits, according to Stephen Balacco, embedded software analyst at Venture Development Corp. (VDC). In terms of the sale of real-time operating systems, on the other hand, Balacco said Wind River still maintains a "commanding market leadership position," but noted that Wind River has been "as challenged as any supplier in this market space over the last two years in the face of a slumping telecommunications industry, where they have been highly leveraged for sales, as well as [from] increased competition from royalty-free and Linux OS vendors making inroads." While not disclosing specific market share numbers publicly, VDC provided the following list indicating the market share position in terms of sales revenue, for the leading vendors in the embedded operating system market . 1. Microsoft 2. Wind River 3. Symbian 4. Palm 5. QNX 6. Enea Data 7. Green Hills Software 8. LynuxWorks 9. MontaVista Software 10. Accelerated Technology (Mentor Graphics) Included among key factors identified by VDC as impacting this market were . • Increased focus and emphasis on bundling integrated development solutions that minimize unnecessary and repetitive development and allow OEMs to focus on their core competencies in differentiating their product through the application; • Ability of OS vendors to adapt business models that are flexible in their pricing and terms and conditions in response to a changing set of market requirements spurred on by competitive market forces; and • A telecommunications market that continues to struggle has affected investments in new projects. -
Embedded Systems Building and Programming Embedded Devices
Embedded Systems Building and Programming Embedded Devices PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Tue, 29 May 2012 01:04:04 UTC Contents Articles Wikibooks:Collections Preface 1 Embedded Systems/Embedded Systems Introduction 3 Embedded Systems/Terminology 7 Microprocessor Basics 10 Embedded Systems/Microprocessor Introduction 10 Embedded Systems/Embedded System Basics 11 Embedded Systems/Microprocessor Architectures 13 Embedded Systems/Programmable Controllers 16 Embedded Systems/Floating Point Unit 18 Embedded Systems/Parity 20 Embedded Systems/Memory 21 Embedded Systems/Memory Units 24 Programming Embedded Systems 25 Embedded Systems/C Programming 25 Embedded Systems/Assembly Language 31 Embedded Systems/Mixed C and Assembly Programming 34 Embedded Systems/IO Programming 42 Embedded Systems/Serial and Parallel IO 43 Embedded Systems/Super Loop Architecture 44 Embedded Systems/Protected Mode and Real Mode 46 Embedded Systems/Bootloaders and Bootsectors 47 Embedded Systems/Terminate and Stay Resident 48 Real Time Operating Systems 49 Embedded Systems/Real-Time Operating Systems 49 Embedded Systems/Threading and Synchronization 51 Embedded Systems/Interrupts 54 Embedded Systems/RTOS Implementation 55 Embedded Systems/Locks and Critical Sections 57 Embedded Systems/Common RTOS 60 Embedded Systems/Common RTOS/Palm OS 63 Embedded Systems/Common RTOS/Windows CE 64 Embedded Systems/Common RTOS/DOS 64 Embedded Systems/Linux 65 Interfacing 68 Embedded Systems/Interfacing -
Computer Architectures
Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative .. -
ADSP-BF537 EZ-KIT Lite® Evaluation System Manual
ADSP-BF537 EZ-KIT Lite® Evaluation System Manual Revision 2.4, April 2008 Part Number 82-000865-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information ©2008 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Limited Warranty The EZ-KIT Lite evaluation system is warranted against defects in materi- als and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli- cation or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices icon bar and logo, VisualDSP++, the VisualDSP++ logo, Blackfin, the Blackfin logo, the CROSSCORE logo, EZ-KIT Lite, and EZ-Extender are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. Regulatory Compliance The ADSP-BF537 EZ-KIT Lite is designed to be used solely in a labora- tory environment. The board is not intended for use as a consumer end product or as a portion of a consumer end product. The board is an open system design which does not include a shielded enclosure and therefore may cause interference to other electrical devices in close proximity. -
Green Hills Software INTEGRITY-178B Separation Kernel, Comprising
CCEVS APPROVED ASSURANCE CONTINUITY MAINTENANCE REPORT ASSURANCE CONTINUITY MAINTENANCE REPORT FOR TM Green Hills Software INTEGRITY-178B Separation Kernel, comprising: INTEGRITY-178B Real Time Operating System (RTOS), version IN-ISP448-0100-SK_LMFWPCD2_Rel running on JSF PCD System Processor CCA, version 437140-007 with PowerPC, version 7448 Maintenance Report Number: CCEVS-VR-VID10119-2008a Date of Activity: 31 July 2009 References: Common Criteria document CCIMB-2004-02-009 “Assurance Continuity: CCRA Requirements”, version 1.0, February 2004; Impact Analysis Report, “High Assurance Security Products GHS JSF Panoramic Cockpit Display Separation Kernel Security Impact Analysis, DO-ISP448-0100- SK_LMFWPCD2SIA” High Assurance Security Products GHS Assurance Maintenance Plan, IN-INNNNN- 0101-HASPAMP Documentation Updated: Green Hills Software INTEGRITY-178B Separation Kernel developer evidence Assurance Continuity Maintenance Report: The vendor for the Green Hills Software INTEGRITY-178B Separation Kernel Operating System, submitted an Impact Analysis Report (IAR) to CCEVS for approval on 09 July 2009. The IAR is intended to satisfy requirements outlined in Common Criteria document CCIMB-2004-02-009, “Assurance Continuity: CCRA Requirements”, version 1.0, February 2004. In accordance with those requirements, the IAR describes the changes made to the certified TOE and the security impact of the changes. Changes to TOE: This maintenance activity consists of a functional and hardware platform modification to the Green Hills Software (GHS) -
MPC555 Interrupts by John Dunlop, Josef Fuchs, and Steve Mihalik Rev
Order this document by: MOTOROLA AN2109/D SEMICONDUCTOR APPLICATION NOTE MPC555 Interrupts by John Dunlop, Josef Fuchs, and Steve Mihalik Rev. 0, 26 July 2001 1 Introduction The MPC555 has numerous timers, peripherals and input pins that can generate interrupts. This appli- cation note describes how the interrupts work and how to write software for their initialization and ser- vice routines. Examples illustrate how interrupt handler routines written in assembler, C and even controlled by an operating system can have a dramatic variation in overhead. This overhead is almost entirely caused by the amount of context, (i.e., registers), saved and restored in the routine. Although this application note focuses on interrupts, the discussion of context saving and restoring ap- plies to other exceptions as well as other Motorola PowerPC™ microcontrollers. In addition, later MPC5xx microprocessors include an enhanced interrupt controller which has features to reduce laten- cy. A summary of these features, which are optional to use in these later microcontrollers is listed in Section Appendix B Enhanced Interrupt Controller Summary. 2 Background 2.1 Interrupts versus Exceptions Definitions of “interrupts” and “exceptions” are not always consistent in PowerPC™ literature. The fol- lowing definitions are used for this application note. Exceptions are events that change normal program flow and machine state. Some examples of excep- tions are reset, decrementer passing zero, system call instruction, various bus access errors, and even a software or hardware debugger. When an exception occurs, a short hardware context switch takes place and the processor branches to an address (exception vector) which is unique for each type of ex- ception. -
Research Purpose Operating Systems – a Wide Survey
GESJ: Computer Science and Telecommunications 2010|No.3(26) ISSN 1512-1232 RESEARCH PURPOSE OPERATING SYSTEMS – A WIDE SURVEY Pinaki Chakraborty School of Computer and Systems Sciences, Jawaharlal Nehru University, New Delhi – 110067, India. E-mail: [email protected] Abstract Operating systems constitute a class of vital software. A plethora of operating systems, of different types and developed by different manufacturers over the years, are available now. This paper concentrates on research purpose operating systems because many of them have high technological significance and they have been vividly documented in the research literature. Thirty-four academic and research purpose operating systems have been briefly reviewed in this paper. It was observed that the microkernel based architecture is being used widely to design research purpose operating systems. It was also noticed that object oriented operating systems are emerging as a promising option. Hence, the paper concludes by suggesting a study of the scope of microkernel based object oriented operating systems. Keywords: Operating system, research purpose operating system, object oriented operating system, microkernel 1. Introduction An operating system is a software that manages all the resources of a computer, both hardware and software, and provides an environment in which a user can execute programs in a convenient and efficient manner [1]. However, the principles and concepts used in the operating systems were not standardized in a day. In fact, operating systems have been evolving through the years [2]. There were no operating systems in the early computers. In those systems, every program required full hardware specification to execute correctly and perform each trivial task, and its own drivers for peripheral devices like card readers and line printers. -
MILS Architectural Approach Supporting Trustworthiness of the Iiot Solutions
MILS Architectural Approach Supporting Trustworthiness of the IIoT Solutions An Industrial Internet Consortium Whitepaper Rance J. DeLong (The Open Group); Ekaterina Rudina (Kaspersky) MILS Architectural Approach Context and Overview 1 Context and Overview ...................................................................................................... 4 1.1 Need for Trustworthy System Operation ............................................................................. 5 1.2 What is MILS today .............................................................................................................. 6 1.3 How MILS Addresses Safety ................................................................................................. 7 1.4 How MILS Addresses Security .............................................................................................. 8 1.5 How MILS Supports Reliability, Resilience, and Privacy ........................................................ 9 2 MILS Concepts .................................................................................................................. 9 2.1 Centralized vs Distributed Security Architecture .................................................................. 9 2.1.1 Domain Isolation .................................................................................................................................. 10 2.1.2 Isolation and Information Flow Control ............................................................................................... 11 2.1.3 Separation -
Selection of a New Hardware and Software Platform for Railway Interlocking
Selection of a new hardware and software platform for railway interlocking Arghya Kamal Bhattacharya School of Electrical Engineering Thesis submitted for examination for the degree of Master of Science in Technology. Espoo 27.04.2020 Supervisor Prof. Valeriy Vyatkin Advisor MSc. Tommi Kokkonen Copyright ⃝c 2020 Arghya Kamal Bhattacharya Aalto University, P.O. BOX 11000, 00076 AALTO www.aalto.fi Abstract of the master’s thesis Author Arghya Kamal Bhattacharya Title Selection of a new hardware and software platform for railway interlocking Degree programme Automation and Electrical Engineering Major Control, Robotics and Autonomous Systems Code of major ELEC3025 Supervisor Prof. Valeriy Vyatkin Advisor MSc. Tommi Kokkonen Date 27.04.2020 Number of pages 82+34 Language English Abstract The interlocking system is one of the main actors for safe railway transportation. In most cases, the whole system is supplied by a single vendor. The recent regulations from the European Union direct for an “open” architecture to invite new game changers and reduce life-cycle costs. The objective of the thesis is to propose an alternative platform that could replace a legacy interlocking system. In the thesis, various commercial off-the-shelf hardware and software products are studied which could be assembled to compose an alternative interlocking platform. The platform must be open enough to adapt to any changes in the constituent elements and abide by the proposed baselines of new standardization initiatives, such as ERTMS, EULYNX, and RCA. In this thesis, a comparative study is performed between these products based on hardware capacity, architecture, communication protocols, programming tools, security, railway certifications, life-cycle issues, etc. -
Microkernel Construction Introduction
Microkernel Construction Introduction Nils Asmussen 04/06/2017 1 / 28 Outline Introduction Goals Administration Monolithic vs. Microkernel Overview About L4/NOVA 2 / 28 Goals 1 Provide deeper understanding of OS mechanisms 2 Look at the implementation details of microkernels 3 Make you become enthusiastic microkernel hackers 4 Propaganda for OS research at TU Dresden 3 / 28 Administration Thursday, 4th DS, 2 SWS Slides: www.tudos.org ! Teaching ! Microkernel Construction Subscribe to our mailing list: www.tudos.org/mailman/listinfo/mkc2017 In winter term: Microkernel-based operating systems (MOS) Various labs 4 / 28 Outline Introduction Monolithic vs. Microkernel Kernel design comparison Examples for microkernel-based systems Vision vs. Reality Challenges Overview About L4/NOVA 5 / 28 Monolithic Kernel System Design u s Application Application Application e r k Kernel e r File Network n e Systems Stacks l m Memory Process o Drivers Management Management d e Hardware 6 / 28 Monolithic Kernel OS (Propaganda) System components run in privileged mode No protection between system components Faulty driver can crash the whole system Malicious app could exploit bug in faulty driver More than 2=3 of today's OS code are drivers No need for good system design Direct access to data structures Undocumented and frequently changing interfaces Big and inflexible Difficult to replace system components Difficult to understand and maintain Why something different? ! Increasingly difficult to manage growing OS complexity 7 / 28 Microkernel System Design Application -
Bdigdb User Manual
bdiGDB BDM interface for GNU Debugger PowerPCMPC8xx/MPC5xx User Manual Manual Version 1.16 for BDI2000 ©1997-2001 by Abatron AG bdiGDB for GNU Debugger, BDI2000 (MPC8xx/MPC5xx) User Manual 2 1 Introduction ................................................................................................................................. 3 1.1 BDI2000................................................................................................................................. 3 1.2 BDI Configuration .................................................................................................................. 4 2 Installation ................................................................................................................................... 5 2.1 Connecting the BDI2000 to Target......................................................................................... 5 2.1.1 Changing Target Processor Type ................................................................................. 7 2.2 Connecting the BDI2000 to Power Supply............................................................................. 8 2.2.1 External Power Supply................................................................................................. 8 2.2.2 Power Supply from Target System ............................................................................... 9 2.3 Status LED «MODE»........................................................................................................... 10 2.4 Connecting the BDI2000 to Host ........................................................................................ -
D68HC08 IP Core
2017 D68HC08 IP Core 8-bit Microcontroller v. 1.00 COMPANY OVERVIEW ♦ Two power saving modes: STOP, WAIT ♦ Fully synthesizable, static synchronous design with no inter- Digital Core Design is a leading IP Core provider and a Sys- nal tri-states tem-on-Chip design house. The company was founded in ♦ No internal reset generator or gated clock 1999 and since the very beginning has been focused on IP ♦ Scan test ready Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 cus- DELIVERABLES tomers and with more than 500 hundred licenses sold to ♦ Source code: companies like Intel, Siemens, Philips, General Electric, ● VHDL Source Code or/and Sony and Toyota. Based on more than 70 different archi- ● VERILOG Source Code or/and tectures, starting from serial interfaces to advanced micro- ● Encrypted, or plain text EDIF controllers and SoCs, we are designing solutions tailored to ♦ VHDL & VERILOG test bench environment ● Active-HDL automatic simulation macros your needs. ● ModelSim automatic simulation macros ● Tests with reference responses I P C O R E OVERVIEW ♦ Technical documentation ● Installation notes The D68HC08 is an advanced 8-bit MCU IP Core with highly ● HDL core specification sophisticated, on-chip peripheral capabilities. The ● Datasheet D68HC08 soft core is binary and cycle - compatible with ♦ Synthesis scripts ♦ Example application the industry standard Motorola 68HC08 8-bit microcon- ♦ Technical support troller. In the standard configuration, the Core has inte- ● IP Core implementation support grated on-chip major peripheral functions. The D68HC08 ● 3 months maintenance Microcontroller Core contains a full-duplex UART - Asyn- ● Delivery of the IP Core and documentation updates, minor and major versions changes chronous Serial Communication Interface (SCI) and a Syn- ● Phone & email support chronous Serial Peripheral Interface (SPI).