D68HC08 IP Core

2017 D68HC08 IP Core

COMPANY OVERVIEW ♦ Two power saving modes: STOP, WAIT ♦ Fully synthesizable, static synchronous design with no inter- Digital Core Design is a leading IP Core provider and a Sys- nal tri-states tem-on-Chip design house. The company was founded in ♦ No internal reset generator or gated clock 1999 and since the very beginning has been focused on IP ♦ Scan test ready Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 cus- DELIVERABLES tomers and with more than 500 hundred licenses sold to ♦ Source code: companies like Intel, Siemens, Philips, General Electric, ● VHDL Source Code or/and Sony and Toyota. Based on more than 70 different archi- ● VERILOG Source Code or/and tectures, starting from serial interfaces to advanced micro- ● Encrypted, or plain text EDIF controllers and SoCs, we are designing solutions tailored to ♦ VHDL & VERILOG test bench environment ● Active-HDL automatic simulation macros your needs. ● ModelSim automatic simulation macros ● Tests with reference responses I P C O R E OVERVIEW ♦ Technical documentation ● Installation notes The D68HC08 is an advanced 8-bit MCU IP Core with highly ● HDL core specification sophisticated, on-chip peripheral capabilities. The ● Datasheet D68HC08 soft core is binary and cycle - compatible with ♦ Synthesis scripts ♦ Example application the industry standard Motorola 68HC08 8-bit microcon- ♦ Technical support troller. In the standard configuration, the Core has inte- ● IP Core implementation support grated on-chip major peripheral functions. The D68HC08 ● 3 months maintenance Microcontroller Core contains a full-duplex UART - Asyn- ● Delivery of the IP Core and documentation updates, minor and major versions changes chronous Serial Communication Interface (SCI) and a Syn- ● Phone & email support chronous Serial Peripheral Interface (SPI). Two 16-bit, flexible timing systems with input capture lines, output- LICENSING compare lines and PWM functionality. A self-monitoring circuitry is included on-chip, to protect against system Comprehensible and clearly defined licensing methods errors. A computer operating properly (COP) watchdog without royalty-per-chip fees make use of our IP Cores system protects against software failures. An illegal op- easy and simple. code detection circuit provides a non-maskable interrupt, Single-Site license option – dedicated to small and middle if an illegal opcode is detected. Two software-controlled sized companies, which run their business in one place. power-saving modes - WAIT and STOP are available to Multi-Site license option – dedicated to corporate custom- conserve additional power. These modes make the ers, who operate at several locations. The licensed product D68HC08 IP Core especially attractive for automotive and can be used in selected company branches. battery-driven applications. The D68HC08 is fully customi- In all cases the number of IP Core instantiations within a zable - it is delivered in an exact configuration to meet project and the number of manufactured chips are unlim- users’ requirements. It includes fully automated test ited. The license is royalty-per-chip free. There are no re- bench with complete set of tests, allowing easy package strictions regarding the time of use. validation at each stage of SoC design flow. Each DCD's There are two formats of the delivered IP Core: D68XX Core has a built-in support for DCD Hardware De- VHDL or Verilog RTL synthesizable HDL Source code TM bug System called DoCD . It's a real-time hardware de- FPGA EDIF/NGO/NGD/QXP/VQM Netlist bugger, which provides debugging capability of a whole TM System-on-Chip (SoC). DoCD provides non-intrusive PERIPHERALS debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of a micro- The peripherals listed below are implemented controller, including all registers, SFRs, including user de- in a standard configuration of the D68HC08. fined peripherals, data and program memories. ♦ DoCDTM On-Chip Debugger ● Processor execution control ● Read, write all processor contents CPU FEATURES ● Hardware execution breakpoints ● Three wire communication interface ♦ Software compatible with standard 68HC08 ♦ I/O Ports ♦ Cycle compatible with the original implementation ♦ Interrupt Controller ♦ Pin-out and memory interface identical to MC68H08 Micro- ● Dedicated vector and interrupt priority for each interrupt source controllers ♦ 16-bit Timer Interface Modules TIMA and TIMB ♦ Optional enhanced memory interface with De-multiplexed ● Four input capture/compare channels

Address/Data Bus to allow easy integration with external ● Buffered and not buffered PWM

memories ● Programmable TIM clock input ● Free-running or modulo up-count operation ♦ Interrupt Controller ● TIM counter stop and reset bits

modaBUS modbController

♦ Programmable Interrupt Timer (PIT) BLOCK DIAGRAM ● Programmable PIT clock input ● Free-running or modulo up-count operation ● PIT counter stop and reset bits clk ♦ Full-duplex UART - SCI reset Opcode Memory Decoder ● Standard non-return-to-zero format (NRZ) controller ● 8 or 9 bit data transfer ● Integrated BAUD Rate generator ● Enhanced receiver data sampling technique Control porta halt ● Noise, Overrun and Framing errors detection Unit portb ● IDLE and BREAK characters generation I/O portc ● Wake-up block to recognize UART wakeup from IDLE Ports ● Three SCI Related interrupts portd ♦ SPI – Master and Slave Serial Peripheral Interface irq Interrupt porte Controller ● Mode fault error portf ● Write collision error ● Software selectable polarity and phase of serial clock SCK ● System errors detection PIT ● Allows operation from a wide range of system clock frequencies Programmable Timer Interrupt A ● Interrupt generation Timer

OPTIONAL PERIPHERALS Timer Optional peripherals (not included in the presented B D68HC08 Microcontroller Core) are also available. The optional peripherals can be implemented upon customer’s adcdatai request. SCI Unit ADC adcdataoi Controller adcclock ♦ PWM – Pulse Width Modulation Timer/Counter with up to adccs four 8-bit or two 16-bit PWM channels esi ♦ Memory extension unit and Chip select EEPROM SPI Unit eso ♦ I2C Master & Slave bus controllers Controller esck ● Master operation ecs ● Multi-master systems supported ● Performs arbitration and clock synchronization clkdocd DoCDTM ● Interrupt generation ALU docddatai ● Supports speed up to 3,4Mb/s (standard, fast & HS modes) Debugger docddatao ● Allows operation from a wide range of clock frequencies (build-in docdclk 8-bit timer) ● User-defined timing ♦ Floating-Point Arithmetic Coprocessor (DFPAU) IEEE-754 standard single precision PINS DESCRIPTION ● FADD, FSUB - addition, subtraction PIN TYPE DESCRIPTION ● FMUL, FDIV- multiplication, division clk input Global system clock ● FSQRT- square root reset input Power on reset vector fetch ● FUCOM - compare irq input Interrupt input ● FCHS - change sign halt output Stop CLK generator during STOP ● FABS - absolute value portx in/out Ports I/O pins shared with peripheral functions ♦ Floating-Point Math Coprocessor (DFPMU) - IEEE-754 stand- D68HC11 Microcontroller pins ard single precision real, word and short integers adcdatai input Serial ADC data input ● FADD, FSUB- addition, subtraction adcdatao output Serial Data output ● FMUL, FDIV- multiplication, division adcclock output Serial Clock to external ADC ● FSQRT- square root adccs output Chip Select to external ADC ● FUCOM- compare Optional external ADC Controller pins ● FCHS - change sign ● FABS - absolute value esi input Serial EEPROM Data input ● FSIN, FCOS- sine, cosine eso output Serial EEPROM Data output ● FPTAN, FPATAN- tangent, arcs tangent esck output Serial EEPROM Clock ♦ Additional special internal interrupt dedicated for DFPAU or ecs output EEPROM Chip Select DFPMU Optional external EEPROM controller pins clkdocd input DoCDTM clock input docddatai input DoCDTM serial Data input DESIGN FEATURES docddatao output DoCDTM Serial Data Output docdclk output DoCDTM Serial Clock Output ♦ One global system clock DoCD debugger interface pins ♦ Synchronous reset

♦ All asynchronous input signals are synchronized before inter-

nal use

UNITS SUMMARY tem. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data Control Unit - Performs the core synchronization and data lines. SPI data are simultaneously transmitted and received. flow control. This module manages execution of all instruc- SPI system is flexible enough to interface directly with numer- tions. The Control Unit also manages execution of STOP in- ous standard product peripherals, from several manufactur- struction and waking-up the processor from the STOP mode. ers. Clock control logic allows a selection of clock polarity and Opcode Decoder - Performs an instruction opcode decoding a choice of two fundamentally different clocking protocols, to and the control functions for all other blocks. accommodate most available synchronous serial peripheral ALU - Arithmetic Logic Unit performs the arithmetic and logic devices. Error-detection logic is included to support interpro- operations during execution of an instruction. It contains cessor communications. A write-collision detector indicates accumulator (A, B), Condition Code Register (CCREG), Index when an attempt is made to write data to the serial shift registers X and related logic like arithmetic unit, logic unit, register, while a transfer is in progress. A multiple-master multiplier and divider. mode-fault detector automatically disables SPI output drivers, Bus Controller – Program Memory, Data Memory & SFR’s if more than one SPI devices simultaneously attempt to be- (Special Function Register) interface controls access into the come a bus master. program and data memories and special registers. It contains I/O Ports - All ports are 8-bit general-purpose bi-directional Program Counter (PC), Stack Pointer (SP) register and related I/O system. The ports data registers have their corresponding logic. data direction registers (DDR), to control ports data flow. It Interrupt Controller –The interrupt requests may come from assures that all D68HC08’s ports have full I/O selectable regis- external pins (IRQ) as well as from particular peripherals. The ters. Writes to any ports pins cause data to be stored in the D68HC08 peripheral systems generate maskable interrupts, data registers. If any port pins are configured as output, then which are recognized only if the global interrupt mask bit (I) in data registers are driven out of those pins. Reads from port the CCR is cleared. Maskable interrupts are prioritized accord- pins configured as input, causes the input pin to be read. If ing to default arrangement, established during reset. When port pins is configured as output, during read data register interrupt condition occurs, an interrupt status flag is set to is read. Writes to any ports pins not configured as outputs, indicate the condition. does not cause data to be driven out of those pins, but the Timer, Compare Capture & COP Watchdog – This timer sys- data is stored in the output registers. Thus, if the pins later tem is based on a free-running 16-bit counter with a pro- become outputs, the last data written to port will be driven grammable prescaler. A timer overflow function allows soft- out of the port pins. ware to extend the timing capability of the system, beyond ADCCTRL – External ADC Controller is used as an interface the 16-bit range of the counter. Input-capture function is used between D68HC08 internal registers and external seri- to automatically record the time, when a selected transition is al/parallel ADC converter. This module has several different detected at a respective timer input pin. Output-compare options, so its details are described in separate document. function is included for generating output signals, or for tim- EEPROMCTRL – External Serial EEPROM controller. It manages ing software delays. Since the input-capture and output- data exchange between D68HC08 and external EEPROM. compare functions may not be familiar to all users, these During initialization, copies contents of whole external concepts are explained in greater detail. EEPROM, to internal EEPRAM (EEPROM Mirror implemented SCI - The SCI is a full-duplex UART type asynchronous system, in standard parallel RAM). This module has several different using standard, non-return to zero (NRZ) format: 1 start bit, 8 options, so its details are described in separate document. or 9 data bits and a 1 stop bit. The D68HC08 resynchronizes DoCDTM - Debug Unit – it’s a real-time hardware debugger, the receiver bit clock on all one to zero transitions in the bit providing debugging capability of a whole SoC system. Unlike stream. Therefore, the differences in baud rate between the other on-chip debuggers DoCD™ provides non-intrusive de- sending device and the SCI are not as likely to cause reception bugging of running application. It can halt, run, step into or errors. Three logic samples are taken near the middle of data skip an instruction, read/write any contents of microcontrol- bit time and majority logic decides the sense for the bit. ler, including all registers, internal, external, program memo- The receiver also has the ability to enter a temporary standby ries and all SFRs, including user defined peripherals. Hardware mode (called receiver wakeup), to ignore messages intended breakpoints can be set and controlled on program memory, for a different receiver. Logic automatically wakes up the internal and external data memories, as well as on SFRs. receiver in time to see the first character of the next message. Hardware breakpoint is executed, if any write/read occurs at This wakeup feature greatly reduces CPU overhead in multi- particular address, with certain data pattern or without pat- drop SCI networks. The SCI transmitter can produce queued tern. The DoCDTM system includes three-wire interface and characters of idle (whole characters of all logic 1) and break complete set of tools, to communicate and work with core in (whole characters of all logic 0). In addition to the usual real time debugging. It is built as scalable unit and some fea- transmit data register empty (TDRE) status flag, this SCI also tures can be turned off by the user, to save silicon and reduce provides a transmit complete (TC) indication that can be used power consumption. When debugger is not used, it is auto- in applications with a modem. matically switched to power save mode. Finally, when debug SPI Unit – it’s a fully configurable master/slave Serial Periph- option is no longer used, whole debugger is turned off. The eral Interface, which allows user to configure polarity and separate CLKDOCD clock line allows the debugger to operate, phase of serial clock signal SCK. It allows the microcontroller

while the CPU is in STOP mode and the major clock line CLK is to communicate with serial peripheral devices. It is also capa- stopped.

ble of interprocessor communications, in a multi-master sys-

D68HC11 AND DF6811 MICROCONTROLLERS OVERVIEW The main features of each DF68XX family member have been summarized in the table below. It gives a brief member charac- teristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (includ-

ing listed above and others) and request the core modifications.

Design

Capture

ASICgates

–

O Ports O

Speedacceleration PhysicalLinear memory space PagedData Memory space MotorolaMemory E pansionLogic RealInterrupt Time DataPointers READYand for Prg. Data memories Compare MainSystem Timer SCI(UART) I SPIM/S Interface WatchdogTimer Pulseaccumulator Interfacefor additionalSFRs DoCDDebugger Size

D6802 1 64k 64k ------3 900 D6803 1 64k 64k ------6 000 D6809 1 64k 64k ------9 000

DF6805 4.1 64k 64k - - - * 1/1* 1* * 4 + * - 6 700 D68HC05 1.0 64k 64k - - - * 1/1* 1* * 4 + -* - 6 700 DF6808 3.2 64k 64k - - - * 2/2* 1* * 4 * - 8 900 D68HC08 1.0 64k 64k - - - * 2/2* 1* * 4 * - 8 900

D68HC11E 1.0 64k 64k - 1* * 5/3* 1* * 4 12 000 D68HC11F 1.0 64K 64K - 1* * 5/3* 1* * 7 13 500 D68HC11KW1 1.0 1M 1M 1* * 13/6* 3* * 10 21 000 D68HC11K 1.0 1M 1M 1* * 5/3* 2* * 7 16 000 DF6811E 4.4 64k 64k - 1* * 5/3* 1* * 4 * * * 12 000 DF6811F 4.4 64k 64k - 1* * 5/3* 1* * 4 * * * 13 000 DF6811K 4.4 1M 1M 1* * 5/3* 2* * 7 16 000

D68HCXX family of High Performance Microcontroller Cores +optional *configurable

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