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Embedded Systems Building and Programming Embedded Devices
Embedded Systems Building and Programming Embedded Devices PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Tue, 29 May 2012 01:04:04 UTC Contents Articles Wikibooks:Collections Preface 1 Embedded Systems/Embedded Systems Introduction 3 Embedded Systems/Terminology 7 Microprocessor Basics 10 Embedded Systems/Microprocessor Introduction 10 Embedded Systems/Embedded System Basics 11 Embedded Systems/Microprocessor Architectures 13 Embedded Systems/Programmable Controllers 16 Embedded Systems/Floating Point Unit 18 Embedded Systems/Parity 20 Embedded Systems/Memory 21 Embedded Systems/Memory Units 24 Programming Embedded Systems 25 Embedded Systems/C Programming 25 Embedded Systems/Assembly Language 31 Embedded Systems/Mixed C and Assembly Programming 34 Embedded Systems/IO Programming 42 Embedded Systems/Serial and Parallel IO 43 Embedded Systems/Super Loop Architecture 44 Embedded Systems/Protected Mode and Real Mode 46 Embedded Systems/Bootloaders and Bootsectors 47 Embedded Systems/Terminate and Stay Resident 48 Real Time Operating Systems 49 Embedded Systems/Real-Time Operating Systems 49 Embedded Systems/Threading and Synchronization 51 Embedded Systems/Interrupts 54 Embedded Systems/RTOS Implementation 55 Embedded Systems/Locks and Critical Sections 57 Embedded Systems/Common RTOS 60 Embedded Systems/Common RTOS/Palm OS 63 Embedded Systems/Common RTOS/Windows CE 64 Embedded Systems/Common RTOS/DOS 64 Embedded Systems/Linux 65 Interfacing 68 Embedded Systems/Interfacing -
Computer Architectures
Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative .. -
COSMIC C Cross Compiler for Motorola 68HC11 Family
COSMIC C Cross Compiler for Motorola 68HC11 Family COSMIC’s C cross compiler, cx6811 for the Motorola 68HC11 family of microcontrollers, incorporates over twenty years of innovative design and development effort. In the field since 1986 and previously sold under the Whitesmiths brand name, cx6811 is reliable, field-tested and incorporates many features to help ensure your embedded 68HC11 design meets and exceeds performance specifications. The C Compiler package for Windows includes: COSMIC integrated development environment (IDEA), optimizing C cross compiler, macro assembler, linker, librarian, object inspector, hex file generator, object format converters, debugging support utilities, run-time libraries and a compiler command driver. The PC compiler package runs under Windows 95/98/ME/NT4/2000 and XP. Complexity of a more generic compiler. You also get header Key Features file support for many of the popular 68HC11 peripherals, so Supports All 68HC11 Family Microcontrollers you can access their memory mapped objects by name either ANSI C Implementation at the C or assembly language levels. Extensions to ANSI for Embedded Systems ANSI / ISO Standard C Global and Processor-Specific Optimizations This implementation conforms with the ANSI and ISO Optimized Function Calling Standard C specifications which helps you protect your C support for Internal EEPROM software investment by aiding code portability and reliability. C support for Direct Page Data C Runtime Support C support for Code Bank Switching C runtime support consists of a subset of the standard ANSI C support for Interrupt Handlers library, and is provided in C source form with the binary Three In-Line Assembly Methods package so you are free to modify library routines to match User-defined Code/Data Program Sections your needs. -
M.Tech –Embedded System Design SEMESTER-I S.NO CODE
CURRICULUM DEPARTMENT OF ELECTRONICS AND COMMUNICATION BRANCH: M.Tech –Embedded System Design SEMESTER-I S.NO CODE SUBJECT NAME L T P C 1 PMA105 Applied Mathematics for Electronics Engineers 3 1 0 4 2 PED101 Microcontroller Based System Design 3 0 0 3 3 PED102 Embedded Systems 3 0 0 3 4 PAE102 Advanced Digital System Design 3 0 0 3 5 PED1E1 Elective-I 3 0 0 3 6 PED1L1 Embedded System Design Lab-I 0 0 4 2 TOTAL CONTACT HOURS- 20 18 SEMESTER-II 1 PED101 ASIC Design 3 0 0 3 2 PED202 Software Technology for Embedded System 3 0 0 3 3 PED203 Real Time Systems 3 0 0 3 4 PED2E2 Elective-II 3 0 0 3 5 PED2E3 Elective-III 3 0 0 3 6 PED2L2 Embedded System Design Lab -II 0 0 4 2 TOTAL CONTACT HOURS -19 17 SEMESTER-III 1. PED3E4 Elective-IV 3 0 0 3 2. PED3E5 Elective-V 3 0 0 3 3. PED3E6 Elective-VI 3 0 0 3 4. PED3P1 Project work phase-I 0 0 12 6 TOTAL CONTACT HOURS-21 15 SEMESTER-IV 1 PED4P2 Project work phase-II 0 0 24 12 TOTAL CONTACT HOURS-24 12 TOTAL CREDITS FOR THE PROGRAMME-62 LIST OF ELECTIVES 1 PED 001 Design of Embedded System 3 0 0 3 2 PED 002 Embedded Control System 3 0 0 3 3 PED 003 Computer Vision and Image Understanding 3 0 0 3 4 PED 004 Distributed Embedded Computing 3 0 0 3 5 PED 005 Design of Digital Control System 3 0 0 3 6 PED 006 Crypto Analytic Systems 3 0 0 3 7 PED 007 Intelligent Embedded Systems 3 0 0 3 8 PAE 006 Artificial Intelligence and Expert systems 3 0 0 3 9 PED102 Embedded systems 3 0 0 3 10 PED201 ASIC Design 3 0 0 3 11 PVL002 Low power VLSI Design 3 0 0 3 12 PVL003 Analog VLSI Design 3 0 0 3 13 PVL004 VLSI Signal processing -
MPC555 Interrupts by John Dunlop, Josef Fuchs, and Steve Mihalik Rev
Order this document by: MOTOROLA AN2109/D SEMICONDUCTOR APPLICATION NOTE MPC555 Interrupts by John Dunlop, Josef Fuchs, and Steve Mihalik Rev. 0, 26 July 2001 1 Introduction The MPC555 has numerous timers, peripherals and input pins that can generate interrupts. This appli- cation note describes how the interrupts work and how to write software for their initialization and ser- vice routines. Examples illustrate how interrupt handler routines written in assembler, C and even controlled by an operating system can have a dramatic variation in overhead. This overhead is almost entirely caused by the amount of context, (i.e., registers), saved and restored in the routine. Although this application note focuses on interrupts, the discussion of context saving and restoring ap- plies to other exceptions as well as other Motorola PowerPC™ microcontrollers. In addition, later MPC5xx microprocessors include an enhanced interrupt controller which has features to reduce laten- cy. A summary of these features, which are optional to use in these later microcontrollers is listed in Section Appendix B Enhanced Interrupt Controller Summary. 2 Background 2.1 Interrupts versus Exceptions Definitions of “interrupts” and “exceptions” are not always consistent in PowerPC™ literature. The fol- lowing definitions are used for this application note. Exceptions are events that change normal program flow and machine state. Some examples of excep- tions are reset, decrementer passing zero, system call instruction, various bus access errors, and even a software or hardware debugger. When an exception occurs, a short hardware context switch takes place and the processor branches to an address (exception vector) which is unique for each type of ex- ception. -
Bdigdb User Manual
bdiGDB BDM interface for GNU Debugger PowerPCMPC8xx/MPC5xx User Manual Manual Version 1.16 for BDI2000 ©1997-2001 by Abatron AG bdiGDB for GNU Debugger, BDI2000 (MPC8xx/MPC5xx) User Manual 2 1 Introduction ................................................................................................................................. 3 1.1 BDI2000................................................................................................................................. 3 1.2 BDI Configuration .................................................................................................................. 4 2 Installation ................................................................................................................................... 5 2.1 Connecting the BDI2000 to Target......................................................................................... 5 2.1.1 Changing Target Processor Type ................................................................................. 7 2.2 Connecting the BDI2000 to Power Supply............................................................................. 8 2.2.1 External Power Supply................................................................................................. 8 2.2.2 Power Supply from Target System ............................................................................... 9 2.3 Status LED «MODE»........................................................................................................... 10 2.4 Connecting the BDI2000 to Host ........................................................................................ -
Experience of Teaching the Pic Microcontrollers
Session 1520 EXPERIENCE OF TEACHING THE PIC MICROCONTROLLERS Han-Way Huang, Shu-Jen Chen Minnesota State University, Mankato, Minnesota/ DeVry University, Tinley Park, Illinois Abstract This paper reports our experience in teaching the Microchip 8-bit PIC microcontrollers. The 8-bit Motorola 68HC11 microcontroller has been taught extensively in our introductory microprocessor courses and used in many student design projects in the last twelve years. However, the microcontroller market place has changed considerably in the recent years. Motorola stopped new development for the 68HC11 and introduced the 8- bit 68HC908 and the 16-bit HCS12 with the hope that customers will migrate their low- end and high-end applications of the 68HC11 to these microcontrollers, respectively. On the other hand, 8-bit microcontrollers from other vendors also gain significant market share in the last few years. The Microchip 8-bit microcontrollers are among the most popular microcontrollers in use today. In addition to the SPI, USART, timer functions, and A/D converter available in the 68HC11 [6], the PIC microcontrollers from Microchip also provide peripheral functions such as CAN, I2C, and PWM. The controller-area- network (CAN) has been widely used in automotive and process control applications. The Inter-Integrated Circuit (I2C) has been widely used in interfacing peripheral chips to the microcontroller whereas the Pulse Width Modulation (PWM) function has been used extensively in motor control. After considering the change in microcontrollers and the technology evolution, we decided to teach the Microchip 8-bit microcontrollers. 1 Several major issues need to be addressed before a new microcontroller can be taught: textbook, demo boards, and development software and hardware tools. -
D68HC08 IP Core
2017 D68HC08 IP Core 8-bit Microcontroller v. 1.00 COMPANY OVERVIEW ♦ Two power saving modes: STOP, WAIT ♦ Fully synthesizable, static synchronous design with no inter- Digital Core Design is a leading IP Core provider and a Sys- nal tri-states tem-on-Chip design house. The company was founded in ♦ No internal reset generator or gated clock 1999 and since the very beginning has been focused on IP ♦ Scan test ready Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 cus- DELIVERABLES tomers and with more than 500 hundred licenses sold to ♦ Source code: companies like Intel, Siemens, Philips, General Electric, ● VHDL Source Code or/and Sony and Toyota. Based on more than 70 different archi- ● VERILOG Source Code or/and tectures, starting from serial interfaces to advanced micro- ● Encrypted, or plain text EDIF controllers and SoCs, we are designing solutions tailored to ♦ VHDL & VERILOG test bench environment ● Active-HDL automatic simulation macros your needs. ● ModelSim automatic simulation macros ● Tests with reference responses I P C O R E OVERVIEW ♦ Technical documentation ● Installation notes The D68HC08 is an advanced 8-bit MCU IP Core with highly ● HDL core specification sophisticated, on-chip peripheral capabilities. The ● Datasheet D68HC08 soft core is binary and cycle - compatible with ♦ Synthesis scripts ♦ Example application the industry standard Motorola 68HC08 8-bit microcon- ♦ Technical support troller. In the standard configuration, the Core has inte- ● IP Core implementation support grated on-chip major peripheral functions. The D68HC08 ● 3 months maintenance Microcontroller Core contains a full-duplex UART - Asyn- ● Delivery of the IP Core and documentation updates, minor and major versions changes chronous Serial Communication Interface (SCI) and a Syn- ● Phone & email support chronous Serial Peripheral Interface (SPI). -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Chapter 7. Microcontroller Implementation Consideration
Chapter 7. Microcontroller Implementation Consideration The overall performance of wheel slip control systems have been limited in the past primarily by the unavailability of low cost, flexible, high-speed electronic technology. The application of high speed digital microcontrollers in anti-lock brake systems allows increased computational capabilities and control performance. In this section, a Motorola 68HC11 microcontroller is evaluated for its suitability for the anti-lock brake control application. This family of microcontroller have been used in FLASH lab, Virginia Tech Center for Transportation Research for evaluation of the automatic highway system concepts and technologies (Kachroo, 1995). Due to the unavailability of the small-size electromagnetic brakes, we have not implemented the electromagnetic brakes and its control system on the small-scale vehicle in FLASH lab. But the digital control algorithm of the possible ABS system is evaluated and features of 68HC11 and alternative families of microcontrollers are evaluated to estimate their suitability for ABS application. For regular friction brakes, modulated brake torque can be calculated and applied to every individual wheel because there is a possibility that different wheels are on different road surfaces. On the other hand, due to the location of electromagnetic brakes, its output torque must be applied to all four wheels in an overall base. The anti-lock brake system discussed in this section takes both situations into consideration. 66 7.1. Motorola 68HC11 Microcontroller (Motorola, 1991) The high-density complementary metal-oxide semiconductor (HCMOS) 68HC11 is an advanced 8-bit microcontroller with sophisticated on-chip peripheral capabilities. The HCMOS technology combines smaller size and higher speeds with the lower power and high noise immunity of CMOS. -
ZAP Cross Debuggers for Motorola Microcontrollers
ZAP Cross Debuggers for Motorola Microcontrollers ZAP is a family of full-featured C and assembly language source-level debuggers designed to give Motorola embedded microcontroller developers a consistent and productive debugging environment across multiple target processors. Key Features: ZAP Addresses Your Debugging Needs At Each Stage of Your Project Provides a Portable Debugging Environment, ZAP’s multiple configurations are designed to address your debugging needs as your project moves from the design stage Debugger for Each Stage of Your Project, to final integration and test; ZAP configurations supported C and Assembler Source-level Debugging, are: software simulation, target monitor, background debug mode, and in-circuit emulator. Each configuration ANSI C Debugging, gives you essentially the same user interface, thus vastly Array and Structure Explorer, improving your productivity, but each addresses a different stage of your project. Debug Fully Optimized Code, Easy-to-use Graphical User Interface, C and Assembler Source-level Debugging If your source code is written in C, you want to debug at the C Extensive Program Control & Analysis Features, level; if parts of your source code are written in assembly Graphical Performance Analysis, language you want to debug at the assembly language level. ZAP automatically supports both modes without any special Code and Data Coverage, options or settings, so you always see your original source C Level Trace, code in the Source window. If you are debugging at the C level, you can activate a Disassembly window that shows you Robust Script language, the corresponding assembly language code for each line of C source. Automated Testing, Real-Time BDM debugging, ANSI C Debugging Hardware Breakpoint support, ZAP provides point and click access to any C object or construct including enums, bit fields, strings, doubles/floats, FLASH and EEPROM Programming, structures and stack frames. -
A Self-Optimizing Embedded Microprocessor Using a Loop Table
A Self-Optimizing Embedded Microprocessor using a Loop Table for Low Power Frank Vahid* and Ann Gordon-Ross Department of Computer Science and Engineering University of California, Riverside http://www.cs.ucr.edu/~vahid {vahid/ann}@cs.ucr.edu *Also with the Center for Embedded Computer Systems at UC Irvine. ABSTRACT additional transistor capacity is to reduce power in a mass- We describe an approach for a microprocessor to tune itself to its produced embedded microprocessor by, adding tunable fixed application to reduce power in an embedded system. We components to the architecture, and extra circuitry that tunes those define a basic architecture and methodology supporting a components to the particular fixed application. Essentially, the microprocessor self-optimizing mode. We also introduce a loop microprocessor is self-optimizing. A designer using such a part table as a tunable component, although self-optimization can be gets reduced power through some customization while still getting done for other tunable components too. We highlight the benefits of a mass-produced IC. experimental results illustrating good power reductions with no In this paper, we describe a basic architecture and methodology performance penalty. for a self-optimizing microprocessor that tunes itself to an application to reduce power. Such a microprocessor represents an Keywords instance of post-fabrication tuning [16], namely tuning done after System-on-a-chip, self-optimizing architecture, embedded an IC has been fabricated. We introduce self-profiling circuitry systems, parameterized architectures, cores, low-power, tuning, and a designer-controlled self-optimization mode, in which platforms. configurable architectural components would be tuned based on an application’s profile.