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SESSION I: Digital Memories Y

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SESSION I: Digital Memories Y WEDNESDAY, FEBRUARY 20, 1963. .UNIVERSITY OF PENNSYLVANIA-IRVINE AUDlTORlUM . .9:00-11:45 kt#- SESSION I: Digital Memories WAM 1.4: Electrical Delayline Memory System Using Tunnel Diodes H. H. Harris and W. 0. Pricer Components Div., IBM Corporation Poughkeepsie, N. Y. THIS PAPER will describe a novel means of achieving fast clock period. Information is stored in a pulse train intra- high-capacityinformation storage with electricaldelay duced at the tunnel diode. These pulses travel down the linesand simple regeneration circuitry. Information length of thedelay line to the termination, a low storage at bit rates as high as 800 Mc has been demon- impedance relative to the cable, where they are inverted strated. One-hundred and fifty bits have been stored on by being reflected. The entire pulse train then traverses a singlea coaxial delay line. The simplicity of the the line toward the tunnel diode. At the tunnel diode the regeneratingcircuitry in conjunction withetched-wire pulse train is combined withthe bit-rate clock signal. delaylines makes largearrays of thesedelay lines The combined signal is sufficient totrigger the tunnel feasible. Any linein the array may be selected for diode circuit into its opposite stable state. The presence input/output purposes withoutdisturbing information of the bit-rate clock serves to re-time the stored pulses, storedin theother lines. Gain,pulse shaping, and re- andthe amplifying action of thetunnel diode circuit clocking areall provided withthe use of only one serves to reshape the stored pulses. It can be seen that tunnel diode per line. this process invertsthe pulse trainevery round trip. The necessary drive current is small (10 to 20 ma) and This property of the cell allows information to be erased the sensesignal islarge (2 to 3 n~a).Such favorable and written with monopolar control drives and accessed terminal conditionsfacilitate simple, fast, peripheral through singlea connecting diode, even with two circuits. The serial-in-time nature of the storage makes coordinates of selection. This simplicity of selection and for further simplification of the peripheral circuits; there the increased storage capacity offered by non-return-to- is only one sense amplifier for the entire memory. Even zero are the principle advantages over previous systems at highspeeds, two-dimensional word selection may be proposed by Goto and used. Typical Operative Model Basic Memory Cell A fully operative model, which contains all the circuits The basic memory cell is shown in Figure 1; it consists for a complete system, includingcircuits for parallel of oneprinted electrical delay line, tunnel diode, input and output andcommutation from serial to parallel conventional diode, resistor, and a printed capacitor, operation, has been constructed.This model isrepre- printedwith the delayline. Each cell maystore many sentative of a 256-word, 8 bits-per-wordsystem, but is bits; for instance, all the bits of a given word. All cells partially populated. It employs a 115-Mc clock and has will regenerate continuouslystored information inde- a complete read/write cycle time of 240 nsec. Except for pendently until addressed by the drive circuitry. Coinci- the details of the timing controls, the block diagram of dence in voltage pulses between X and Y will cause the atypical system, as shown inFigure 4, representsthis conventionaldiode to conduct. Itis through this diode model. that information passes in and out of the cell. A typical An independent experiment consisting of the basic pulse pattern, along with the bit-rate clock is shown in cell and the delay line showed that the cell and a coaxial Figure 2. Thebit-rate clock serves to synchronize all line of type RGSA/U cable could perform at 810 iclc with stored information on all lines. a 5-ma, 3-pf, tunnel diode. A 150-bit cell was produced Information isrepresented by twovoltage levels. A using a 160-nsec line of RGSA/U, a bit-rate frequency of change in voltage level always occurs in phase with an 450 Mc, and a 5-ma, 5-pf, tunnel diode. These experi- appropriate zero crossing of the clock. To accomplish this ments verified thefact that for best performance, the relationship, theround-trip line delay is alwaysan impedance level and switching speed of the tunnel diode integralmultiple of a clock periodplus one-half of a should be compatible with the delay-line characteristics. -. This new memory system offers great flexibility of 1 Goto, ,E., Murata, K., Nakazawa, K.,, and Nakagawa, K. “Esaki Dlode Hlgh-Speed Loglcal Clrcults”. IRE Trans. Elec: application over a wide spectrum of capacitiesand tronic Computers, p. 25-29; March, 1960. speeds. Besides achieving higher information rates than moreconventional systems do, this system promises 2 Perry K. E “A Tunnel Diode Reflex Memory,” MIT Lincoln lab RepGrt 526-0018. attractive cost factors because of its simplicity. - a E! v) 14 0 1963 InternationalSolid-State Circuits Conference Y v) WEDNESDAY, FEBRUARY 20, 1963,. , UNIVERSITY OF PEN'NSYLVANIA-IRVINE AUDITORIUM.. .9:00-11:45 A.M.[WAW 1.41 P OTHER TO CELLS X DRIVE +o TT I1 I1 I I ToCELLS OTHER Y DRIVE 1' II I I BIT 1RATE b CLOCK PBGURE I-Shielded basic memory cell-in dashed FIGURE %-Typical pulse pattern stored on delayline. line area. FIGURE 3-Actual 650-Me waveform. Vert: 0.5 vldiu; hor: 5 nseeldiu. DATA LATCHES' 1911 lq21 @I----@ SERIAL PARALLEL PARALLEL SERIAL CLOCK ~ COUNTER READ -WRITE CONTROL SIGNAL / Y DECODE FIGURE 4-Typical system block diagram. FIGURE 5-Typical pattern of the 115-Mc, 8-bit model. Vert: 0.5 vldiu; hor: 50 nsec/div. - z 0 DIGEST OF TECHNICAL PAPERS 0 15 v, v)E .
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