Systemc Analog/Mixed-Signal User's Guide
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Prostep Ivip CPO Statement Template
CPO Statement of Mentor Graphics For Questa SIM Date: 17 June, 2015 CPO Statement of Mentor Graphics Following the prerequisites of ProSTEP iViP’s Code of PLM Openness (CPO) IT vendors shall determine and provide a list of their relevant products and the degree of fulfillment as a “CPO Statement” (cf. CPO Chapter 2.8). This CPO Statement refers to: Product Name Questa SIM Product Version Version 10 Contact Ellie Burns [email protected] This CPO Statement was created and published by Mentor Graphics in form of a self-assessment with regard to the CPO. Publication Date of this CPO Statement: 17 June 2015 Content 1 Executive Summary ______________________________________________________________________________ 2 2 Details of Self-Assessment ________________________________________________________________________ 3 2.1 CPO Chapter 2.1: Interoperability ________________________________________________________________ 3 2.2 CPO Chapter 2.2: Infrastructure _________________________________________________________________ 4 2.3 CPO Chapter 2.5: Standards ____________________________________________________________________ 4 2.4 CPO Chapter 2.6: Architecture __________________________________________________________________ 5 2.5 CPO Chapter 2.7: Partnership ___________________________________________________________________ 6 2.5.1 Data Generated by Users ___________________________________________________________________ 6 2.5.2 Partnership Models _______________________________________________________________________ 6 2.5.3 Support of -
Powerpoint Template
Accellera Overview February 27, 2017 Lu Dai | Accellera Chairman Welcome Agenda . About Accellera . Current news . Technical activities . IEEE collaboration 2 © 2017 Accellera Systems Initiative, Inc. February 2017 Accellera Systems Initiative Our Mission To provide a platform in which the electronics industry can collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products. 3 © 2017 Accellera Systems Initiative, Inc. February 2017 Broad Industry Support Corporate Members 4 © 2017 Accellera Systems Initiative, Inc. February 2017 Broad Industry Support Associate Members 5 © 2017 Accellera Systems Initiative, Inc. February 2017 Global Presence SystemC Evolution Day DVCon Europe DVCon U.S. SystemC Japan Design Automation Conference DVCon China Verification & ESL Forum DVCon India 6 © 2017 Accellera Systems Initiative, Inc. February 2017 Agenda . About Accellera . Current news . Technical activities . IEEE collaboration 7 © 2017 Accellera Systems Initiative, Inc. February 2017 Accellera News . Standards - IEEE Approves UVM 1.2 as IEEE 1800.2-2017 - Accellera relicenses SystemC reference implementation under Apache 2.0 . Outreach - First DVCon China to be held April 19, 2017 - Get IEEE free standards program extended 10 years/10 standards . Awards - Thomas Alsop receives 2017 Technical Excellence Award for his leadership of the UVM Working Group - Shrenik Mehta receives 2016 Accellera Leadership Award for his role as Accellera chair from 2005-2010 8 © 2017 Accellera Systems Initiative, Inc. February 2017 DVCon – Global Presence 29th Annual DVCon U.S. 4th Annual DVCon Europe www.dvcon-us.org 4th Annual DVCon India www.dvcon-europe.org 1st DVCon China www.dvcon-india.org www.dvcon-china.org 9 © 2017 Accellera Systems Initiative, Inc. -
Reception of Low Frequency Time Signals
Reprinted from I-This reDort show: the Dossibilitks of clock svnchronization using time signals I 9 transmitted at low frequencies. The study was madr by obsirvins pulses Vol. 6, NO. 9, pp 13-21 emitted by HBC (75 kHr) in Switxerland and by WWVB (60 kHr) in tha United States. (September 1968), The results show that the low frequencies are preferable to the very low frequencies. Measurementi show that by carefully selecting a point on the decay curve of the pulse it is possible at distances from 100 to 1000 kilo- meters to obtain time measurements with an accuracy of +40 microseconds. A comparison of the theoretical and experimental reiulb permib the study of propagation conditions and, further, shows the drsirability of transmitting I seconds pulses with fixed envelope shape. RECEPTION OF LOW FREQUENCY TIME SIGNALS DAVID H. ANDREWS P. E., Electronics Consultant* C. CHASLAIN, J. DePRlNS University of Brussels, Brussels, Belgium 1. INTRODUCTION parisons of atomic clocks, it does not suffice for clock For several years the phases of VLF and LF carriers synchronization (epoch setting). Presently, the most of standard frequency transmitters have been monitored accurate technique requires carrying portable atomic to compare atomic clock~.~,*,3 clocks between the laboratories to be synchronized. No matter what the accuracies of the various clocks may be, The 24-hour phase stability is excellent and allows periodic synchronization must be provided. Actually frequency calibrations to be made with an accuracy ap- the observed frequency deviation of 3 x 1o-l2 between proaching 1 x 10-11. It is well known that over a 24- cesium controlled oscillators amounts to a timing error hour period diurnal effects occur due to propagation of about 100T microseconds, where T, given in years, variations. -
Co-Simulation Between Cλash and Traditional Hdls
MASTER THESIS CO-SIMULATION BETWEEN CλASH AND TRADITIONAL HDLS Author: John Verheij Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) Computer Architecture for Embedded Systems (CAES) Exam committee: Dr. Ir. C.P.R. Baaij Dr. Ir. J. Kuper Dr. Ir. J.F. Broenink Ir. E. Molenkamp August 19, 2016 Abstract CλaSH is a functional hardware description language (HDL) developed at the CAES group of the University of Twente. CλaSH borrows both the syntax and semantics from the general-purpose functional programming language Haskell, meaning that circuit de- signers can define their circuits with regular Haskell syntax. CλaSH contains a compiler for compiling circuits to traditional hardware description languages, like VHDL, Verilog, and SystemVerilog. Currently, compiling to traditional HDLs is one-way, meaning that CλaSH has no simulation options with the traditional HDLs. Co-simulation could be used to simulate designs which are defined in multiple lan- guages. With co-simulation it should be possible to use CλaSH as a verification language (test-bench) for traditional HDLs. Furthermore, circuits defined in traditional HDLs, can be used and simulated within CλaSH. In this thesis, research is done on the co-simulation of CλaSH and traditional HDLs. Traditional hardware description languages are standardized and include an interface to communicate with foreign languages. This interface can be used to include foreign func- tions, or to make verification and co-simulation possible. Because CλaSH also has possibilities to communicate with foreign languages, through Haskell foreign function interface (FFI), it is possible to set up co-simulation. The Verilog Procedural Interface (VPI), as defined in the IEEE 1364 standard, is used to set-up the communication and to control a Verilog simulator. -
Development of Systemc Modules from HDL for System-On-Chip Applications
University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Masters Theses Graduate School 8-2004 Development of SystemC Modules from HDL for System-on-Chip Applications Siddhartha Devalapalli University of Tennessee - Knoxville Follow this and additional works at: https://trace.tennessee.edu/utk_gradthes Part of the Electrical and Computer Engineering Commons Recommended Citation Devalapalli, Siddhartha, "Development of SystemC Modules from HDL for System-on-Chip Applications. " Master's Thesis, University of Tennessee, 2004. https://trace.tennessee.edu/utk_gradthes/2119 This Thesis is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Masters Theses by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications." I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the equirr ements for the degree of Master of Science, with a major in Electrical Engineering. Dr. Donald W. Bouldin, Major Professor We have read this thesis and recommend its acceptance: Dr. Gregory D. Peterson, Dr. Chandra Tan Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications". -
AN 307: Altera Design Flow for Xilinx Users Supersedes Information Published in Previous Versions
Altera Design Flow for Xilinx Users June 2005, ver. 5.0 Application Note 307 Introduction Designing for Altera® Programmable Logic Devices (PLDs) is very similar, both in concept and in practice, to designing for Xilinx PLDs. In most cases, you can simply import your register transfer level (RTL) into Altera’s Quartus® II software and begin compiling your design to the target device. This document will demonstrate the similar flows between the Altera Quartus II software and the Xilinx ISE software. For designs, which the designer has included Xilinx CORE generator modules or instantiated primitives, the bulk of this document guides the designer in design conversion considerations. Who Should Read This Document The first and third sections of this application note are designed for engineers who are familiar with the Xilinx ISE software and are using Altera’s Quartus II software. This first section describes the possible design flows available with the Altera Quartus II software and demonstrates how similar they are to the Xilinx ISE flows. The third section shows you how to convert your ISE constraints into Quartus II constraints. f For more information on setting up your design in the Quartus II software, refer to the Altera Quick Start Guide For Quartus II Software. The second section of this application note is designed for engineers whose design code contains Xilinx CORE generator modules or instantiated primitives. The second section provides comprehensive information on how to migrate a design targeted at a Xilinx device to one that is compatible with an Altera device. If your design contains pure behavioral coding, you can skip the second section entirely. -
Table of Contents
2012 Sediment Quality Cascade Pole Site Olympia, Washington January 13, 2014 Prepared for Port of Olympia 915 Washington Street NE 130 2nd Avenue South Edmonds, WA 98020 (425) 778-0907 TABLE OF CONTENTS Page 1.0 INTRODUCTION 1-1 1.1 BACKGROUND 1-1 1.1.1 Cleanup Action 1-1 1.1.2 Previous Performance Monitoring 1-2 1.1.2.1 Post-Construction Sediment Monitoring 1-2 1.1.2.2 Prior Performance Monitoring Event 1-2 1.2 REPORT ORGANIZATION 1-3 2.0 SEDIMENT MONITORING APPROACH 2-1 2.1 SAMPLE COLLECTION 2-2 2.1.1 Subsurface Sediment Sampling Procedures 2-2 2.1.2 Surface Sediment Sampling Procedures 2-3 2.2 SAMPLE ANALYSIS 2-3 3.0 MONITORING RESULTS 3-1 3.1 SEDIMENT PHYSICAL CHARACTERISTICS 3-1 3.2 ANALYTICAL RESULTS 3-1 3.2.1 Interior Backfill and Subsurface Sediment Results 3-1 3.2.2 Surface Sediment Results 3-2 4.0 EVALUATION OF CLEANUP EFFECTIVENESS 4-1 5.0 USE OF THIS REPORT 5-1 6.0 REFERENCES 6-1 1/10/14 P:\021\039\FileRm\R\2012 Sed Monitoring Rpt\2012 Sed Quality Rpt.docx LANDAU ASSOCIATES ii FIGURES Figure Title 1 Vicinity Map 2 2012 Sediment Quality - Phase I Sample Locations 3 2012 Sediment Quality - Phase II Surface Sample Locations 4 2012 Sediment Quality - Phase III Surface Sample Locations TABLES Table Title 1 Sample Locations Coordinates 2 Interior Backfill and Subsurface Sediment Results 3 Surface Sediment Results APPENDICES Appendix Title A Sediment Exploration Logs B Analytical Laboratory Reports C Historical Sediment Analytical Results 1/10/14 P:\021\039\FileRm\R\2012 Sed Monitoring Rpt\2012 Sed Quality Rpt.docx LANDAU ASSOCIATES iii LIST OF ABBREVIATIONS AND ACRONYMS ARI Analytical Resources, Incorporated BGS Below Ground Surface CAP Cleanup Action Plan cPAH Carcinogenic Polycyclic Aromatic Hydrocarbons CSL Cleanup Screening Level COPC Chemical of Potential Concern Ecology Washington State Department of Ecology GPS Global Positioning System LPAH Low Molecular Weight PAHs MBL Multiple Benefits Line MSS Marine Sampling Systems, Inc. -
Portable Stimulus: What's Coming in 1.1
Portable Stimulus: What’s Coming in 1.1 and What it Means For You Portable Stimulus Working Group PSS 1.1 Tutorial Agenda • What is PSS Introduction • Tom Fitzpatrick, • Abstract DMA model in PSS 1.0 Mentor, a Siemens Business Memory • The problem • Prabhat Gupta, AMD Allocation • New PSS concepts Higher-Level • The problem • Matan Vax, Scenarios • New constructs Cadence Design Systems • The problem • Karthick Gururaj, HSI Realization • New concepts and constructs Vayavya Labs System-Level • Portability • Hillel Miller, Synopsys Usage • Complex scenarios • Summary Special Thanks to: Conclusion • What’s next Dave Kelf, Breker Verification Systems Josh Rensch, Semifore 2 The Need for Verification Abstraction Test content authoring represents major proportion of development SIMULATION Disconnected cross-process methods Test Content • Block EMULATION • UVM tests laborious, error-prone • SoC FPGA PROTO • Hard to hit corner-cases with C tests • Post-Silicon • Disconnected diagnostic creation IP BLOCK SUBSYSTEM FULL SYSTEM Test portability, reuse, scaling, maintenance all problematic 3 Key Aspects of Portable Stimulus Capture pure Partial scenario Composable Formal Automated test Target multiple test intent description scenarios representation generation platforms of test space Separate test intent from implementation High-coverage test generation across the verification process with much less effort 4 PSS Improves Individual Verification Phases IP BLOCK SUB-SYSTEM FULL SYSTEM Create block-level (UVM) tests & Easily model system-level Generate -
Arm Cortex-M System Design Kit Technical Reference Manual
Arm® Cortex®-M System Design Kit Revision: r1p1 Technical Reference Manual Copyright © 2011, 2013, 2017 Arm Limited (or its affiliates). All rights reserved. ARM DDI 0479D (ID110617) Arm Cortex-M System Design Kit Technical Reference Manual Copyright © 2011, 2013, 2017 Arm Limited (or its affiliates). All rights reserved. Release Information The following changes have been made to this document: Change history Date Issue Confidentiality Change 14 March 2011 A Non-Confidential First release for r0p0 16 June 2011 B Non-Confidential Second release for r0p0 19 April 2013 C Non-Confidential First release for r1p0 31 October 2017 D Non-Confidential First release for r1p1 Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated. Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. -
Workshop on Post-Silicon Debug: Technologies, Methodologies, and Best Practices
Wisam Kadry – IBM Research, Haifa 7 June 2012 Workshop on Post-silicon Debug: Technologies, Methodologies, and Best Practices © 2012 IBM Corporation DAC 2012, Post-silicon Debug Workshop Thanks to Mr. Amir Nahir IBM Research – Haifa, Israel Received his BSc in computer science from Technion, IIT in 2005, and is currently pursuing his PhD there. He has been a research staff member at the IBM Research Labs in Haifa since 2006, and has spent most of his time leading the development of Threadmill – a post-silicon functional validation exerciser. Since the beginning of 2011, Amir manages the Post-Silicon Validation and Design Automation Group 2 © 2012 IBM Corporation DAC 2012, Post-silicon Debug Workshop Agenda Session I (09:00-10:30) Wisam Kadry - IBM Haifa Research Lab., Haifa, Israel Kevin Reick - IBM Corp., Austin, TX Subhasish Mitra - Stanford Univ., Stanford, CA David Erikson - Advanced Micro Devices, Fort Collins, CO Bradley Quinton - Tektronix, Inc., Vancouver, BC, Canada Break (10:30-11:00) Session II (11:00-12:30) Alan Hu - Univ. of British Columbia, Vancouver, BC, Canada Keshavan Tiruvallur - Intel Corp., Portland, OR Nagib Hakim - Intel Corp., Santa Clara, CA Valeria Bertacco - Univ. of Michigan, Ann Arbor, MI Sharad Kumar - Freescale Semiconductor, Inc., Noida, India Lunch (12:30-13:30) Panel (13:30-15:00) Moderator: Harry Foster - Mentor Graphics Corp., Plano, TX 3 © 2012 IBM Corporation DAC 2012, Post-silicon Debug Workshop More complex chips 4 © 2012 IBM Corporation DAC 2012, Post-silicon Debug Workshop Observe 5 © 2012 IBM -
UNIVERSITY of CALIFORNIA RIVERSIDE Emulation of Systemc
UNIVERSITY OF CALIFORNIA RIVERSIDE Emulation of SystemC Applications for Portable FPGA Binaries A Dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science by Scott Spencer Sirowy June 2010 Dissertation Committee: Dr. Frank Vahid, Chairperson Dr. Tony Givargis Dr. Sheldon X.-D. Tan Copyright by Scott Spencer Sirowy 2010 The Dissertation of Scott Spencer Sirowy is approved: Committee Chairperson University of California, Riverside ABSTRACT OF THE DISSERTATION Emulation of SystemC Applications for Portable FPGA Binaries by Scott Spencer Sirowy Doctor of Philosophy, Graduate Program in Computer Science University of California, Riverside, June 2010 Dr. Frank Vahid, Chairperson As FPGAs become more common in mainstream general-purpose computing platforms, capturing and distributing high-performance implementations of applications on FPGAs will become increasingly important. Even in the presence of C-based synthesis tools for FPGAs, designers continue to implement applications as circuits, due in large part to allow for capture of clever spatial, circuit-level implementation features leading to superior performance and efficiency. We demonstrate the feasibility of a spatial form of FPGA application capture that offers portability advantages for FPGA applications unseen with current FPGA binary formats. We demonstrate the portability of such a distribution by developing a fast on-chip emulation framework that performs transparent optimizations, allowing spatially-captured FPGA applications to immediately run on FPGA platforms without costly and hard-to-use synthesis/mapping tool flows, and sometimes faster than PC-based execution. We develop several dynamic and transparent optimization techniques, including just-in-time compilation , bytecode acceleration , and just-in-time synthesis that take advantage of a platform’s available resources, resulting in iv orders of magnitude performance improvement over normal emulation techniques and PC-based execution. -
Hardware Description Languages Compared: Verilog and Systemc
Hardware Description Languages Compared: Verilog and SystemC Gianfranco Bonanome Columbia University Department of Computer Science New York, NY Abstract This library encompasses all of the necessary components required to transform C++ into a As the complexity of modern digital systems hardware description language. Such additions increases, engineers are now more than ever include constructs for concurrency, time notion, integrating component modeling by means of communication, reactivity and hardware data hardware description languages (HDLs) in the types. design process. The recent addition of SystemC to As described by Edwards [1], VLSI an already competitive arena of HDLs dominated verification involves an initial simulation done in by Verilog and VHDL, calls for a direct C or C++, usually for proof of concept purposes, comparison to expose potential advantages and followed by translation into an HDL, simulation of flaws of this newcomer. This paper presents such the model, applying appropriate corrections, differences and similarities, specifically between hardware synthesization and further iterative Verilog and SystemC, in effort to better categorize refinement. SystemC is able to shorten this the scopes of the two languages. Results are based process by combining the first two steps. on simulation conducted in both languages, for a Consequently, this also decreases time to market model with equal specifications. for a manufacturer. Generally a comparison between two computer languages is based on the number of Introduction lines of code and execution time required to achieve a specific task, using the two languages. A Continuous advances in circuit fabrication number of additional parameters can be observed, technology have augmented chip density, such as features, existence or absence of constructs consequently increasing device complexity.