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Packaging for Power Electronics “Habilitation À Diriger Des Recherches” Packaging for Power Electronics “Habilitation à Diriger des Recherches” Cyril BUTTAY Laboratoire Ampère, Lyon, France 2015 1 / 45 Outline Professional Record Background Contributions Perspectives Conclusion 1 / 45 Outline Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion 1 / 45 History 1996 – 2001: Electrical Engineer training (INSA Lyon) 2001 – 2004: PhD thesis (CIFRE grant with Valeo) at CEGELY 2004 – 2005: Teaching assistant (ATER at INSA Lyon), LGEF 2005 – 2007: Research Associate with Sheffield and Nottingham Universities 2008 – . : Researcher (Chargé de recherche) with CNRS. § From pure Electrical Engineering to Packaging 2 / 45 Teaching Student Level Type of classes (Licence/Bachelor or Master) Lab/Projects M2 59% L1 21% 27% 11% M1 6% 16% 4% 31% 24% Tutorials L2 Lectures Administrative L3 Total 2001–2015: 645 h 3 / 45 Publications 10 conferences 8 journals 6 I Journals: Count I 9 IEEE 4 I 6 Elsevier 2 I 2 invited conferences I 2008: Starting with CNRS 0 I 2013-2014: HDR writing-up 2003200420052006200720082009201020112012201320142015 WOS Google Citations 182 610 h-index 6 12 4 / 45 Supervision PhD A. Masson A.-S. Podlejski PhD W. Sabbah C. Yu V. Dos Santos PhD B. Mouawad L. Ruffeil PhD S. Hascoet I. Dchar PhD R. Riva H. Reynes License Master N. Qorchi H. Dung J. Billore M. Kamden D. Moureaux Master E. Rjeilly R. Caillaud Master J. Zaraket R. Leite Master H. Ben Omar 2009 2010 2011 2012 2013 2014 2015 I Shared supervision, various degrees I Funded by the industry or by research projects I Increase in Master’s projects 5 / 45 Research Projects EPAHT ETHAER BQR CIFRE Industry Project ECLIPSE ARC THOR Industry Project BQR Ind. Project ACCITE SuMeCe Ind. Project Supergrid Genome 2009 2010 2011 2012 2013 2014 2015 I Some projects with lower involvment not mentionned I Various funding schemes: I European: Euripides-Catrene (THOR) I National: Agency for Research (ETHAER, ECLIPSE), Aerospace and Space –FNRAE– (EPAHT, ACCITE) I Local fundings: BQR, Carnot institute (SuMeCe) I Direct funding by the industry (5 companies) 6 / 45 Others activities I In the lab I Member of the laboratory board I Installation and management of shared equipment: I Packaging lab (≈ 300kC) I Computer cluster (2009–2014) I In the research community I Reviewer for journals/conferences (20-30 publications/year) I Reviewer for projects proposals (Cleansky, 7 days) I Member of 3 selection panels (hiring of lecturers) I Member of PhD jurys (10) I Member of an evaluation committee (LN2, Sherbrooke) I Management of the “3DPHI” platform on power integration (Toulouse) with 2 colleagues. 7 / 45 Outline Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion 7 / 45 The Power Module I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. 8 / 45 The Power Module I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. 8 / 45 The Power Module I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. 8 / 45 The Power Module I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. 8 / 45 The Power Module I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. 8 / 45 The Power Module I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. 8 / 45 Operating Temperature Limits 3000°C Silicon 3C−SiC 2500°C 6H−SiC 4H−SiC 2H−GaN Diamond 2000°C Some limits: 1500°C 660°C Aluminium melts 1000°C ≈ 300°C Die Solder melts Junction temperature 500°C 200 – 250 °C Silicone gel degrades 0°C ≈ 200°C Board solder melts 10 V 100 V 1 kV 10 kV 100 kV 1 MV Breakdown voltage Source: C. Raynaud et al. “Comparison of high voltage and high temperature performances of wide bandgap semiconductors for vertical power devices” Diamond and Related Materials, 2010, 19, 1-6 I For Wide-Bandgap devices, limits set by packaging I Additional packaging issues with thermal cycling 9 / 45 Effect of the Packaging on Electrical Performance RGh Th VDRh VIn IOut RGl Tl VDRl I Stray inductances cause ringing and switching losses I Parasitic capacitances cause common-mode current I Both are caused by packaging 10 / 45 Effect of the Packaging on Electrical Performance LDC1 LDC2 CGDh R L Gh Gh CDSh Th C V GSh CCM1 LCdc DRh LSh VIn CCM2 CDC COut LDl I CGDl Out R L Gl Gl CDSl Tl CGSl VDRl LSl LDC3 LDC4 I Stray inductances cause ringing and switching losses I Parasitic capacitances cause common-mode current I Both are caused by packaging 10 / 45 Effect of the Packaging on Electrical Performance – 2 Simulations at I0 = 100 A Energy stored in the drain inductance 1 mJ 500 uJ Switching energy (J) 0 J 0 H 20 nH 40 nH 60 nH 80 nH 100 nH 120 nH Drain inductance (H) I Low voltage switching cell (30 V Si MOSFETs) simulations I Most of the losses can be attributed to circuit layout I Here all stray inductances 1 nH, except LD 11 / 45 Outline Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion 11 / 45 Outline Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion 11 / 45 I Share the cooling system between electrical and internal combustion engines. I Cooling fluid temperature: 120 °C I NASA mission to Venus: up to 480°C I Mission to Jupiter: 100 bars, 400°C I Oil, gas and geothermal drilling I Low thermal cycling, high ambient temp. (200 to >300 °C) Applications of High Temperature Electronics I Actuators and electronics close to the jet engine I Deep thermal cycling (-55/+225°C) I Long operating life (up to 30 years) 12 / 45 I NASA mission to Venus: up to 480°C I Mission to Jupiter: 100 bars, 400°C I Oil, gas and geothermal drilling I Low thermal cycling, high ambient temp. (200 to >300 °C) Applications of High Temperature Electronics I Actuators and electronics close to the jet engine I Deep thermal cycling (-55/+225°C) I Long operating life (up to 30 years) I Share the cooling system between electrical and internal combustion engines. I Cooling fluid temperature: 120 °C 12 / 45 I Oil, gas and geothermal drilling I Low thermal cycling, high ambient temp. (200 to >300 °C) Applications of High Temperature Electronics I Actuators and electronics close to the jet engine I Deep thermal cycling (-55/+225°C) I Long operating life (up to 30 years) I Share the cooling system between electrical and internal combustion engines. I Cooling fluid temperature: 120 °C I NASA mission to Venus: up to 480°C I Mission to Jupiter: 100 bars, 400°C 12 / 45 Applications of High Temperature Electronics I Actuators and electronics close to the jet engine I Deep thermal cycling (-55/+225°C) I Long operating life (up to 30 years) I Share the cooling system between electrical and internal combustion engines. I Cooling fluid temperature: 120 °C I NASA mission to Venus: up to 480°C I Mission to Jupiter: 100 bars, 400°C I Oil, gas and geothermal drilling I Low thermal cycling, high ambient temp. (200 to >300 °C) 12 / 45 High temperature behaviour of SiC devices Static Characterization of 490 mΩ JFET 12 -50 ◦ C -10 ◦ C 10 30 ◦ C 70 ◦ C 8 110 ◦ C 150 ◦ C 6 190 ◦ C 230 ◦ C 4 270 ◦ C 300 ◦ C Forward current [A] 2 0 0 2 4 6 8 10 12 Forward voltage [V] VGS = 0 V , i.e. device fully-on I Large increase in on-state resistance with temperature; I Strong sensitivity of conduction losses to temperature. 13 / 45 High temperature behaviour of SiC devices Static Characterization of 490 mΩ JFET 12 -50 ◦ C 140 2.0 A -10 ◦ C 4.0 A 10 30 ◦ C 120 6.0 A 70 ◦ C 8.0 A 8 100 10.0 A 110 ◦ C 150 ◦ C 80 6 190 ◦ C 60 230 ◦ C 4 270 ◦ C 300 ◦ C 40 Forward current [A] Dissipated power [W] 2 20 0 0 0 2 4 6 8 10 12 50 0 50 100 150 200 250 300 Forward voltage [V] Junction temperature [C] VGS = 0 V , i.e. device fully-on I Large increase in on-state resistance with temperature; I Strong sensitivity of conduction losses to temperature. 13 / 45 Always stable Always unstable Becomming unstable with ambient temperature rise High temperature behaviour of SiC devices Thermal Run-away mechanism I The device characteristic I Its associated cooling system I Two equilibrium points: one stable and one unstable I Above the unstable point, run-away occurs 14 / 45 Always stable Always unstable Becomming unstable with ambient temperature rise High temperature behaviour of SiC devices Thermal Run-away mechanism I The device characteristic I Its associated cooling system I Two equilibrium points: one stable and one unstable I Above
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