Packaging for Power Electronics “Habilitation À Diriger Des Recherches”

Packaging for Power Electronics “Habilitation à Diriger des Recherches”

Cyril BUTTAY

Laboratoire Ampère, Lyon, France

2015

1 / 45 Outline

Professional Record

Background

Contributions

Perspectives

Conclusion

1 / 45 Outline

Professional Record

Background

Contributions Packaging for High Temperatures New Packaging Structures for Power Modules

Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages

Conclusion

1 / 45 History

1996 – 2001: Electrical Engineer training (INSA Lyon) 2001 – 2004: PhD thesis (CIFRE grant with Valeo) at CEGELY 2004 – 2005: Teaching assistant (ATER at INSA Lyon), LGEF 2005 – 2007: Research Associate with Shefﬁeld and Nottingham Universities 2008 – . . . : Researcher (Chargé de recherche) with CNRS. § From pure Electrical Engineering to Packaging

2 / 45 Teaching

Student Level Type of classes (Licence/Bachelor or Master)

Lab/Projects

M2 59% L1 21% 27%

11% M1 6% 16% 4% 31% 24% Tutorials L2 Lectures Administrative L3

Total 2001–2015: 645 h

3 / 45 Publications

10 conferences 8 journals

6 I Journals:

Count I 9 IEEE 4 I 6 Elsevier

2 I 2 invited conferences I 2008: Starting with CNRS 0 I 2013-2014: HDR writing-up 2003200420052006200720082009201020112012201320142015

WOS Google Citations 182 610 h-index 6 12

4 / 45 Supervision

PhD A. Masson A.-S. Podlejski PhD W. Sabbah C. Yu V. Dos Santos PhD B. Mouawad L. Ruffeil PhD S. Hascoet I. Dchar PhD R. Riva H. Reynes License

Master N. Qorchi H. Dung J. Billore M. Kamden D. Moureaux

Master E. Rjeilly R. Caillaud

Master J. Zaraket R. Leite

Master H. Ben Omar

2009 2010 2011 2012 2013 2014 2015 I Shared supervision, various degrees

I Funded by the industry or by research projects

I Increase in Master’s projects

5 / 45 Research Projects

EPAHT ETHAER

BQR CIFRE Industry Project

ECLIPSE ARC

THOR Industry Project

BQR Ind. Project ACCITE

SuMeCe Ind. Project

Supergrid

Genome

2009 2010 2011 2012 2013 2014 2015

I Some projects with lower involvment not mentionned I Various funding schemes:

I European: Euripides-Catrene (THOR) I National: Agency for Research (ETHAER, ECLIPSE), Aerospace and Space –FNRAE– (EPAHT, ACCITE) I Local fundings: BQR, Carnot institute (SuMeCe) I Direct funding by the industry (5 companies)

6 / 45 Others activities

I In the lab

I Member of the laboratory board I Installation and management of shared equipment:

I Packaging lab (≈ 300kC) I Computer cluster (2009–2014) I In the research community

I Reviewer for journals/conferences (20-30 publications/year) I Reviewer for projects proposals (Cleansky, 7 days) I Member of 3 selection panels (hiring of lecturers) I Member of PhD jurys (10) I Member of an evaluation committee (LN2, Sherbrooke) I Management of the “3DPHI” platform on power integration (Toulouse) with 2 colleagues.

7 / 45 Outline

Professional Record

Background

Contributions Packaging for High Temperatures New Packaging Structures for Power Modules

Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages

Conclusion

7 / 45 The Power Module

I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. . .

8 / 45 The Power Module

I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. . .

8 / 45 The Power Module

I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. . .

8 / 45 The Power Module

I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. . .

8 / 45 The Power Module

I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. . .

8 / 45 The Power Module

I Many functions: I Thermal management I Electrical insulation I Interconnects I Mechanical/chemical protection I Many materials: I Ceramics I Metals I Organics. . .

8 / 45 Operating Temperature Limits

3000°C Silicon 3C−SiC 2500°C 6H−SiC 4H−SiC 2H−GaN Diamond 2000°C Some limits:

1500°C 660°C Aluminium melts

1000°C ≈ 300°C Die Solder melts Junction temperature

500°C 200 – 250 °C Silicone gel degrades

0°C ≈ 200°C Board solder melts 10 V 100 V 1 kV 10 kV 100 kV 1 MV Breakdown voltage Source: C. Raynaud et al. “Comparison of high voltage and high temperature performances of wide bandgap semiconductors for vertical power devices” Diamond and Related Materials, 2010, 19, 1-6

I For Wide-Bandgap devices, limits set by packaging

I Additional packaging issues with thermal cycling

9 / 45 Effect of the Packaging on Electrical Performance

RGh Th

VDRh

VIn

IOut

RGl Tl

VDRl

I Stray inductances cause ringing and switching losses

I Parasitic capacitances cause common-mode current

I Both are caused by packaging

10 / 45 Effect of the Packaging on Electrical Performance

LDC1 LDC2

CGDh R L Gh Gh CDSh Th C V GSh CCM1 LCdc DRh LSh

VIn

CCM2 CDC COut LDl I CGDl Out R L Gl Gl CDSl Tl

CGSl VDRl LSl LDC3 LDC4

I Stray inductances cause ringing and switching losses

I Parasitic capacitances cause common-mode current

I Both are caused by packaging

10 / 45 Effect of the Packaging on Electrical Performance – 2

Simulations at I0 = 100 A Energy stored in the drain inductance

1 mJ

500 uJ Switching energy (J)

0 J 0 H 20 nH 40 nH 60 nH 80 nH 100 nH 120 nH Drain inductance (H)

I Low voltage switching cell (30 V Si MOSFETs) simulations I Most of the losses can be attributed to circuit layout

I Here all stray inductances 1 nH, except LD

11 / 45 Outline

Professional Record

Background

Contributions Packaging for High Temperatures New Packaging Structures for Power Modules

Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages

Conclusion

11 / 45 Outline

Professional Record

Background

Contributions Packaging for High Temperatures New Packaging Structures for Power Modules

Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages

Conclusion

11 / 45 I Share the cooling system between electrical and internal combustion engines.

I Cooling ﬂuid temperature: 120 °C

I NASA mission to Venus: up to 480°C

I Mission to Jupiter: 100 bars, 400°C

I Oil, gas and geothermal drilling

I Low thermal cycling, high ambient temp. (200 to >300 °C)

Applications of High Temperature Electronics

I Actuators and electronics close to the jet engine

I Deep thermal cycling (-55/+225°C)

I Long operating life (up to 30 years)

12 / 45 I NASA mission to Venus: up to 480°C

I Mission to Jupiter: 100 bars, 400°C

I Oil, gas and geothermal drilling

I Low thermal cycling, high ambient temp. (200 to >300 °C)

Applications of High Temperature Electronics

I Actuators and electronics close to the jet engine

I Deep thermal cycling (-55/+225°C)

I Long operating life (up to 30 years)

I Share the cooling system between electrical and internal combustion engines.

I Cooling ﬂuid temperature: 120 °C

12 / 45 I Oil, gas and geothermal drilling

I Low thermal cycling, high ambient temp. (200 to >300 °C)

Applications of High Temperature Electronics

I Actuators and electronics close to the jet engine

I Deep thermal cycling (-55/+225°C)

I Long operating life (up to 30 years)

I Share the cooling system between electrical and internal combustion engines.

I Cooling ﬂuid temperature: 120 °C

I NASA mission to Venus: up to 480°C

I Mission to Jupiter: 100 bars, 400°C

12 / 45 Applications of High Temperature Electronics

I Actuators and electronics close to the jet engine

I Deep thermal cycling (-55/+225°C)

I Long operating life (up to 30 years)

I Share the cooling system between electrical and internal combustion engines.

I Cooling ﬂuid temperature: 120 °C

I NASA mission to Venus: up to 480°C

I Mission to Jupiter: 100 bars, 400°C

I Oil, gas and geothermal drilling

I Low thermal cycling, high ambient temp. (200 to >300 °C)

12 / 45 High temperature behaviour of SiC devices

Static Characterization of 490 mΩ JFET

-50 ◦ C -10 ◦ C 10 30 ◦ C

70 ◦ C 8 110 ◦ C

150 ◦ C 6 190 ◦ C 230 ◦ C

4 270 ◦ C 300 ◦ C Forward current [A] 2

0 0 2 4 6 8 10 12 Forward voltage [V]

VGS = 0 V , i.e. device fully-on I Large increase in on-state resistance with temperature; I Strong sensitivity of conduction losses to temperature.

13 / 45 High temperature behaviour of SiC devices

Static Characterization of 490 mΩ JFET

-50 ◦ C 140 2.0 A -10 ◦ C 4.0 A 10 30 ◦ C 120 6.0 A

70 ◦ C 8.0 A 8 100 10.0 A 110 ◦ C

150 ◦ C 80 6 190 ◦ C 60 230 ◦ C

4 270 ◦ C 300 ◦ C 40 Forward current [A] Dissipated power [W] 2 20

0 0 0 2 4 6 8 10 12 50 0 50 100 150 200 250 300 Forward voltage [V] Junction temperature [C]

VGS = 0 V , i.e. device fully-on I Large increase in on-state resistance with temperature; I Strong sensitivity of conduction losses to temperature.

13 / 45 Always stable Always unstable Becomming unstable with ambient temperature rise

High temperature behaviour of SiC devices

Thermal Run-away mechanism

I The device characteristic

I Its associated cooling system

I Two equilibrium points: one stable and one unstable

I Above the unstable point, run-away occurs

14 / 45 Always stable Always unstable Becomming unstable with ambient temperature rise

High temperature behaviour of SiC devices

Thermal Run-away mechanism

I The device characteristic

I Its associated cooling system

I Two equilibrium points: one stable and one unstable

I Above the unstable point, run-away occurs

14 / 45 Always stable Always unstable Becomming unstable with ambient temperature rise

High temperature behaviour of SiC devices

Thermal Run-away mechanism

I The device characteristic

I Its associated cooling system

I Two equilibrium points: one stable and one unstable

I Above the unstable point, run-away occurs

14 / 45 Always stable Always unstable Becomming unstable with ambient temperature rise

High temperature behaviour of SiC devices

Thermal Run-away mechanism

I The device characteristic

I Its associated cooling system

I Two equilibrium points: one stable and one unstable

I Above the unstable point, run-away occurs

14 / 45 Always stable Always unstable Becomming unstable with ambient temperature rise

High temperature behaviour of SiC devices

Thermal Run-away mechanism

I The device characteristic

I Its associated cooling system

I Two equilibrium points: one stable and one unstable

I Above the unstable point, run-away occurs

14 / 45 Always unstable Becomming unstable with ambient temperature rise

High temperature behaviour of SiC devices

Thermal Run-away mechanism

I The device characteristic

I Its associated cooling system

I Two equilibrium points: one stable and one unstable

I Above the unstable point, run-away occurs

Always stable 14 / 45 Becomming unstable with ambient temperature rise

High temperature behaviour of SiC devices

Thermal Run-away mechanism

I The device characteristic

I Its associated cooling system

I Two equilibrium points: one stable and one unstable

I Above the unstable point, run-away occurs

Always stable Always unstable 14 / 45 High temperature behaviour of SiC devices

Thermal Run-away mechanism

I The device characteristic

I Its associated cooling system

I Two equilibrium points: one stable and one unstable

I Above the unstable point, run-away occurs

Always stable Always unstable Becomming unstable with ambient temperature rise 14 / 45 Power dissipation as a function of the junction temp.

140 2.0 A 4.0 A 120 6.0 A 8.0 A 100 10.0 A

40 Dissipated power [W] 20

0 50 0 50 100 150 200 250 300 Junction temperature [C]

15 / 45 Power dissipation as a function of the junction temp.

140 2.0 A 4.0 A 1K/W 120 6.0 A 8.0 A 100 10.0 A

80 2K/W 60

Dissipated power [W] 4.5K/W 20

0 50 0 50 100 150 200 250 300 Junction temperature [C]

15 / 45 High Temperature Thermal Management

Buttay et al. “Thermal Stability of Silicon Carbide Power JFETs”, IEEE Trans on Electron Devices, 2014 80

70 SiC JFET: Run-away 60 I 490 mΩ, 1200 V

I RThJA = 4.5 K /W 50

power [W] I 135 °C ambient

40 I On-state losses current changed from 3.65 to 3.7 A 30

100 150 200 250 300 350 time [s] High temperature capability 6= reduced cooling needs! SiC JFETs must be attached to a low-RTh cooling system.

16 / 45 High Temperature die attaches

The problem with solders

Solders operate in this region Homologous temperature:

T [K ] Properties little Unable to bear Oper aﬀected by engineering TH = temperature Creep range loads TMelt [K ]

Strengh/Hardness Example:

I AuGe solder: TMelt = 356°C = 629 K 0 0.4 0.6 1 Homologous Temperature I T = 0 8 § T = 503 K = 230 °C Source: H . Oper http://www.ami.ac.uk/courses/topics/0164_homt/

I High temperature solder alloys not practical I Need to decorrelate process temperature and melting point:

I Sintering (solid state, process below melting point) I Diffusion soldering/TLPB (creation of a high melting point alloy)

17 / 45 High Temperature die attaches

The problem with solders

Solders operate in this region Homologous temperature:

T [K ] Properties little Unable to bear Oper aﬀected by engineering TH = temperature Creep range loads TMelt [K ]

Strengh/Hardness Example:

I AuGe solder: TMelt = 356°C = 629 K 0 0.4 0.6 1 Homologous Temperature I T = 0 8 § T = 503 K = 230 °C Source: H . Oper http://www.ami.ac.uk/courses/topics/0164_homt/

I High temperature solder alloys not practical I Need to decorrelate process temperature and melting point:

I Sintering (solid state, process below melting point) I Diffusion soldering/TLPB (creation of a high melting point alloy)

17 / 45 High Temperature die attaches

The problem with solders

Solders operate in this region Homologous temperature:

T [K ] Properties little Unable to bear Oper aﬀected by engineering TH = temperature Creep range loads TMelt [K ]

Strengh/Hardness Example:

I AuGe solder: TMelt = 356°C = 629 K 0 0.4 0.6 1 Homologous Temperature I T = 0 8 § T = 503 K = 230 °C Source: H . Oper http://www.ami.ac.uk/courses/topics/0164_homt/

I High temperature solder alloys not practical I Need to decorrelate process temperature and melting point:

I Sintering (solid state, process below melting point) I Diffusion soldering/TLPB (creation of a high melting point alloy)

17 / 45 High Temperature die attaches

The problem with solders

Solders operate in this region Homologous temperature:

T [K ] Properties little Unable to bear Oper aﬀected by engineering TH = temperature Creep range loads TMelt [K ]

Strengh/Hardness Example:

I AuGe solder: TMelt = 356°C = 629 K 0 0.4 0.6 1 Homologous Temperature I T = 0 8 § T = 503 K = 230 °C Source: H . Oper http://www.ami.ac.uk/courses/topics/0164_homt/

I High temperature solder alloys not practical I Need to decorrelate process temperature and melting point:

I Sintering (solid state, process below melting point) I Diffusion soldering/TLPB (creation of a high melting point alloy)

17 / 45 High Temperature die attaches

The problem with solders

Solders operate in this region Homologous temperature:

T [K ] Properties little Unable to bear Oper aﬀected by engineering TH = temperature Creep range loads TMelt [K ]

Strengh/Hardness Example:

I AuGe solder: TMelt = 356°C = 629 K 0 0.4 0.6 1 Homologous Temperature I T = 0 8 § T = 503 K = 230 °C Source: H . Oper http://www.ami.ac.uk/courses/topics/0164_homt/

I High temperature solder alloys not practical I Need to decorrelate process temperature and melting point:

I Sintering (solid state, process below melting point) I Diffusion soldering/TLPB (creation of a high melting point alloy)

17 / 45 High Temperature Die Attaches – PhD A. MASSON

I development of the sintering process

I Nano-particles paste from NBE Tech

I Evaluation of many parameters

I Sintering pressure I Surface roughness I Thickness of stencil I Substrate ﬁnish. . .

I Once set, process is robust

18 / 45 High Temperature Die Attaches – PhD A. MASSON

I development of the sintering process

I Nano-particles paste from NBE Tech

I Evaluation of many parameters

I Sintering pressure 70 I Surface roughness 60

I Thickness of stencil 50 I Substrate ﬁnish. . . 40

I Once set, process is robust 30

20 Shear strenght [MPa] 10

0 A’ B C D E F J N O T Series name

18 / 45 High Temperature Die Attaches – PhD A. MASSON

I development of the sintering process

I Nano-particles paste from NBE Tech

I Evaluation of many parameters

I Sintering pressure 70 I Surface roughness 60

I Thickness of stencil 50 I Substrate ﬁnish. . . 40

I Once set, process is robust 30

20 Shear strenght [MPa]

SiC 10 0 Ag A’ B C D E F J N O T Series name Cu

18 / 45 High Temperature Die Attaches – PhD S. HASCOËT

I “Pressureless” sintering process

I Based on micro-particles I Findings:

I Oxygen is necessary I Bonding on copper (oxide) I Standard Ni/Au ﬁnish not ideal

I Conﬁrmed by several teams I weak bonds at Ag/Au interface

I Bond strength lower I Porosity higher I Can be used to attach fragile components

19 / 45 High Temperature Die Attaches

250

200 200°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 200°C I All-sintered assembly 3

I Half-Bridge structure ] A [

t 2 u o I SiC JFETs I 1 I Integrated gate drivers (Ampère) 0 I Ceramic capacitors 1 49.0 48.8 48.6 48.4 0.2 0.0 0.2 I Isolation function not integrated time [ s] time [ s] µ µ 20 / 45 High Temperature Die Attaches

250

200 210°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 210°C I All-sintered assembly 3

I Half-Bridge structure ] A [

250

200 220°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 220°C I All-sintered assembly 3

I Half-Bridge structure ] A [

250

200 230°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 230°C I All-sintered assembly 3

I Half-Bridge structure ] A [

250

200 240°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 240°C I All-sintered assembly 3

I Half-Bridge structure ] A [

250

200 250°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 250°C I All-sintered assembly 3

I Half-Bridge structure ] A [

250

200 260°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 260°C I All-sintered assembly 3

I Half-Bridge structure ] A [

250

200 270°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 270°C I All-sintered assembly 3

I Half-Bridge structure ] A [

250

200 280°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 280°C I All-sintered assembly 3

I Half-Bridge structure ] A [

250

200 290°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 290°C I All-sintered assembly 3

I Half-Bridge structure ] A [

250

200 300°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 300°C I All-sintered assembly 3

I Half-Bridge structure ] A [

250

200 310°C

150 ] V [

t 100 u o V

50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [µs] time [µs]

4 310°C I All-sintered assembly 3

I Half-Bridge structure ] A [

T = 3 0 0 ° C

1 E - 2 ) 1 -

h (

t / 1

1 E - 3 S t o p p a r a m e t e r

W i t h o u t p a r y l e n e P a r y l e n e S C S H T

5 0 0 1 0 0 0 1 5 0 0 2 0 0 0 2 5 0 0 3 0 0 0 3 5 0 0 4 0 0 0 4 5 0 0 5 0 0 0 E l e c t r i c F i e l d ( V / m m )

I Causes: electric ﬁeld, high temperature and oxygen

I Large differences between similar test vehicles:

I Short life without encapsulation (100–1000 h)

I Much longer life with parylene HT protection 21 / 45 High Temperature Die Attaches – Silver migration, R. RIVA

T = 3 0 0 ° C

1 E - 2 ) 1 -

h (

t / 1

1 E - 3 S t o p p a r a m e t e r

W i t h o u t p a r y l e n e P a r y l e n e S C S H T

5 0 0 1 0 0 0 1 5 0 0 2 0 0 0 2 5 0 0 3 0 0 0 3 5 0 0 4 0 0 0 4 5 0 0 5 0 0 0 E l e c t r i c F i e l d ( V / m m )

I Causes: electric ﬁeld, high temperature and oxygen

I Large differences between similar test vehicles:

I Short life without encapsulation (100–1000 h)

I Much longer life with parylene HT protection 21 / 45 Conclusion on Packaging for High Temperature

SiC devices can operate at high temperature (>300 °C)

I With efﬁcient thermal management!

I RTh must remain low Silver sintering for high temperature die attaches

I Compatible with standard die ﬁnishes

I Very good results

I High thermal/electrical performance

I Industry is catching on I Research: long-term behaviour at elevated temperature

I pressureless processes are a good model

22 / 45 Outline

Professional Record

Background

Contributions Packaging for High Temperatures New Packaging Structures for Power Modules

Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages

Conclusion

22 / 45 New Structures

23 / 45 New Structures

23 / 45 New Packaging Structures – Macro post 1

I Dies soldered to two DBC substrates to form a “sandwich” module;

I Power module clamped between heat-exchangers;

I Connection to DC capacitors using a low inductance link.

24 / 45 New Packaging Structures – Macro post 1

I Dies soldered to two DBC substrates to form a “sandwich” module;

I Power module clamped between heat-exchangers;

I Connection to DC capacitors using a low inductance link.

24 / 45 New Packaging Structures – Macro post 1

I Dies soldered to two DBC substrates to form a “sandwich” module;

I Power module clamped between heat-exchangers;

I Connection to DC capacitors using a low inductance link.

24 / 45 New Packaging Structures – Macro post 1

I Dies soldered to two DBC substrates to form a “sandwich” module;

I Power module clamped between heat-exchangers;

I Connection to DC capacitors using a low inductance link.

24 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

I “top” heat-exchanger;

I power modules

I “bottom” heat-exchanger;

I driver boards;

I driver interconects;

I driver cover

I capacitor board;

I power terminals;

I busbar;

I capacitor cover.

25 / 45 New Packaging Structures – Macro post 1

26 / 45 New Packaging Structures – Macro post 1

700

600

500

] 400 V [

t u o

V 300

200

100

0 10.1 10.2 10.3 11.7 11.8 11.9 time [µs] time [µs]

I Switching speed limited by switches (Si IGBTs, SiC diodes);

I No ringing measured at the terminals of the modules;

I DC link inductance estimated at 10 nH.

27 / 45 New Packaging Structures – Macro post 2 (R RIVA)

Vbus

OUT

GND

I Two ceramic substrates, in “sandwich” conﬁguration

I Two SiC JFET dies (SiCED)

I assembled using silver sintering

I 25.4 mm×12.7 mm (1 in×0.5 in)

28 / 45 New Packaging Structures – Macro post 2 (R RIVA)

Copper

Alumina

0.16 mm 0,15 mm mm 0,15

0.15 mm Source Gate Source mm 0,3 I Etching accuracy exceeds 0.2 mm SiC JFET standard design rules I Double-step copper etching for 0.3 mm Drain die contact § Custom etching technique

Scale drawing for 2.4×2.4 mm2 die

29 / 45 New Packaging Structures – Macro post 2 (R RIVA)

200°C 200

150 I Two-step etching of copper

100 ] V

[ I Ti/Ag PVD using shadow mask on dies

t u o V 50 I Set of aligment jigs for assembly

0 I Proper drying of silver paste

50 0.9 1.0 1.1 1.2 49.9 50.0 50.1 50.2 I First electrical tests on 300 Ω load time [µs] time [µs]

30 / 45 New Packaging Structures – Macro post 2 (R RIVA)

I Good form factor achieved using the two-step copper etching process

I Satisfying alignment

I Poor quality of Al-Cu attach

31 / 45 New Packaging Structures – Micro posts (B MOUAWAD)

I First studies during L. MÉNAGER PhD

I Copper posts growth on die (electroplating) I Original die/DBC assembly technology: SnCu diffusion bonding

I Proposition of M. SOUEIDAN: direct copper bonding

32 / 45 New Packaging Structures – Micro posts (B MOUAWAD)

Parameters:

I SPS press

I Cu/Cu bonding

I 5 or 20 min

I 200 or 300°C

I 16 or 77 MPa

I Very good bond, without any interface material

I All conﬁguration but one yield to bonding I Tensile strenght 106 to 261 MPa (365 MPa for bulk copper)

I Parameters compatible with the process of a semiconductor die I Bonding mechanism still unclear

I Some investigations performed, much more needed

33 / 45 New Packaging Structures – Micro posts (B MOUAWAD)

Parameters:

I SPS press

I Cu/Cu bonding

I 5 or 20 min

I 200 or 300°C

I 16 or 77 MPa

I Very good bond, without any interface material

I All conﬁguration but one yield to bonding I Tensile strenght 106 to 261 MPa (365 MPa for bulk copper)

I Parameters compatible with the process of a semiconductor die I Bonding mechanism still unclear

I Some investigations performed, much more needed

33 / 45 New Packaging Structures – Micro posts (B MOUAWAD)

Parameters:

I SPS press

I Cu/Cu bonding

I 5 or 20 min

I 200 or 300°C

I 16 or 77 MPa

I Very good bond, without any interface material

I All conﬁguration but one yield to bonding I Tensile strenght 106 to 261 MPa (365 MPa for bulk copper)

I Parameters compatible with the process of a semiconductor die I Bonding mechanism still unclear

I Some investigations performed, much more needed

33 / 45 New Packaging Structures – Micro posts (B MOUAWAD)

Parameters:

I SPS press

I Cu/Cu bonding

I 5 or 20 min

I 200 or 300°C

I 16 or 77 MPa

I Very good bond, without any interface material

I All conﬁguration but one yield to bonding I Tensile strenght 106 to 261 MPa (365 MPa for bulk copper)

I Parameters compatible with the process of a semiconductor die I Bonding mechanism still unclear

I Some investigations performed, much more needed

33 / 45 New Packaging Structures – Micro posts (B MOUAWAD)

I “Wafer”-level process

I Based on copper electroplating

I Assembly of DBC/die/DBC “sandwiches”

I No damage to dies

240

25 210

180 20 150

15 120

90 10 60

5 30

0 0 0 5 10 15 20 25 34 / 45 New Packaging Structures – Micro posts (B MOUAWAD)

200

150

100

Forward Current [A] 50

To 247 Sandwich package 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Forward Voltage [V]

16000

14000 I Higher resistance than expected 12000 I Due to seed layer/die topside interface 10000 8000 02 I Would not happen with suitable dies Intensity Ti 6000 Al2 AlO2 4000 I Simple and reproducible process TiO 2000 CuO Cu2 0 I Tens of sample assembled, with good yield 200 300 400 500 600 700 800 Sputter time [s] 35 / 45 Conclusions on New Packaging Structures

I Several sandwich conﬁgurations:

I Solder I Silver sintering I Direct Cu/Cu bonding (Micro-posts) I More suited to direct liquid cooling

I Solid/liquid interface I Homogeneous compressing force I No issue with ﬂatness I Remaining issues:

I Dies topside ﬁnish I Mechanical relief structures I Intrinsic thermo-mechanical reliability

I Need for further investigation

36 / 45 Conclusions on New Packaging Structures

I Several sandwich conﬁgurations:

I Solder I Silver sintering I Direct Cu/Cu bonding (Micro-posts) I More suited to direct liquid cooling

I Solid/liquid interface I Homogeneous compressing force I No issue with ﬂatness I Remaining issues:

I Dies topside ﬁnish I Mechanical relief structures I Intrinsic thermo-mechanical reliability

I Need for further investigation

36 / 45 Conclusions on New Packaging Structures

I Several sandwich conﬁgurations:

I Solder I Silver sintering I Direct Cu/Cu bonding (Micro-posts) I More suited to direct liquid cooling

I Solid/liquid interface I Homogeneous compressing force I No issue with ﬂatness I Remaining issues:

I Dies topside ﬁnish I Mechanical relief structures I Intrinsic thermo-mechanical reliability

I Need for further investigation

36 / 45 Outline

Professional Record

Background

Contributions Packaging for High Temperatures New Packaging Structures for Power Modules

Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages

Conclusion

36 / 45 Outline

Professional Record

Background

Contributions Packaging for High Temperatures New Packaging Structures for Power Modules

Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages

Conclusion

36 / 45 J.-L. Marchesini et al., “Realization and Characterization of an IGBT Module Based on the Power Chip-on-Chip 3D Concept”, ECCE 2014

E. Hoene, “Ultra Low Inductance Package for SiC” ECPE workshop on power boards, 2012

New Packaging Structures for Power Modules

I Simulation-based design to evaluate

I Thermo-mechanical stress in assemblies (esp. “Sandwiches”) I Thermal resistance I Parasitic inductance/capacitance I Development of structures for fast wide-bandgap devices:

I Die stacking (Chip-On-Chip, G2ELab) for low EMI I PCB Embedding

37 / 45 New Packaging Structures for Power Modules

I Simulation-based design to evaluate

I Thermo-mechanical stress in assemblies (esp. “Sandwiches”) I Thermal resistance I Parasitic inductance/capacitance I Development of structures for fast wide-bandgap devices:

I Die stacking (Chip-On-Chip, G2ELab) for low EMI I PCB Embedding

J.-L. Marchesini et al., “Realization and Characterization of an IGBT Module Based on the Power Chip-on-Chip 3D Concept”, ECCE 2014

E. Hoene, “Ultra Low Inductance Package for SiC” ECPE workshop on power boards, 2012

37 / 45 Flex-based SiC half-bridge PCB Embedding, ANR Project interconnect (Industrial project) ETHAER

New Packaging Structures – PCB Embedding PCB technology offers:

I High interconnect density (multilayers, < 50 µm tracks)

I Advanced design tools

I Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

I Silver sintering for accurate positionning of devices

I Adaptation of die topside metallization

I Advanced DBC etching for thermal management

38 / 45 PCB Embedding, ANR Project ETHAER

New Packaging Structures – PCB Embedding PCB technology offers:

I High interconnect density (multilayers, < 50 µm tracks)

I Advanced design tools

I Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

I Silver sintering for accurate positionning of devices

I Adaptation of die topside metallization

I Advanced DBC etching for thermal management

Flex-based SiC half-bridge

interconnect (Industrial project) 38 / 45 New Packaging Structures – PCB Embedding PCB technology offers:

I High interconnect density (multilayers, < 50 µm tracks)

I Advanced design tools

I Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

I Silver sintering for accurate positionning of devices

I Adaptation of die topside metallization

I Advanced DBC etching for thermal management

Flex-based SiC half-bridge PCB Embedding, ANR Project

interconnect (Industrial project) ETHAER 38 / 45 New Packaging Structures – PCB Embedding PCB technology offers:

I High interconnect density (multilayers, < 50 µm tracks)

I Advanced design tools

I Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

I Silver sintering for accurate positionning of devices

I Adaptation of die topside metallization

I Advanced DBC etching for thermal management

Flex-based SiC half-bridge PCB Embedding, ANR Project

interconnect (Industrial project) ETHAER 38 / 45 New Packaging Structures – PCB Embedding PCB technology offers:

I High interconnect density (multilayers, < 50 µm tracks)

I Advanced design tools

I Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

I Silver sintering for accurate positionning of devices

I Adaptation of die topside metallization

I Advanced DBC etching for thermal management

Flex-based SiC half-bridge PCB Embedding, ANR Project

interconnect (Industrial project) ETHAER 38 / 45 New Packaging Structures – PCB Embedding PCB technology offers:

I High interconnect density (multilayers, < 50 µm tracks)

I Advanced design tools

I Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

I Silver sintering for accurate positionning of devices

I Adaptation of die topside metallization

I Advanced DBC etching for thermal management

Flex-based SiC half-bridge PCB Embedding, ANR Project

interconnect (Industrial project) ETHAER 38 / 45 New Packaging Structures – PCB Embedding PCB technology offers:

I High interconnect density (multilayers, < 50 µm tracks)

I Advanced design tools

I Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

I Silver sintering for accurate positionning of devices

I Adaptation of die topside metallization

I Advanced DBC etching for thermal management

Flex-based SiC half-bridge PCB Embedding, ANR Project

interconnect (Industrial project) ETHAER 38 / 45 New Packaging Structures – PCB Embedding PCB technology offers:

I High interconnect density (multilayers, < 50 µm tracks)

I Advanced design tools

I Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

I Silver sintering for accurate positionning of devices

I Adaptation of die topside metallization

I Advanced DBC etching for thermal management

Flex-based SiC half-bridge PCB Embedding, ANR Project

interconnect (Industrial project) ETHAER 38 / 45 New Packaging Structures – PCB Embedding PCB technology offers:

I High interconnect density (multilayers, < 50 µm tracks)

I Advanced design tools

I Simple process (can be performed in-house, 3DPHI, industry)

To take advantage of previous developments

I Silver sintering for accurate positionning of devices

I Adaptation of die topside metallization

I Advanced DBC etching for thermal management

Flex-based SiC half-bridge PCB Embedding, ANR Project

interconnect (Industrial project) ETHAER 38 / 45 Outline

Professional Record

Background

Contributions Packaging for High Temperatures New Packaging Structures for Power Modules

Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages

Conclusion

38 / 45 Reliability of High Temperature Packaging

Source: Pressureless Sintering of Microscale Silver Paste for 300°C Applications, Fang Yu et al., IEEE trans. on CMPT, vol. 5, No.9, p 1258–1264

I Silver sintered assemblies are increasingly available in the industry I Need to assess its reliability for high temperature

I Assessment of migration phenomenon

I Next step: effect of atmosphere (oxygen content)

I Use of pressureless sintered silver as a material model

I Behaviour in high temperature storage conditions I Mechanisms are accelerated and highlighted

39 / 45 Integration in High Temperature

I Other elements of packaging:

I High temperature ageing of PCBs I Thermo-mechanical analysis of structures I Manufacturing of integrated inductors (C. MARTIN)

40 / 45 Outline

Professional Record

Background

Contributions Packaging for High Temperatures New Packaging Structures for Power Modules

Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages

Conclusion

40 / 45 Packaging of high voltage power devices

I Context: Supergrid Institute

I Development of HVDC networks

I Need for HV devices (>10 kV) and packaging

I Increase in switching speed

I Ensure low inductance I Large creepage distance (> 8 cm !)

I High conversion efﬁciency

I Trade-off: Insulation/Junction temp. § (Very) efﬁcient cooling required!

Source: 10 kV SiC MOSFET from Wolfspeed

41 / 45 Special Features of High Voltage Packaging

I Series connexions of many switches

I A single failed switch should not stop the converter § Fail-to-short behaviour I For Si dies:

I Melting of silicon I Alloying with surrounding metals I Formation of conductive area

I SiC only sublimes at > 2500°C!

Source Gunturi, S. et al. “Innovative Metal System for IGBT Press Pack Modules”, ISPSD, 2003, 4

42 / 45 Special Features of High Voltage Packaging

I Series connexions of many switches

I A single failed switch should not stop the converter § Fail-to-short behaviour I For Si dies:

I Melting of silicon I Alloying with surrounding metals I Formation of conductive area

I SiC only sublimes at > 2500°C!

Source Gunturi, S. et al. “Innovative Metal System for IGBT Press Pack Modules”, ISPSD, 2003, 4

42 / 45 Special Features of High Voltage Packaging

I Series connexions of many switches

I A single failed switch should not stop the converter § Fail-to-short behaviour I For Si dies:

I Melting of silicon I Alloying with surrounding metals I Formation of conductive area

I SiC only sublimes at > 2500°C!

Source Gunturi, S. et al. “Innovative Metal System for IGBT Press Pack Modules”, ISPSD, 2003, 4

42 / 45 Outline

Professional Record

Background

Contributions Packaging for High Temperatures New Packaging Structures for Power Modules

Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages

Conclusion

42 / 45 Conclusion

I PhD 11 years ago

I From electrical engineering to packaging I 11 PhD students supervised (5 theses defended)

I Until recently, most activity on high temperature packaging I Broadening of my research focus

I High temperature packaging I High voltage packaging I Integration for WBG devices I Packaging is an active domain

I Strong support from the industry I Many scientiﬁc challenges

43 / 45 Acknowledgements

[email protected]

44 / 45 Credits

I picture of the Airbus A350: airbus

I picture of the Toyota Prius: Picture by Pawel Golsztajn, CC-SA, available on Wikimedia Commons http: //commons.wikimedia.org/wiki/File:Toyota_Prius.2.JPG

I geothermal power plant: http://energy.gov/eere/ geothermal/photos/geothermal-photo-gallery

I picture of Jupiter: NASA http://en.wikipedia.org/wiki/File:PIA04866_modest.jpg

45 / 45