Enhance Reliability of Semiconductor Devices in Power Converters

electronics

Review Enhance Reliability of Semiconductor Devices in Power Converters

Minh Hoang Nguyen and Sangshin Kwak * School of Electrical Engineering, Chung-Ang University, Seoul 06974, Korea; [email protected] * Correspondence: [email protected]; Tel.: +82-02-820-5346

Received: 18 November 2020; Accepted: 2 December 2020; Published: 4 December 2020

Abstract: As one of the most vulnerable components to temperature and temperature cycling conditions in power electronics converter systems in these application fields as wind power, electric vehicles, drive system, etc., power semiconductor devices draw great concern in terms of reliability. Owing to the wide utilization of power semiconductor devices in various power applications, especially insulated gate bipolar transistors (IGBTs), power semiconductor devices have been studied extensively regarding increasing reliability methods. This study comparatively reviews recent advances in the area of reliability research for power semiconductor devices, including condition monitoring (CM), active thermal control (ATC), and remaining useful lifetime (RUL) estimation techniques. Different from previous review studies, this technical review is carried out with the aim of providing a comprehensive overview of the correlation between various enhancing reliability techniques and discussing the corresponding merits and demerits by using 144 related up-to-date papers. The structure and failure mechanism of power semiconductor devices are first investigated. Different failure indicators and recent associated CM techniques are then compared. The ATC approaches following the type of converter systems are further summarized. Furthermore, RUL estimation techniques are surveyed. This paper concludes with summarized challenges for future research opportunities regarding reliability improvement.

Keywords: power semiconductor device; condition monitoring (CM); active thermal control (ATC); remaining useful lifetime (RUL); temperature; reliability

1. Introduction Power semiconductor devices are the core of power electronic systems. The power semiconductor devices serve as a crucial role in power conversion systems and additionally are extensively utilized in many applications such as renewable energy systems, electric vehicles, machine drive, and industrial equipment [1–4]. These applications oﬀer a high demand for reliable operation of the power electronics system. From the engineering point of view, reliability is the probability that a system or component will carry out a required task without failure under a particular condition for a designated time [5,6]. As stated before, due to the indispensable role of power semiconductor devices of the power electronics system, power semiconductor devices have a substantial inﬂuence on the reliability of the power electronics system. Following a conducted survey [7], the power semiconductor devices are ranked as the most vulnerable components in the system overall with 31% of the responders, as shown in Figure1. The harsh environmental conditions and thermal operating conditions can potentially trigger both die and package-related degradation in power semiconductor devices [8,9], whereas 60% of failures of which are caused by thermal stress [10]. For every 10 ◦C increase in temperature in the working temperature range of power semiconductor devices, the failure probability increases two times [11]. This is because the die and packaging of power semiconductor devices consist of

Electronics 2020, 9, 2068; doi:10.3390/electronics9122068 www.mdpi.com/journal/electronics Electronics 2020, 9, x FOR PEER REVIEW 2 of 37 Electronics 2020, 9, 2068 2 of 37 packaging of power semiconductor devices consist of several layers of different materials, each having different coefficients of thermal expansion. For a long time, the accumulated damage in power severaldevices layers can lead of di fftoerent an abrupt materials, failure, each which having causes different costly coeffi systemcients ofdowntime thermal expansion.and damage For to a longother time,critical the system accumulated components. damage in power devices can lead to an abrupt failure, which causes costly system downtime and damage to other critical system components.

17% 18% 2%

5% 15% 12%

31%

Capacitors Resistors Inductors Connectors Power devices Gate drivers Other

Figure 1. Survey of fragile components in the power system. Figure 1. Survey of fragile components in the power system. According to the discussion above, it can be noticed that the reliability of the power system is According to the discussion above, it can be noticed that the reliability of the power system is related to the reliability of the power semiconductor devices. The power converter fault is largely related to the reliability of the power semiconductor devices. The power converter fault is largely due due to the failure of power semiconductor devices. Therefore, increasing the reliability of power to the failure of power semiconductor devices. Therefore, increasing the reliability of power semiconductor devices is essential to enhance the reliability of the power electronics system. Until now, semiconductor devices is essential to enhance the reliability of the power electronics system. Until many attempts have been made to address the vulnerable problem of power semiconductor devices, now, many attempts have been made to address the vulnerable problem of power semiconductor including condition monitoring (CM), active thermal control (ATC), and remaining useful lifetime devices, including condition monitoring (CM), active thermal control (ATC), and remaining useful (RUL) estimation techniques, as shown in Figure2. The basis of CM is to select a physical measurement, lifetime (RUL) estimation techniques, as shown in Figure 2. The basis of CM is to select a physical which indicates that failures or degradation can occur in the power system. Based on the result of measurement, which indicates that failures or degradation can occur in the power system. Based on CM, the proper actions can be applied to avoid sudden system shutdown or scheduled maintenance. the result of CM, the proper actions can be applied to avoid sudden system shutdown or scheduled The implementation of CM requires a power semiconductor device’s failure mechanism knowledge, maintenance. The implementation of CM requires a power semiconductor device’s failure which will be presented and discussed in this paper. In addition to CM, ATC is another method to mechanism knowledge, which will be presented and discussed in this paper. In addition to CM, ATC improve the reliability of power semiconductor devices. As depicted in Figure2, the degradation is another method to improve the reliability of power semiconductor devices. As depicted in Figure indicator information obtained from online CM techniques can be applied, to not only passively update, 2, the degradation indicator information obtained from online CM techniques can be applied, to not but also actively control the system lifetime, using ATC. As stated before, thermal stress is the root only passively update, but also actively control the system lifetime, using ATC. As stated before, cause of the failures in power semiconductor devices. The ATC method eases the thermal stress of the thermal stress is the root cause of the failures in power semiconductor devices. The ATC method components either by lowering the temperature fluctuation amplitude or by lowering the average eases the thermal stress of the components either by lowering the temperature fluctuation amplitude temperature, while the converter does not need any modification, meaning that there may be no extra or by lowering the average temperature, while the converter does not need any modification, cost for the enhancement of the converter design or components. However, the trade-off between the meaning that there may be no extra cost for the enhancement of the converter design or components. thermal control capability and the performance of the power system should be considered. Regarding However, the trade-off between the thermal control capability and the performance of the power the RUL estimation technique, it is generally utilized to design ATC and verify the effect of ATC. system should be considered. Regarding the RUL estimation technique, it is generally utilized to The relation among the CM, ATC, and RUL techniques is described in Figure2. design ATC and verify the effect of ATC. The relation among the CM, ATC, and RUL techniques is In 2010, Yang et al. conducted a review of CM approaches [12]. This study described the CM described in Figure 2. state-of-the-art of the power electronics in addition to the benefits and limitations of currently available CM techniques for power electronics, including insulated gate bipolar transistors (IGBTs). In 2015, Oh et al. proposed a review of IGBT CM and prognostic principle and related physics-of-failure [13]. Meanwhile, the author in [14] focused on implementation issues of CM approaches. Another review was proposed in [15], but concentrating on the reliability of wind turbines only. In terms of ATC techniques, a study gave an overview of various ATC approaches based on four typical mission profiles [16]. Furthermore, a recent comprehensive review toward the state-of-the-art in failure and lifetime predictions of power electronics devices was introduced in [17]. It can be noticed that the previous studies have concentrated on a specific technique corresponding to enhancing the reliability of power electronic converters. Although the power semiconductor device reliability has been

Electronics 2020, 9, 2068 3 of 37 reviewed systematically in [18,19], the relation among techniques has not been discussed. These are the motivations of this review paper. In this paper, new findings on CM have been reported, especially on online CM methods for both IGBT and silicon carbide metal-oxide semiconductor field-effect transistor (SiC MOSFET), which can be employed in real-time operation of the power converters. The various ATC approaches are classified according to the perspective of converter type to develop an accurate and suitable solution for extending the lifetime of converter systems. Additionally, the RUL, including both model-based and data-driven approaches, will be reported. Electronics 2020, 9, x FOR PEER REVIEW 3 of 37

Monitored parameters: temperature sensitive electrical Condition parameters (TSEPs), Monitoring (CM) temperature, etc. Unit

Fixing

Active thermal Action to be taken Power Converter control (ATC) Unit Temperature Verification Maintenance

Remaining useful lifetime (RUL) estimation Unit

Figure 2. Relation am amongong condition monitoring (CM) (CM),, active active thermal thermal control control ( (ATC),ATC), and remaining useful lifetime ( (RUL)RUL) estimation techniques in the power system.

In light2010, ofYang the above,et al. conducted this paper presentsa review an of overview CM approaches of the failure [12]. mechanisms,This study described associated the failure CM stateindicators,-of-the- andart CMof the techniques power electronics of IGBTs and in SiCaddition MOSFETs. to the The benefits ATC methodsand limitations and RUL of estimation currently availableapproaches CM are techniques also reported. for power This electronics, paper is organized including as insulated Section2 presentsgate bipolar the failuretransistors mechanism, (IGBTs). Infailure 2015, indicators, Oh et al. proposed and CM techniquesa review of ofIGBT IGBT CM and and SiC prognostic MOSFET; principle Section3 and summarizes related physics the ATC-of- failuremethod [13]. from Meanwhile, different types the author of converters; in [14] focused Section4 onsummarizes implementation the RUL issues estimation of CM approaches;approaches. Anothera discussion review on was the reliabilityproposed ofin power[15], but semiconductor concentrating deviceson the reliability and the relation of wind among turbines enhancing only. In termsreliability of ATC techniques techniques, is given a study in Section gave an5, overv and Sectioniew of6 various draws theATC conclusion. approaches based on four typical mission profiles [16]. Furthermore, a recent comprehensive review toward the state-of-the-art in failure2. Condition and lifetime Monitoring predictions Techniques of power electronics devices was introduced in [17]. It can be noticed that theBecause previous of the studies relatively have large concentrated number of on publications a specific dealingtechnique with corresponding CM, this report to isenhancing therefore the not reliabilityexhaustive. of This power study electronic attempts converters. to focus on Although recent techniques the power proposed semiconductor since the device review reliability performed has by beenYang reviewed et al. in 2010 systematically [12], and the in study[18,19], simultaneously the relation among is more techniques concentrated has not on been online discussed. CM methods, These arewhich the canmotivations be employed of this in real-timereview paper. operation In this of paper, the power new converters.findings on TheCM CMhave definition been reported, can be especiallyexplained thaton online the technique CM methods targets for tracking both IGBT variations and silicon in the carbide electrical metal parameters-oxide semiconductor that are an indication field- effectof device transistor degradation (SiC MOSFET), or incipient which fault [20can]. Becausebe employed monitoring in real all-time of the operation electrical of parameters the power is converters.not practicable The various in a power ATC converter, approaches specific are classified parameters according should to bethe recognized perspective depending of converter on type the todominant develop aging an accurate failure mechanism. and suitable In additionsolution to for the extending silicon (Si)-based the lifetime semiconductor of converter device systems. such as Additionally,the IGBT based the power RUL, converter, including SiC both semiconductor model-based devicesand data have-driven been approaches, developed and will commercialized be reported. recentlyIn light due of to the their above, superior this propertiespaper presents compared an overview to Si counterparts, of the failure like mechanisms, the ability toassociated operate failureat higher indicators, temperatures, and CM increased techniques blocking of IGBTs voltages, and SiC faster-switching MOSFETs. The speeds, ATC andmethods higher and thermal RUL estimationconductivity approaches [21–24]. However, are also comparedreported. This to IGBT, paper degradation is organized monitoring as Section methods 2 presents for SiCthe devicesfailure mechanism,have not been failure reported indicators, as extensively and CM in literaturetechniques due of toIGBT the relativeand SiC nascence MOSFET; of Section SiC device 3 summarizes technology. theTherefore, ATC method in this study, from thedifferent failure mechanismtypes of converters; and the CM Section techniques 4 summarizes for IGBT andthe SiCRUL MOSFET estimation will approaches;be reviewed a together. discussion on the reliability of power semiconductor devices and the relation among enhancing reliability techniques is given in Section 5, and Section 6 draws the conclusion.

2. Condition Monitoring Techniques Because of the relatively large number of publications dealing with CM, this report is therefore not exhaustive. This study attempts to focus on recent techniques proposed since the review performed by Yang et al. in 2010 [12], and the study simultaneously is more concentrated on online CM methods, which can be employed in real-time operation of the power converters. The CM definition can be explained that the technique targets tracking variations in the electrical parameters that are an indication of device degradation or incipient fault [20]. Because monitoring all of the electrical parameters is not practicable in a power converter, specific parameters should be

Electronics 2020, 9, x FOR PEER REVIEW 4 of 37

recognized depending on the dominant aging failure mechanism. In addition to the silicon (Si)-based semiconductor device such as the IGBT based power converter, SiC semiconductor devices have been developed and commercialized recently due to their superior properties compared to Si counterparts, like the ability to operate at higher temperatures, increased blocking voltages, faster-switching speeds, and higher thermal conductivity [21–24]. However, compared to IGBT, degradation monitoring methods for SiC devices have not been reported as extensively in literature due to the Electronics 2020, 9, 2068 4 of 37 relative nascence of SiC device technology. Therefore, in this study, the failure mechanism and the CM techniques for IGBT and SiC MOSFET will be reviewed together. 2.1. Failure Mechanism and Indicators 2.1. Failure Mechanism and Indicators IGBT and SiC MOSFET have a similar chip-level structure, except for an additional p+ layer above the collectorIGBT and in IGBTSiC MOSFET and an additional have a similar body diodechip-level part structure, in SiC MOSFET except and,for an as seenadditional in Figure p+ 3layera,b. Theabove most the popularcollector chip-level in IGBT and failure an additional types in IGBTbody anddiode SiC part MOSFET in SiC MOSFET is the gate and, oxide as seen degradation in Figure failure.3a,b. The The most gate oxidepopular degradation chip-level failure failure is caused types byin highIGBT temperature and SiC MOSFET and high electricis the ﬁeldgate stress.oxide degradation failure. The gate oxide degradation failure is caused by high temperature and high Compared to IGBT, SiC MOSFETs are more often applied with the higher gate-source voltage Vgs and aelectric higher field temperature stress. Compared to achieve to lower IGBT, on-state SiC MOSFET resistances are and more a smaller often applied heat sink. with This the would higher make gate- thesource gate voltage oxide more and vulnerable a higher [temperature25]. The gate to oxide achieve degradation lower on- failurestate resistance in IGBT and a SiC smaller MOSFET heat sink. This would make the gate oxide more vulnerable [25]. The gate oxide degradation failure in increases the threshold𝑉𝑉𝑔𝑔𝑔𝑔 voltage Vth [26,27]; gate leakage current [28–30]. Furthermore, since the gate oxideIGBT degradation,and SiC MOSFET the gate increases oxide capacitancethe threshold increases, voltage resulting [26,27]; in extendinggate leakage the current Miller plateau[28–30]. Furthermore, since the gate oxide degradation, the gate oxide capacitance increases, resulting in time duration tgp [31,32]. The on-state resistance can be considered𝑉𝑉𝑡𝑡ℎ as an indicator for the gate oxide degradationextending the failure Miller in plateau SiC MOSFET time duration [32–34], but [31,32]. it has been The moreon-state often resistance than not can utilized be considered to identify as an indicator for the gate oxide degradation failure in SiC MOSFET [32–34], but it has been more often the package-related failures. In the SiC MOSFET,𝑡𝑡𝑔𝑔𝑔𝑔 there exists a body diode formed by the n- drift regionthan not and utilized the well to of identify the p-type the semiconductor.package-related Infailures. addition In tothe the SiC gate MOSFET, oxide degradation, there exists thea body SiC MOSFETdiode formed body by diode the n degradation- drift region isand caused the well by theof the forward p-type voltagesemiconductor. bias stress In addition [35–37] because to the gate of theoxide stacking degradation, fault mechanism. the SiC MOSFET In this body case, diode the forwarddegradat currention is caused ﬂowing by path the forward is blocked voltage by these bias faults.stress [35 Thus,–37] because both the of on-resistance the stacking fault and forwardmechanism. voltage In this of case, the bodythe forward diode wouldcurrent increase flowing path [38]. Theis blocked on-resistance by these [35 faults.], forward Thus, voltage both the [39 on], and-resistance drain leakage and forward current voltage [25] are of considered the body asdiode indicators would forincrease the body [38]. diode The degradation.on-resistance [35], forward voltage [39], and drain leakage current [25] are considered as indicators for the body diode degradation.

Gate Gate Emitter Oxide Source Oxide (Insulating (Insulating the gate) the gate)

+ + + + p+ n n p+ p+ n n p+ p p

Body diode drift region ـdrift region SiC n ـSi n Si p+ substrate SiC n+ substrate

Collector Drain

(a) (b)

FigureFigure 3.3. ((aa)) insulatedinsulated gategate bipolarbipolar transistortransistor (IGBT)(IGBT) crosscross section,section, ((bb)) siliconsilicon carbidecarbide metal-oxidemetal-oxide semiconductorsemiconductor ﬁeld-efield-effectﬀect transistor transistor (SiC (SiC MOSFET) MOSFET) cross cross section. section.

AlthoughAlthough some some new new packaging packaging technologies technologies are introduced, are introduced, especially especially for power for modulespower modules to enhance to theenhance reliability, the reliability, still, conventional still, conventional packaging packaging and wire bonding and wire techniques bonding aretechniques utilized are for theutilized majority for the of commercialmajority of IGBTcommercial and SiC IGBT MOSFET. and SiC Figure MOSFET.4 illustrates Figure a typical4 illustrates package-level a typical structurepackage- forlevel both structure IGBT andfor SiCboth MOSFET IGBT and due SiC to themMOSFET sharing due the to same them package-level sharing the structure.same package A direct-level copper structure. bonded A (DCB)direct substrate is soldered to a baseplate. The DCB provides electrical insulation between power components and cooling systems. Further, it conducts the current via copper tracks and also provides excellent thermal. The baseplate provides thermal capacity and helps for the thermal spreading by increasing the contact area to a heat-sink. IGBT and diode chips are soldered to DCB. Bond wires are commonly utilized in order to connect the emitter of the Si/SiC chips to the substrate and in order to connect the substrate to the terminals. The chip die and the DCB, as well as the baseplate and the DCB, are commonly attached Electronics 2020, 9, x FOR PEER REVIEW 5 of 37 copper bonded (DCB) substrate is soldered to a baseplate. The DCB provides electrical insulation between power components and cooling systems. Further, it conducts the current via copper tracks and also provides excellent thermal. The baseplate provides thermal capacity and helps for the thermal spreading by increasing the contact area to a heat-sink. IGBT and diode chips are soldered to DCB. Bond wires are commonly utilized in order to connect the emitter of the Si/SiC chips to the Electronicssubstrate2020 and, 9, 2068in order to connect the substrate to the terminals. The chip die and the DCB, as well5 of 37as the baseplate and the DCB, are commonly attached by solder. It can be observed in Figure 4 that the IGBT and SiC MOSFET modules contain various layers, and each layer has been made of different by solder. It can be observed in Figure4 that the IGBT and SiC MOSFET modules contain various materials, resulting in a different coefficient of thermal expansion (CTE). The switching devices layers, and each layer has been made of different materials, resulting in a different coefficient of thermal produce the switching loss and conduction loss, and they produce thermal stress in the power expansion (CTE). The switching devices produce the switching loss and conduction loss, and they produce module [40–42]. The converter load variation, the periodical commutation of the power switching thermal stress in the power module [40–42]. The converter load variation, the periodical commutation of device, and the ambient temperature change cause the temperature variation in the power the power switching device, and the ambient temperature change cause the temperature variation in the semiconductor module. The significant CTE mismatch between the bond wires and chip under the power semiconductor module. The significant CTE mismatch between the bond wires and chip under the temperature variation causes the thermomechanical stress in bond wires and, finally, leads to bond temperature variation causes the thermomechanical stress in bond wires and, finally, leads to bond wire wire lift-off or crack failure [43,44]. The bond wire failures cause an increase in the resistance of the lift-off or crack failure [43,44]. The bond wire failures cause an increase in the resistance of the bond wires. bond wires. Consequently, the on-state voltage will increase, which can be identified to indicate Consequently, the on-state voltage will increase, which can be identified to indicate bond-wire failures bond-wire failures (on-state collector-emitter voltage , in the IGBT module and on-state drain- (on-state collector-emitter voltage Vce,on in the IGBT module and on-state drain-source voltage Vds,on in source voltage , in SiC MOSFET module) [26,45–47] . Other indicators of the bond wire failure SiC MOSFET module) [26,45–47]. Other indicators of the𝑉𝑉 bond𝑐𝑐𝑐𝑐 𝑜𝑜𝑜𝑜 wire failure are listed in Table1. Another are listed in Table 1. Another dominant failure mechanism that occurs in IGBT and SiC MOSFET is dominant failure𝑉𝑉 mechanism𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 that occurs in IGBT and SiC MOSFET is solder layer fatigue. The two solder solder layer fatigue. The two solder layers in the IGBT/SiC MOSFET module, as shown in Figure 4, layers in the IGBT/SiC MOSFET module, as shown in Figure4, are the die attach between the Si /SiC are the die attach between the Si/SiC die and DCB and substrate attach between DCB and baseplate. die and DCB and substrate attach between DCB and baseplate. The temperature fluctuations and the The temperature fluctuations and the CTE mismatches between the Si/SiC chip and solder material, CTE mismatches between the Si/SiC chip and solder material, DCB, and solder material slowly generate DCB, and solder material slowly generate cracks and voids in the solder layer, resulting in solder cracks and voids in the solder layer, resulting in solder layer fatigue. The solder layer failure reduces the layer fatigue. The solder layer failure reduces the thermal dissipation capability, which leads to the thermal dissipation capability, which leads to the increased thermal resistance R . Thus, the junction increased thermal resistance . Thus, the junction temperature of the powerth devices rises. As for temperature of the power devices rises. As for solder layer failure, the junction-to-case thermal resistance solder layer failure, the junction-to-case thermal resistance (or thermal impedance) is usually utilized (or thermal impedance) is usually𝑅𝑅𝑡𝑡ℎ utilized as an indicator to indicate the solder fatigue in IGBT and SiC as an indicator to indicate the solder fatigue in IGBT and SiC MOSFET [48,49]. Additionally, the MOSFET [48,49]. Additionally, the solder layer resistance and junction temperature are utilized to indicate solder layer resistance and junction temperature are utilized to indicate the solder layer fatigue in SiC the solder layer fatigue in SiC MOSFET [50] and IGBT [51,52], respectively. The typical failure indicators MOSFET [50] and IGBT [51,52], respectively. The typical failure indicators of IGBT and SiC MOSFET of IGBT and SiC MOSFET are summarized in Table1. are summarized in Table 1.

Bond wire

IGBT die/ SiC MOSFET die

Solder Substrate conductor Substrate insulator }DCB Substrate conductor Solder Baseplate

FigureFigure 4. 4.IGBT IGBT/Sic/Sic MOSFET MOSFET package-level package-level structure. structure.

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Table 1. Typical failure indicators of IGBT and SiC MOSFET.

.5 Failure Mechanism Indicators Types IGBT SiC MOSFET IGBT SiC MOSFET

Threshold voltage Gate leakage current Miller Plateau time duration

High temperature, high electric Gate oxide ﬁeld Drain leakage current Miller Plateau voltage amplitude

On-resistance Forward Forward voltage Body diode voltage bias Drain stress leakage current

On-state resistance On-state voltage

Bond wire Combination of CTE mismatch Voltage between Miller Plateau fatigue and temperature ﬂuctuation Kelvin, power source time duration The eddy current in Short-circuit current bond wires

Junction-to-case thermal resistance

Solder layer Combination of CTE mismatch Junction temperature fatigue and temperature ﬂuctuation Voltage change rate dVce/dt Solder Current change rate layer resistance dIc/dt Low order harmonic

2.2. CM for IGBT

2.2.1. Monitoring Collector-Emitter on-State Voltage The on-state voltage of an IGBT is a representative electrical parameter indicating the aging failures, and it is the favored indicator for CM technique, which can be recognized by various previous studies on Vce,on [53–56]. The increase of on-state voltage is usually utilized as an indicator for wire bonding failure. For instance, the criterion to detect bond wire failure was a +5% [53,54] 15% [55] and 20% [53] increment of Vce,on from the initial value. From the discussion in [13], the real-time monitoring Vce,on is challenging because the measured value of Vce,on can be overwhelmed by signal noise or disturbance during switching. Furthermore, the Vce,on is influenced by the junction temperature. Therefore, the measurement of Vce,on should be carefully conducted by evaluating the effect of individual circuit components, corresponding failure mechanism, and junction temperature. One of the first online Vce,on measurements was proposed in [57], using two diodes derived from a typical desaturation protection circuit. This approach can measure Vce,on under the converter operation, but the deviation between the two diodes could lead to the measurement error. Therefore, this technique Electronics 2020, 9, 2068 7 of 37

requires strict requirements regarding that two diodes as the similar currents flowing through, the similar junction temperature level, and forward voltage temperature coefficients. A diode with low reverse Electronics 2020, 9, x FOR PEER REVIEW 7 of 37 recovery and high blocking voltage should be used to ensure accurate measurement. In order to resolve the previous problem of CM using Vce,on, the author in [58] proposed an intelligent on-state dependingcollector-emitter on converter voltage opera measurementtion conditions. circuit The and proposed CM strategies real depending-time measurement on converter operation circuit of 푉푐푒,표푛 is shown conditions.in Figure The5. For proposed instance, real-time in order measurement to measure circuit the of V푉ce푐푒,on,표푛is shownof the inupper Figure IGBT,5. For instance,the drain of n- channel smallin order-signal to measure MOSFET the V cein,on theof themeasurement upper IGBT, the circuit drain is of connected n-channel small-signal with the collector MOSFET inof thethe upper measurement circuit is connected with the collector of the upper IGBT (TUH). The measurement of IGBT (푇푈퐻). The measurement of 푉푐푒,표푛 is conducted during a positive 퐼퐷 current period as a positive Vce,on is conducted during a positive ID current period as a positive value. The measurement of Vce,on for value. The measurement of 푉푐푒,표푛 for the lower IGBT also can be implemented in the same manner. the lower IGBT also can be implemented in the same manner. The proposed online Vce,on measurement The proposedapproach online was conducted 푉푐푒,표푛 measurement for both converter approach application was with conducted the fixed operating for both condition converter and varied application with the operating fixed operating condition, considering condition the and temperature varied operating dependence condition,of Vce,on, which considering confirmed the the feasibility temperature dependenceand eofff ectiveness푉푐푒,표푛, which of the confirmed proposed method. the feasibility and effectiveness of the proposed method.

R VC ID D S + Vout +VGS VCC Upper IGBT G

TUH

V CC Figure 5. Conﬁguration of V measurement circuit for upper IGBT using a depletion mode MOSFET. Figure 5. Configuration of 푉푐푒,표푛ce,on measurement circuit for upper IGBT using a depletion mode MOSFET.Another real-time on-state voltage calculation based on the control variables and junction temperature for modular multilevel converter (MMC) submodule (SM) IGBT was proposed in [59]. AnotherThe on-state real-time voltage on of-state IGBT SMs voltage in MMCs calculation is calculated based from theon on-state the control resistance variables as follow: and junction temperature for modular multilevel converter (MMC) submodule (SM) IGBT was proposed in [59]. Vce,on = Rce Ic + Vce . (1) The on-state voltage of IGBT SMs in MMCs is calculated× from0 the on-state resistance as follow: The correlation between the on-state resistance and the junction temperature for a new IGBT is 푉푐푒,표푛 = 푅푐푒 × 퐼푐 + 푉푐푒0. (1) usually given in the datasheet. For the certain aging state as a solder layer, the on-state resistance at a The particularcorrelation junction between temperature the on can-state be describedresistance as following:and the junction temperature for a new IGBT is usually given in the datasheet. For the certain aging state as a solder layer, the on-state resistance at Rce,T = Rce + Tj 125 kce, (2) a particular junction temperature can be described,125 as following− × :

where Rce,T is the on-state resistance at a specific junction temperature, Tj is the junction temperature, 푅푐푒,푇 = 푅푐푒,125 + (푇푗 − 125) × 푘푐푒, (2) and kce is the slope value of Rce T characteristic curve. A function sets of the on-state resistance are − j deduced by applying the Kirchhoff voltage laws (KVL) in one MMC arm for positive and negative current where 푅푐푒,푇 is the on-state resistance at a specific junction temperature, 푇푗 is the junction directions independently. Consequently, the on-state voltage is calculated following the matrix format of temperature, and 푘 is the slope value of 푅 − 푇 characteristic curve. A function sets of the on- the on-state resistance.푐푒 The proposed measurement푐푒 푗 method is implemented repeatedly, and the results state resistanceare continuously are deduced calculated by every applying sampling the instant. Kirchhoff Hence, voltage the Kalman laws filter (KVL) is utilized in to one enhance MMC the arm for positive calculation and negative accuracy. current This proposed directions technique independently. does not require the Consequently, external circuit as the the method on-state in [59 ] butvoltage is calculatedneeds following a relatively the high matrix calculation format effort of in the the on controller.-state resistance. Additionally, theThe accuracy proposed of results measurement in this method method is implementedstrongly depends repeatedly, on the measurement and the results accuracy are of junction continuously temperature, calculated capacitor voltages, every arm sampling voltages, instant. and arm currents. Compared with previous approaches, this method can reduce the costs and avoid the Hence, the Kalman filter is utilized to enhance the calculation accuracy. This proposed technique modification of the system. However, it also requires to build a more complex model of the IGBT considering does not requirethe coupling the relation external to ensure circui thet as accuracy the method of measurements. in [59] but needs a relatively high calculation effort in the controller. Additionally, the accuracy of results in this method strongly depends on the measurement accuracy of junction temperature, capacitor voltages, arm voltages, and arm currents. Compared with previous approaches, this method can reduce the costs and avoid the modification of the system. However, it also requires to build a more complex model of the IGBT considering the coupling relation to ensure the accuracy of measurements.

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2.2.2. Monitoring Miller Plateau Time Duration In [60], an in situ CM technique for IGBTs based on the Miller plateau duration during the turn-on transition was proposed. As illustrated in Figure6, the configuration of the Miller plateau duration detection circuit includes four main parts: the differentiator stage, the comparator stage, the reference voltage setting stage, and the isolation stage [60]. The gate voltage signal is received and differentiated by using a simple RC network. A fixed reference voltage, which represents the rising rate threshold of the gate voltage signal, can be utilized for comparison. Besides, an adjustable reference voltage that depends on the differentiator output can be generated by using a voltage reference generating circuit and voltage divider R6, R7, R8 to implement the measurement under Electronicsdifferent 20 operating20, 9, x FORconditions. PEER REVIEW The comparison between the differentiator output and the adjustable8 of 37 reference voltage is employed to produce the double-pulse signal, which deduces the information reference voltage is employed to produce the double-pulse signal, which deduces the information of of Miller plateau duration. The isolation stage is utilized to isolate the analog circuit and the digital Miller plateau duration. The isolation stage is utilized to isolate the analog circuit and the digital circuit. The main design requirements of the proposed measurement circuit can be listed as the time circuit. The main design requirements of the proposed measurement circuit can be listed as the time constant should be less than 1/10 the width of the input signal, the differential capacitance must be constant should be less than 1/10 the width of the input signal, the differential capacitance must be smaller than the input capacitance of the devices under tests (DUT), and the load resistance must be smaller than the input capacitance of the devices under tests (DUT), and the load resistance must be small enough to achieve high bandwidth. Although this method can be used without interrupting small enough to achieve high bandwidth. Although this method can be used without interrupting system operation, it requires an accurate calibration procedure to avoid the effect of the changing system operation, it requires an accurate calibration procedure to avoid the effect of the changing operation points. Moreover, the practical implementation of this method is preferred for the IGBT in a operation points. Moreover, the practical implementation of this method is preferred for the IGBT in low-switching-speed application where the measurement uncertainty is reduced. a low-switching-speed application where the measurement uncertainty is reduced.

Reference tracking stage

D1 R4

C D2 D3 − 1 − + +

C3 R3 R1 C4 Differential stage R8 R6 R7 Isolation stage − + Comparative stage

FigureFigure 6. 6. ConfigurationConﬁguration of of tgp measurement circuit.

2.2.3. Monitoring Threshold Voltage 𝑡𝑡𝑔𝑔𝑔𝑔 2.2.3. Monitoring Threshold Voltage The threshold voltage is the minimum gate-emitter voltage Vge required to form an inversion The threshold voltage is the minimum gate-emitter voltage required to form an inversion layer at the interface between the substrate region and the gate oxide at the MOS-structure in the IGBT. layer at the interface between the substrate region and the gate oxide at the MOS-structure in the This inversion layer constitutes a conducting channel that allows𝑉𝑉𝑔𝑔 the𝑔𝑔 collector current to pass from IGBT. This inversion layer constitutes a conducting channel that allows the collector current to pass collector to emitter. It can be described as: from collector to emitter. It can be described as: p 4ε qN Ψ 4 S A B Vth = VFB + 2ΨB + , (3) = + 2 + COX , (3) � 𝜀𝜀𝑆𝑆𝑞𝑞𝑁𝑁𝐴𝐴Ψ𝐵𝐵 where V is the flat-band voltage,𝑉𝑉q𝑡𝑡ℎis the𝑉𝑉𝐹𝐹𝐹𝐹 elementaryΨ𝐵𝐵 charge of the electron, ε is the silicon dielectric where FB is the flat-band voltage, is the elementary𝐶𝐶 𝑂𝑂𝑂𝑂charge of the electron,S is the silicon dielectricconstant, constant,NA is the doping is the concentration, doping concentration,COX is the capacitance is the capacitance of the oxide, of the and oxide,ΨB isand the bulk is 𝑉𝑉𝐹𝐹𝐹𝐹 𝑞𝑞 𝜀𝜀𝑆𝑆 potential. An increase in Vge,th was identified in thermal over-stress tests of IGBT components. the bulk potential. An𝐴𝐴 increase in , was identified𝑂𝑂𝑂𝑂 in thermal over-stress tests of IGBT𝐵𝐵 The increase in V 𝑁𝑁is considered as an indicator for𝐶𝐶 gate oxide degradation [26]. Previous studiesΨ components. The geincrease,th in , is considered as an indicator for gate oxide degradation [26]. 𝑉𝑉𝑔𝑔𝑔𝑔 𝑡𝑡ℎ have to interrupt IGBT’s operation to employ the measurements of Vge,th. In order to overcome this Previous studies have to interrupt𝑔𝑔𝑔𝑔 𝑡𝑡 ℎIGBT’s operation to employ the measurements of , . In order problem, an online measurement𝑉𝑉 method for V was proposed in [61] by using an external circuit, to overcome this problem, an online measurementge,th method for , was proposed in [61] by using 𝑉𝑉𝑔𝑔𝑔𝑔 𝑡𝑡ℎ anas shownexternal in circuit, Figure 7as. TheshownVge inis Figure obtained 7. fromThe a voltage is obtained divider from stage a voltage and an amplifier.divider stage The and voltage an 𝑉𝑉𝑔𝑔𝑔𝑔 𝑡𝑡ℎ amplifier. The voltage drop across the parasitic emitter inductance is compared with a reference 𝑉𝑉𝑔𝑔𝑔𝑔 voltage to capture the voltage value at the instant of current initiation. The captured value is utilized to estimate the threshold voltage. It should be noted that the variation of , is affected by 𝑉𝑉𝑟𝑟𝑟𝑟𝑟𝑟 temperature, so the effect of junction temperature should be combined during the , 𝑉𝑉𝑔𝑔𝑔𝑔 𝑡𝑡ℎ measurement. 𝑉𝑉𝑔𝑔𝑔𝑔 𝑡𝑡ℎ

Electronics 2020, 9, 2068 9 of 37

drop across the parasitic emitter inductance is compared with a reference voltage Vre f to capture the voltage value at the instant of current initiation. The captured value is utilized to estimate the threshold voltage. It should be noted that the variation of Vge,th is aﬀected by temperature, so the eﬀect of junction temperature should be combined during the Vge th measurement. Electronics 2020, 9, x FOR PEER REVIEW , 9 of 37

R1 C2 R2 − + Vge Vth + − R3 C5 C3 Ve R4

+ − + C4 − V Voltage divider ref stage Captured stage

FigureFigure 7. 7. ConfigurationConﬁguration of of the the Vge,,th measurementmeasurement circuit.circuit.

𝑉𝑉𝑔𝑔𝑔𝑔 𝑡𝑡ℎ 2.2.4. Monitoring Junction TemperatureTemperature andand ThermalThermal ResistanceResistance The junction temperature during converter operation can be utilized as an indicator for the CM technique [[44,45];44,45]; however, it isis didifficultﬃcult toto measuremeasure directly.directly. WithoutWithout usingusing anan integratedintegrated sensor in the devicedevice toto avoidavoid modifyingmodifying the package or housing,housing, the junction temperature in CM methods is indirectly calculated calculated by by using using the the temperature temperature-sensitive-sensitive electrical electrical parameters parameters (TSEPs). (TSEPs). The The TSEPs TSEPs can canbe divided be divided into into two two main main types: types: static static parameter parameter based based technique technique and and dynamic dynamic paramete parameterr based technique, asas shown shown in in Table Table2. The2. The various various techniques, techniques, which which use di useﬀerent different TSEPs, TSEPs, are discussed are discussed below. below. Table 2. Temperature-sensitive electrical parameters (TSEPs) for junction temperature estimation.

Table 2. Temperature-sensitive electrical parameters (TSEPs) for junction temperature estimation. Collector-emitter voltage under high currents Vce,high

CollectorCollector-emitter-emitter voltage voltage under under high high currents currents V ce,low,

Static parametersCollectorGate-emitter internal voltage resistance underRg high currents , 𝑉𝑉𝑐𝑐𝑐𝑐 ℎ𝑖𝑖𝑖𝑖ℎ Static parameters Gate internalShort circuitresistance current I sc 𝑉𝑉𝑐𝑐𝑐𝑐 𝑙𝑙𝑙𝑙𝑙𝑙 Short circuit current Gate-emitter voltage𝑅𝑅𝑔𝑔Vge Gate-emitter voltage Threshold voltage𝐼𝐼𝑠𝑠𝑠𝑠 Vth Threshold voltage 𝑔𝑔𝑔𝑔 Dynamic parameters Miller Plateau voltage𝑉𝑉 Vgp Dynamic parameters Miller Plateau voltage Turn-on/turn𝑉𝑉 o𝑡𝑡ℎﬀ delay time t /t Turn-on/turn off delay time /don do f f 𝑉𝑉𝑔𝑔𝑔𝑔 𝑑𝑑𝑑𝑑𝑑𝑑 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 Calculate the junction temperature using the on-state collector-emitter𝑡𝑡 𝑡𝑡 voltage at a high current. • Calculate the junction temperature using the on-state collector-emitter voltage at a high current.

In [[62],62], the relation between the Vce,high andand aa givengiven currentcurrent levellevel isis generatedgenerated asas aa functionfunction to estimate the junction temperature from a preliminary I-VI-V characterization curve. From this relation, 𝑉𝑉𝑐𝑐𝑐𝑐 ℎ𝑖𝑖𝑖𝑖ℎ the junction temperaturetemperature cancan bebe estimatedestimated fromfrom thethe measuredmeasured currentcurrent andand thetheV ce,on, as as follows: follows:

𝑐𝑐𝑐𝑐 𝑜𝑜𝑜𝑜 _ = ( ) × , , ( ) + , (4) T = SF V V + TB,𝑉𝑉 (4) j_est (I) × ce,measured − ce,B(I) 𝑗𝑗 𝑒𝑒𝑒𝑒𝑒𝑒 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚 𝑐𝑐𝑐𝑐 𝐵𝐵 𝐼𝐼 𝐵𝐵 where ( ) is the slope factor𝑇𝑇 as a function𝑆𝑆𝑆𝑆 � 𝑉𝑉of the current,− 𝑉𝑉 , � 𝑇𝑇 is the measured on-state where SF(I) is the slope factor as a function of the current, Vce,measured is the measured on-state Vce in real-time, in real-time,𝐼𝐼 , ( ) is the base on-state as a function of current𝑐𝑐𝑐𝑐 𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚 𝑚𝑚𝑚𝑚𝑚𝑚which can be chosen among the𝑐𝑐𝑐𝑐 Vce,B(I) is𝑆𝑆𝑆𝑆 the base on-state Vce as a function of current which can be𝑉𝑉 chosen among the characterization curves,𝑉𝑉 characterization𝑐𝑐𝑐𝑐 𝐵𝐵curves,𝐼𝐼 and is the base𝑐𝑐𝑐𝑐 temperature corresponding to base on-state . Due to and TB is the𝑉𝑉 base temperature corresponding𝑉𝑉 to base on-state Vce. Due to the effect of interconnection the effect of interconnection resistance,𝐵𝐵 which leads to lower , measurement. Subsequently,𝑐𝑐𝑐𝑐 resistance, which leads to lower𝑇𝑇Vce,high measurement. Subsequently, the estimated junction temperature𝑉𝑉 the estimated junction temperature by the , at high current is smaller than the real measured 𝑉𝑉𝑐𝑐𝑒𝑒 ℎ𝑖𝑖𝑖𝑖ℎ result. Compensation is needed to acquire accurate junction temperature estimation. The internal 𝑉𝑉𝑐𝑐𝑐𝑐 ℎ𝑖𝑖𝑖𝑖ℎ resistance variation can be described as (5), whereas the on-state voltage compensation can be expressed as (6):

= × _ × , (5)

𝑖𝑖𝑖𝑖𝑖𝑖 𝑗𝑗 𝑒𝑒𝑒𝑒𝑒𝑒 𝐻𝐻 ∆,𝑅𝑅 =×𝛼𝛼 �_𝑇𝑇 − 𝑇𝑇 ×� 𝑅𝑅𝑅𝑅𝑅𝑅× , (6) 𝑉𝑉𝑐𝑐𝑐𝑐 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 �𝑇𝑇𝑗𝑗 𝑒𝑒𝑒𝑒𝑒𝑒 − 𝑇𝑇𝐻𝐻� 𝑅𝑅𝑅𝑅𝑅𝑅 𝐼𝐼

Electronics 2020, 9, 2068 10 of 37

by the Vce,high at high current is smaller than the real measured result. Compensation is needed to acquire accurate junction temperature estimation. The internal resistance variation can be described as (5), whereas the on-state voltage compensation can be expressed as (6): ∆R = α T TH RVF, (5) int × j_est − × Vce,comp = α T TH RVF I, (6) × j_est − × × where TH is the heat sink temperature, α is the scaling factor, RVF is the resistance variation factor, and I isElectronics the output 2020, 9, current.x FOR PEER Hence, REVIEW the junction temperature after compensated can be calculated10 of 37 as: where is the heat sink temperature, is the scaling factor, RVF is the resistance variation factor, Tj_est_comp = SF(I) Vce,measured Vce,B(I) + Vce,comp + TB. (7) and I is the output current. Hence, the ×junction temperature− after compensated can be calculated as: 𝑇𝑇𝐻𝐻 𝛼𝛼 Calculate the junction_ temperature_ = ( ) using× , the on-state, collector-emitter( ) + , + . voltage at a low( current.7) • 𝑗𝑗 𝑒𝑒𝑒𝑒𝑒𝑒 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚 𝑐𝑐𝑐𝑐 𝐵𝐵 𝐼𝐼 𝑐𝑐𝑐𝑐 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 𝐵𝐵 Di• ﬀerentCalculate from the the junction calculation𝑇𝑇 temperature of𝑆𝑆𝑆𝑆 the using junction�𝑉𝑉 the on- temperaturestate− 𝑉𝑉 collector𝑉𝑉-emitter using� thevoltage𝑇𝑇 on-state at a low collector-emitter current. voltage atDifferent high current, from the calculation temperature of the coe junctionﬃcient temperature for the low using current the is on negative-state collector [62].- Thisemitter method is preferredvoltage dueat high to itscurrent, simplicity the temperature and adequate coefficient sensitivity for the low which current is aboutis negative2 to [62].2.5 This mV method/ C for few − − ◦ hundredsis preferred of mA senseddue to its current simplicity [63]. and Such adequate a low currentsensitivi doesty which not is produce about −2 any to −2 noticeable.5 mV/°C extrafor few heating at thehundreds device, and of mA it can sensed be applied current continuously[63]. Such a low when current the IGBTdoes not is in produce on-state. any noticeable extra heating at the device, and it can be applied continuously when the IGBT is in on-state. Calculate the junction temperature using the gate internal resistance. • • Calculate the junction temperature using the gate internal resistance. The previous junction temperature using gate internal resistance studies have been The previous junction temperature using gate internal resistance Rg,int studies, have been reported reported in [64,65]. Although these approaches have a good result, they require modifying the in [64,65]. Although these approaches have a good result, they require modifying𝑅𝑅𝑔𝑔 𝑖𝑖𝑖𝑖𝑖𝑖 the substrate layout substrate layout to facilitate the measurement. The proposed method in [66] considers the equivalent to facilitate the measurement. The proposed method in [66] considers the equivalent series resistance series resistance of both gate emitter capacitor and gate collector capacitor as , to form the gate of both gate emitter capacitor and gate collector capacitor as R to form the gate driver RLC without driver RLC without disrupting the converter operation, as showng,int in Figure 8. During the turn-on 𝑅𝑅𝑔𝑔 𝑖𝑖𝑖𝑖𝑖𝑖 disruptingdelay, theboth converter and operation, are constant as shown before inthe Figure gate voltage8. During equals the the turn-on threshold delay, voltage both C. geTheand Cgc are constantgate current before the can gate be utilized voltage as equalsa step response the threshold of the RLC voltage network,Vth. Theand the gate parasitic current gateIg can inductor be utilized 𝐶𝐶𝑔𝑔𝑔𝑔 𝐶𝐶𝑔𝑔𝑔𝑔 𝑉𝑉𝑡𝑡ℎ as a stepshould response satisfy of the> RLC4 / . network,Subsequently, and the the RLC parasitic network gate is overdamped, inductor should and the satisfygate currentR2 > 4L/C. 𝐼𝐼𝑔𝑔 Subsequently,can be approximated. the RLC2 network is overdamped, and the gate current Ig can be approximated. 𝑅𝑅 𝐿𝐿 𝐶𝐶 𝐼𝐼𝑔𝑔

= V t (8) 𝑡𝑡 I = e− RC (8) g 𝑉𝑉 −𝑅𝑅𝑅𝑅 𝐼𝐼𝑔𝑔 R𝑒𝑒 𝑅𝑅 Reset/ Control

Peak ADC detector Differential amplifier + − Memory C capacitor IGBT G Rg,ext E + − Gate driver Equivalent gate driver RLC network

Rg,ext Rg,int Lg Cg + − Gate driver

FigureFigure 8. Conﬁguration 8. Configuration of of junction junction temperaturetemperature estimation estimation using using internal internal resistance. resistance.

Using a peak detector circuit, as shown in Figure 8, it can monitor the peak gate current by measuring the peak value of the voltage across the external gate resistor. Hence, the internal gate resistance can be calculated as:

, , , = , . (9) 𝑉𝑉𝑔𝑔 𝑝𝑝𝑝𝑝𝑝𝑝 − 𝑉𝑉𝑔𝑔 𝑛𝑛𝑒𝑒𝑒𝑒, 𝑅𝑅𝑔𝑔 𝑖𝑖𝑖𝑖𝑖𝑖 − 𝑅𝑅𝑔𝑔 𝑒𝑒𝑒𝑒𝑒𝑒 𝑉𝑉𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝⁄𝑅𝑅𝑔𝑔 𝑒𝑒𝑒𝑒𝑒𝑒

Electronics 2020, 9, 2068 11 of 37

Using a peak detector circuit, as shown in Figure8, it can monitor the peak gate current by measuring the peak value of the voltage across the external gate resistor. Hence, the internal gate resistance can be calculated as:

Vg,pos Vg,neg = − Electronics 2020, 9, x FOR PEER REVIEW Rg,int Rg,ext.11 of (9)37 Vpeakdetector/Rg,ext −

Subsequently, basedbased on on the the calibration, calibration, the the junction junction temperature temperature can can be estimated.be estimated. The The result result in [66 in] [66]showed showed a strong a strong linear linear relationship relationship between between the resistance the resistance and the estimated and the estimated temperature. temperature. However, However,due to the due assumption to the assumption during measurement during measurement and calibration, and calibration, there might there be measurement might be measurement errors. errors. Calculate the junction temperature using short-circuit current. • Calculate the junction temperature using short-circuit current. InIn [67], [67], the the authors authors proposed proposed a a method method using using short short-circuit-circuit cur current-basedrent-based estimation to calculate thethe junction temperature in in using an additional bypass switch as shown in Figure9 9.. TheThe relationrelation between the short short-circuit-circuit current and the temperature is a negative coecoefficientfficient [[6868–70]. The bypass IGBTIGBT is is connected connected in in par parallelallel with with the the complementary complementary IGBT IGBT and andis active is active only when only whenthe switch the switchunder testunder is test in the is in off the state off state to create to create short short-circuit-circuit conditions. conditions. The The short short circuit circuit current current amplitude amplitude is approximatelyis approximately linear, linear, with with the thejunction junction temperature temperature with with an adequate an adequate temperature temperature sensitivity sensitivity of 0.3 of5 A0.35/°C. A Although/◦C. Although the duration the duration of short of short-circuit-circuit time time is short, is short, the the repetitive repetitive short short circuit circuit could could have have a cumulative degradation degradation effect effect on on the device, which should be taken into consideration if if the short circuit current is adopted for onlineonline temperature measurement.

Switch under test

Bypass switch

Figure 9. ConfigurationConﬁguration of of junction junction temperature temperature estimation estimation using using short short-circuit-circuit with an additional bypass switch.

Calculate the junction temperature using the threshold voltage. • Calculate the junction temperature using the threshold voltage. As stated stated before, before, the the threshold threshold voltage voltage is the is the gate gate emitter emitter voltage voltage when when the device the device begins begins to turn to- on.turn-on. In [71,72], In [71 a, 72SEMIKRON], a SEMIKRON SKM-75GB12T4 SKM-75GB12T4 IGBT was IGBT utilized was utilized as an experimental as an experimental IGBT to IGBT obtain to theobtain junction the junction temperature temperature estimation estimation model model based based on 푉 on푔푒 Vandge and 푡푑표푛tdon. . By By conducting conducting an an offline oﬄine calibration experiment under under different diﬀerent temperatures and bus voltages, the negative relation between

푉V푔푒ge andand temperature temperature and and the positive the positive relation relation between betweenVge and bus푉푔푒 voltage and bus are deduced. voltage are Consequently, deduced. Consequently,a model, which a presents model, the which exact pr correlationesents the between exact correlationtdon, Tj, and betweenVge can 푡 be푑표푛 described, 푇푗 , and as푉푔푒 follows: can be described as follows: Tj = 1.24Vge + 132.84tdon 23969.7. (10) 푇푗 = 1.24푉푔푒 + 132.84푡푑표푛 − 23969.7. (10) The obtained model model can can help help measure measure the the junction junction temperature temperature without without interrupting interrupting the the regular regular operation of of IGBT. IGBT. Besides, Besides, this this model model rejects rejects the eﬀ ect the of effect the bus of voltage the bus and voltage only requires and only measurement requires of the voltage signal, Vge. Hence, the measurement circuit is easy to implement, and it is not hard to measurement of the voltage signal, 푉푔푒. Hence, the measurement circuit is easy to implement, and it conﬁrm accuracy. is not hard to confirm accuracy.  Calculate the the junction junction temperature temperature using using Miller Miller p plateaulateau voltage voltage.. • Following [73], the Miller plateau voltage can be calculated according to (11) using the threshold voltage 푉푡ℎ and transconductance gain 퐾푛 , both of which can be influenced by the junction temperature:

퐼푐푒 푉푔푝 = √ + 푉푡ℎ. (11) 퐾푛

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Following [73], the Miller plateau voltage can be calculated according to (11) using the threshold voltage Vth and transconductance gain Kn, both of which can be inﬂuenced by the junction temperature: r Ice Vgp = + Vth. (11) Kn

However, the junction temperature cannot be directly estimated based on the Miller plateau voltage calculated in (11). Due to the internal gate resistance, which is placed inside the power semiconductor, the gate voltage is unreachable. In order to overcome this problem, the measurable Miller plateau voltage can be utilized to estimate the junction temperature. The measurable Miller plateau voltage can be presented as a function of the Miller plateau voltage, the gate driver voltage, and the internal and external gate resistance:

Vm,gp = Vgp + ∆V, (12)

Rg,int ∆V = Vd Vgp . (13) − × Rg,int + Rg,ext Consequently, the junction temperature can be estimated by using a lookup table based on the measurable Miller plateau voltage and the device current Ice.

Calculate the junction temperature using turn on/off delay time. • As stated in [71], the dynamic TSEPs can be influenced by the bus voltage or load current. The turn-on delay time is calculated as the time between the rising edge of the gate-emitter voltage and the rising edge of the collector current, or the time within the gate voltage reaching the threshold voltage [74]. The turn-on delay time was defined which is suitable to be utilized as TSEP. The results showed that the turn-on delay time has excellent linearity with the temperature. However, due to the influence of the bus voltage, the measurement can only be conducted when the bus voltage is kept constant. In order to overcome this problem, the author in [75] proposed a method, which utilized both turn-on delay time and the maximum increasing rate of collector current to calculate the junction temperature, eliminated the effect of the bus voltage. The relations between the junction temperature and the turn-on delay time can be described as:

1 T = [(a t a VeE max) + (a b + a b )], (14) j a a a a × 22 × don − 12 × _ 22 × 1 12 × 2 | 11 22 − 12 21| where a and b are the constant coefficients after the calibration process and VeE_max is the maximum voltage that crosses the parasitic inductor LeE. In addition to the turn-on delay time, the turn-off delay time, which is defined from the time point when the gate-emitter voltage falls to 90% maximum value to the time point when the collector-emitter voltage rises to 90% off-state value. In [76], a simple measurement circuit including current/voltage collecting part, voltage reference part, voltage divider, signal processing part, isolation circuit, and DSP controller, was proposed to estimate the junction temperature based on the turn-off delay time as shown in Figure 10. Following the definition, the turn-off delay time can be calculated following as:

tdo f f = ∆t1 + ∆t2, (15) ! 0.9Vge(on) Vge(o f f ) ∆t1 = RG Cge + Cgc ln − , (16) Vgp V − ge(o f f ) 0.9Vdc Vce(on) ∆t2 = RGCgc − . (17) Vgp V − ge(o f f ) Electronics 2020, 9, x FOR PEER REVIEW 12 of 37

푉푚,푔푝 = 푉푔푝 + ∆푉, (12)

푅푔,푖푛푡 ∆푉 = (푉푑 − 푉푔푝) × . (13) 푅푔,푖푛푡 + 푅푔,푒푥푡 Consequently, the junction temperature can be estimated by using a lookup table based on the measurable Miller plateau voltage and the device current 퐼푐푒.  Calculate the junction temperature using turn on/off delay time. As stated in [71], the dynamic TSEPs can be influenced by the bus voltage or load current. The turn-on delay time is calculated as the time between the rising edge of the gate-emitter voltage and the rising edge of the collector current, or the time within the gate voltage reaching the threshold voltage [74]. The turn-on delay time was defined which is suitable to be utilized as TSEP. The results showed that the turn-on delay time has excellent linearity with the temperature. However, due to the influence of the bus voltage, the measurement can only be conducted when the bus voltage is kept constant. In order to overcome this problem, the author in [75] proposed a method, which utilized both turn-on delay time and the maximum increasing rate of collector current to calculate the junction temperature, eliminated the effect of the bus voltage. The relations between the junction temperature and the turn-on delay time can be described as: 1 푇푗 = × [(푎22 × 푡푑표푛 − 푎12 × 푉푒퐸_푚푎푥) + (푎22 × 푏1 + 푎12 × 푏2)], (14) |푎11푎22 − 푎12푎21| where a and b are the constant coefficients after the calibration process and 푉푒퐸_푚푎푥 is the maximum voltage that crosses the parasitic inductor 퐿푒퐸. In addition to the turn-on delay time, the turn-off delay time, which is defined from the time point when the gate-emitter voltage falls to 90% maximum value to the time point when the collector- emitterElectronics voltage2020, 9, 2068 rises to 90% off-state value. In [76], a simple measurement circuit including13 of 37 current/voltage collecting part, voltage reference part, voltage divider, signal processing part, isolation circuit, and DSP controller, was proposed to estimate the junction temperature based on the It can be observed that the turn-off delay time increases with increased Vdc as the turn-on delay time. turn-off delay time as shown in Figure 10.

IL / Vdc Current/ Voltage IL1 / Vdc1 collecting circuit

Vge Vref1 Voltage divider + DSP IGBT Vce Vge1 Isolation circuit Vref2 Voltage + reference circuit Vce1 Signal processing circuit

Figure 10. Figure 10. DiagramDiagram of of junction junction temperature temperature estimation estimation using using a a turn turn-o-offﬀ delay time circuit. According to the discussions above, it can be noticed that resolving junction temperature from Following the definition, the turn-off delay time can be calculated following as: the measurement of TSEPs can be challenging due to many reasons as the low sensitivity of junction temperature, dependence on loading conditions,푡푑표푓푓 = ∆ and푡1 + measurement∆푡2, inaccuracies. The ideal TSEPs(15) can be applicable to any device type, any converter topology, suitable for any application. However, for the case of online TSEPs measurements, the proposed solutions may only be adaptable to particular converter topologies. Therefore, some TSEPs have advantageous qualities, but due to implementation issues, they may only be able to be sampled periodically without causing unacceptable disruption to normal converter operation.

Monitoring thermal resistance. •

The increase of the internal thermal resistance ∆Rth by 20% of the nominal value in [35,77] can be adopted to indicate the solder fatigue. The thermal resistance increase usually is approximately equal to:

∆TC ∆Rth , (18) Ptot

where ∆TC is the temperature change due to the increase in power loss. The detailed principle of the method in [78] is shown in Figure 11. The power loss was ﬁrst estimated from a thermal model that utilized temperature measurements as inputs. A lookup table that provided the information of power loss in healthy IGBT modules was subsequently incorporated, which enabled the estimation of solder layer damage under various operating conditions. It should be noted that due to the correlation between junction temperature, case temperature, and power loss, the measurement should be employed correctly. The implementation of the method requires consistent measurements and online calculation, which can be carried out by the controller digital signal processor, and an iterative calculation is recommended to provide a running update of the changes in thermal resistance. Electronics 2020, 9, 2068 14 of 37

Electronics 2020, 9, x FOR PEER REVIEW 14 of 37

7th-order heat-sink thermal model

Ptot Rth1 Rth2 Rth,n Measured case Measured ambient temperature Tc temperature Ta Cth1 Cth2 Cth,n

Estimated power loss

Ptot

Tc Virtual case temperature calculation Tc’=Tc + Ptot +∆Rth

Virtual power loss calculation following look up power loss curve ∆Rth Ptot’=f(Tc’)

No Ptot|< threshold ـ’Ptot|

Yes ∆Rth

End

Figure 11. DiagramDiagram of of the CM thermal resistance resistance..

2.2.5. Other Other M Monitoringonitoring T Techniquesechniques Embedded sensor-based CM techniques. • Embedded sensor-based CM techniques. The first first embedded sensor sensor-based-based CM technique was first first developed in 2003 to detect bond wire liftlift-o-offff in an an operating operating power power module module [79]. [79]. Redundant Redundant bond bond wires wires are are attached attached to the to theemit emitterter of the of die.the die.Bond Bond wire wirefailure failure was detected was detected when whenthe resistance the resistance between between the emitter the emitter terminal terminal and the and sensor the terminalsensor terminal deviated deviated from a nominal from a nominal value. Although value. Although it provided it provided accurate accurate detection detection of bond of wire bond failure wire regardlessfailure regardless of the ofoperation, the operation, the technique the technique required required a modification a modification of ofthe the original original design design of of IGBT IGBT modules and implementation of the monitoring circuit in a gate driver. Recently, aa workwork proposed proposed a techniquea technique for for using using the the already already integrated integrated current current sensors sensors in the in IGBT the IGBTpower power module module for monitoring for monitoring of the bondof the wire bond lift-o wireff failurelift-off [failure80]. That [80]. integrated That integrated current sensorscurrent sensorsare giant are magnetoresistive giant magnetoresistive (GMR) detectors, (GMR) detectors, which are which utilized are for utilized current andfor current ambient and temperature ambient temperaturesensing [81,82 sensing]. The basic [81,82]. idea The is thatbasic these idea detectors is that these are detectors placed near are the placed bond near wires, the and bond the wires, change and in the change magnetic in fieldthe magnetic caused by field any caused lifted bondby any wires lifted will bond be wires sensed. will In be [80 sensed.], two GMRs In [80], are two required GMRs areto sense required the current,to sense wherethe current, GMR 1wheresenses GMR the low-frequency1 senses the low current,-frequency and current, GMR2 extends and GMR the2 extends current thesensing current bandwidth. sensing bandwidth. In the case ofIn bond the case wire of lift-o bondff exists,wire lift the-off flux exists, density the sensedflux density by one sensed GMR by will one be GMRless because will be theless lifted because bond the wires lifted no bond longer wires carry no current. longer Thecarry remaining current. The GMR remaining will have GMR a slightly will havehigher a fluxslightly density higher because flux density the current because is forced the current to flow is through forced to the flow remaining through bond the wires.remaining Although bond wires.the utilization Although of the GMR utiliz doesation not of require GMR modificationdoes not require of the modification IGBT module, of the the IGBT proposed module, method the proposedrequires accurately method requires extracting accurately the lift-o ffextractingmonitoring the signals. lift-off monitoring The proposed signals. method The in proposed [83] also doesmethod not inrequire [83] also any does modification not require to the any DCB modification layer compared to the withDCB thelayer technique compare ind [wit79].h Besides,the technique this approach in [79]. Besides,can identify this theapproach number can of identify lifted bond the number wires and of lifted locate bond these wires lifted and wires. locate The these Kelvin lifted connection wires. The is Kelvinrealized connection by introducing is realized additional by introducing terminals. additional The emitter terminals. side of The the emitter IGBT chip side is of connected the IGBT withchip isthe connected added Kelvin with pins. the added When bondKelvin wire pins. lift-o Whenff occurs bond at wire a specific lift-off chip, occurs the correspondingat a specific chip, on-state the correspondingvoltage VcKe will on decrease,-state voltage whereas the will remaining decrease,V whereascKe increases. the remaining increases.

• Converter output-based techniques𝑉𝑉𝑐𝑐𝑐𝑐𝑐𝑐 . 𝑉𝑉𝑐𝑐𝑐𝑐𝑐𝑐

Electronics 2020, 9, 2068 15 of 37

ElectronicsConverter 2020, 9, output-basedx FOR PEER REVIEW techniques. 15 of 37 • TheThe converter output output-based-based CM CM technique technique identifies identifies variations variations in the in voltage the voltage and current and current output outputof power of converters. power converters. Although Although this approach this approachdoes not need does any not additional need any sensors additional and sensorsmodification and modificationin switching indevices, switching the devices,converter the output converter-based output-based CM technique CM has technique to operate has at to a operate specific at condition, a specific condition,which makes which it makesis hard it to is hardidentify to identify the harmonic the harmonic amplitude amplitude in real in-time real-time operation. operation. Besides, Besides, the theidentification identification of ofspecific specific aged aged devices devices requires requires additional additional tools. tools. Therefore, Therefore, the the utilizationutilization ofof thethe converterconverter output-baseoutput-base techniquetechnique forfor CMCM isis limited.limited. AA well-knownwell-known studystudy waswas reportedreported byby XiangXiang measuringmeasuring the the fifth fifth harmonic harmonic of theof the output output current current to monitor to monitor the solder the solder fatigue fatigue [84]. The [84]. small The change small ofchange fifth harmonic of fifth harmonic current with current respect with to respect a specific to a case specific temperature case temperature for a given for load a given level isload measured level is bymeasured the converter by the controller.converter controlle Further studyr. Further is required study is to required improve to the improve converter the output-basedconverter output CM- techniquebased CM to technique increase theto increase number ofthe aging number indicators of aging from indicators converter from output, converter conducting output, the conduct approaching inthe real-time approach operation, in real-time and operation, widely applicable and widely to various applicable converter to various types. converter types.

2.3.2.3. CMCM forfor SiCSiC MOSFETMOSFET ModuleModule 2.3.1. Monitoring Gate Leakage Current 2.3.1. Monitoring Gate Leakage Current The previous studies defined the gate leakage current i as an indicator of gate oxide The previous studies defined the gate leakage current lk as an indicator of gate oxide degradation [85]. The gate leakage current measurement does not utilize any signal from high-current degradation [85]. The gate leakage current measurement does not utilize any signal from high-current or high-voltage parts of the power stage for monitoring the device.𝑖𝑖𝑙𝑙 Besides,𝑙𝑙 it has very distinct values or high-voltage parts of the power stage for monitoring the device. Besides, it has very distinct values for a healthy and aged state. In [86], the author proposed a method for the online aging detection for a healthy and aged state. In [86], the author proposed a method for the online aging detection method using the gate leakage current. The block diagram of the proposed method in [86] is illustrated method using the gate leakage current. The block diagram of the proposed method in [86] is in Figure 12. The gate leakage current is measured by using the gate resistance. A difference amplifier illustrated in Figure 12. The gate leakage current is measured by using the gate resistance. A senses the voltage drop on the gate turn-on resistance, then compares the sensed amplified differential difference amplifier senses the voltage drop on the gate turn-on resistance, then compares the sensed voltage to a limit voltage. The limit voltage is utilized as a threshold to indicate the aging effect. amplified differential voltage to a limit voltage. The limit voltage is utilized as a threshold to indicate From the aging test, it can be realized that there is no leakage current in healthy devices or before the aging effect. From the aging test, it can be realized that there is no leakage current in healthy the aging effect becomes remarkable. Since there is no current, the comparator logic output will be 0, devices or before the aging effect becomes remarkable. Since there is no current, the comparator logic indicating that the switch is healthy. On the other hand, the gate current will be leaked in the range output will be 0, indicating that the switch is healthy. On the other hand, the gate current will be of a few mA from the aged switch. Subsequently, the logic output from the comparator will be one leaked in the range of a few mA from the aged switch. Subsequently, the logic output from the if the sensed voltage drop exceeds the limit value. This result warns that gate oxide degradation comparator will be one if the sensed voltage drop exceeds the limit value. This result warns that gate failure might occur in the near future. It is noted that due to the relatively small value of the gate oxide degradation failure might occur in the near future. It is noted that due to the relatively small leakage current and the high switching frequency of switch, some requirements for the amplifier, value of the gate leakage current and the high switching frequency of switch, some requirements for limit voltage is required [86]. Additionally, this method can be integrated into a gate driver chip as an the amplifier, limit voltage is required [86]. Additionally, this method can be integrated into a gate extra protection layer or implemented separately on the power stage to prevent unexpected shutdown driver chip as an extra protection layer or implemented separately on the power stage to prevent depending on the demand. unexpected shutdown depending on the demand.

SiC MOSFET Rg,off

Gate driver Rg,on

PWM signals

Differential − Isolation + amplifier Controller stage

+ Voltage − Comparator divider

Figure 12. Configuration of the gate leakage current measurement circuit. Figure 12. Conﬁguration of the gate leakage current measurement circuit.

2.3.2.2.3.2. MonitoringMonitoring on-Stateon-State ResistanceResistance TheThe on-stateon-state resistance can can be be utilized utilized as as the the indicator indicator for forboth both gate gate oxide oxide degradation degradation and bond and bondwire failures wire failures [32,87]. [32 In,87 [88],]. In the [88 drain], the- drain-sourcesource on-state on-state resistance resistance , R isds ,calculatedon is calculated by utilizing by utilizing high- frequency network reflectometry. A block diagram of the spread spectrum time domain 𝑅𝑅𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 reflectometry (SSTDR) mechanism [88] is shown in Figure 13, the fundamental of SSTRD is explained in [89]. Since the SSTDR hardware is able to detect any impedance mismatch on its path propagation, it can detect the drain-source on-state resistance due to degradation. By applying high-frequency gate

Electronics 2020, 9, 2068 16 of 37 high-frequency network reflectometry. A block diagram of the spread spectrum time domain reflectometry (SSTDR) mechanism [88] is shown in Figure 13, the fundamental of SSTRD is explained in [89]. Since the SSTDR hardware is able to detect any impedance mismatch on its path propagation, Electronics 2020, 9, x FOR PEER REVIEW 16 of 37 Electronicsit can detect 2020, the9, x FOR drain-source PEER REVIEW on-state resistance due to degradation. By applying high-frequency16 of gate 37 signalssignals to to an an entirely entirely conducting conducting SiC SiC MOSFET MOSFET switc switch,h, the the magnitude magnitude of ofthe the bounced bounced back back voltage voltage is signals to an entirely conducting SiC MOSFET switch, the magnitude of the bounced back voltage is utilizedis utilized to measure to measure the thedevice device impedance impedance variation, variation, drain drain-source-source on-state on-state resistance, resistance, in this in case, this over case, utilized to measure the device impedance variation, drain-source on-state resistance, in this case, over aging.over aging. However, However, this method this method is not isspecifically not specifically suited suited to on- toboard on-board implementation. implementation. aging. However, this method is not specifically suited to on-board implementation.

cos(ωt) Shaper PN gen Cable cos(ωt) Shaper PN gen Cable

Variable phase Variable phase Shaper PN gen delay Shaper PN gen ADC delay ∫ ADC

Figure 13. Block diagram of spread spectrum time domain reflectometry mechanism. FigureFigure 13. 13. BlockBlock d diagramiagram of of spread spread spectrum spectrum time time domain domain reflectometry reflectometry mechanism. mechanism. In order to resolve the above problem, the author in [90] proposed a practical on-board SiC InIn order order to to resolve resolve the the above above problem, problem, the the author author in in [90] [90] proposed proposed a a practical practical on on-board-board SiC SiC MOSFET CM technique for aging failures indication, whereas the saturation region on-state MOSFETMOSFET CMCM techniquetechnique for for aging aging failures failures indication, indication, whereas whereas the saturation the saturation region on-state region resistanceon-state resistance is employed to indicate the die-related aging failure and the drain-source on-state resistanceRds,sat is employed , is toemployed indicate to the indicate die-related the die aging-related failure aging and failure the drain-source and the drain on-state-source resistance on-state resistance , is utilized as an indicator for the detection of package-related degradation. First, the Rds,on is utilized𝑑𝑑𝑑𝑑,𝑠𝑠𝑠𝑠𝑠𝑠 as an indicator for the detection of package-related degradation. First, the effectiveness resistance 𝑅𝑅 , is utilized as an indicator for the detection of package-related degradation. First, the effectiveness𝑑𝑑 of𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠 and as indicators for aging failures are discussed and verified through of Rds,sat and𝑅𝑅𝑑𝑑𝑑𝑑R𝑜𝑜𝑜𝑜ds,on as, indicators, for aging failures are discussed and verified through characterization effectiveness𝑅𝑅 of , and , as indicators for aging failures are discussed and verified through characterization𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 of a batch of SiC devices aged under accelerated tests. Then, an in situ measurements of a batch𝑅𝑅 of SiC devices𝑑𝑑𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠 aged𝑑𝑑𝑑𝑑 under𝑜𝑜𝑜𝑜 accelerated tests. Then, an in situ measurements of Rds,sat and characterization 𝑅𝑅of𝑑𝑑 𝑑𝑑a𝑠𝑠𝑠𝑠𝑠𝑠 batch of𝑅𝑅 SiC𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 devices aged under accelerated tests. Then, an in situ measurements of , and 𝑅𝑅 , using 𝑅𝑅readily available system sensors at system startup was proposed, as ofRds ,on using and readily available using systemreadily sensorsavailable at systemsystem startup sensors was at proposed,system st asartup shown was in proposed, Figure 14[ 90as]. shown, in Figure 14, [90]. As for measurement, on a switch of a phase leg, is turned on at a As for𝑑𝑑𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠Rds,sat measurement,𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 on a switch, of a phase leg, is turned on at a reduced gate voltage such shown𝑅𝑅 in Figure𝑅𝑅 14 [90]. As for , measurement, on a switch of a phase leg, is turned on at a reducedthat𝑅𝑅𝑑𝑑 it𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠 operates gate voltage𝑅𝑅 in𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 a saturationsuch that it region, operates whereas in a saturation the other region, switch whereas in the leg the is other turned switch on at in full the gate leg reduced gate voltage such that it 𝑅𝑅operates𝑑𝑑𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠 in a saturation region, whereas the other switch in the leg is turned on at full gate voltage (𝑅𝑅Figure𝑑𝑑𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠 15a). The measured results from the system current sensor isvoltage turned (Figure on at full 15a). gate The voltage measured (Figure results 15a). from The themeasured system results current from sensor the andsystem bus current voltage sensor sensor and bus voltage sensor are utilized to calculate the amplitude of the device operating in andare utilizedbus voltage to calculate sensor theareR utilizedds,sat amplitude to calculate of the the device , operating amplitude in saturation of the device mode. operating Meanwhile, in saturation mode. Meanwhile, the of the switch is calculated, by sensing the across the the Rds,on of the switch is calculated by, sensing the Vds,𝑑𝑑on𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠across the switch under test, and dividing saturation mode. Meanwhile, the , of the switch 𝑅𝑅is calculated by sensing the , across the switchit by the under current test valueand dividing obtained it from by the the current system value current obtained𝑅𝑅𝑑𝑑𝑑𝑑 sensor.𝑠𝑠𝑠𝑠𝑠𝑠 from The the magnitude system current of the V sensor.for R The switch under test and dividing it by𝑅𝑅𝑑𝑑 the𝑑𝑑 𝑜𝑜𝑜𝑜 current value obtained from the system current𝑉𝑉𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 sensor.gs Theds,sat magnitude of the for measurement𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 and measurement are shown in𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜Figure 15a,b. measurement and Rds on measurement, 𝑅𝑅 are shown in Figure, 15a,b. Due to the combination𝑉𝑉 of Rds sat and magnitude of the ,for , measurement and , measurement are shown in Figure , 15a,b. DueRds,on tomeasurement the combination𝑔𝑔𝑔𝑔 during of 𝑑𝑑 startup𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠, and and the, use measurement of available𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 current during and startup voltage and sensors the use in of the available system, Due to the combination𝑉𝑉 of𝑅𝑅 , and , measurement𝑅𝑅 during startup and the use of available currentthis method and voltage just requires𝑉𝑉𝑔𝑔𝑔𝑔 sensors a𝑅𝑅 simple𝑑𝑑 𝑑𝑑in𝑠𝑠𝑠𝑠𝑠𝑠 the voltage system, measurement this method𝑅𝑅𝑑𝑑𝑑𝑑 circuit𝑜𝑜𝑜𝑜just requires and reduces a simple the costvoltage of implementation. measurement current and voltage sensors𝑅𝑅 in𝑑𝑑𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠the system,𝑅𝑅𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜this method just requires a simple voltage measurement circuit and reduces the cost 𝑅𝑅of𝑑𝑑 𝑑𝑑implementation.𝑠𝑠𝑠𝑠𝑠𝑠 𝑅𝑅𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 circuit and reduces the cost of implementation.

Voltage Gate Vgs1 regulatorVoltage driverGate Vgs1 regulator driver

Amplifier Radj Amplifier

V − Radj ds

Vds −

Vf + Drain Vf + Drain Vf − Vds,on

Vf − Vds,on Voltage Gate Vgs2 + regulatorVoltage driverGate Vgs2 + regulator driver Differential + Differential

−+ Vk amplifier + Vk amplifier

Id Source − I + Source Radj d −

Rshunt

Radj − Rshunt 50R a R Monitored switch 50Ra a Monitored switch Ra

FigureFigure 14. 14. ConConﬁgurationfiguration of of the the V sensingsensing circuit. circuit. Figure 14. Configuration of the ds sensing circuit.

𝑉𝑉𝑑𝑑𝑑𝑑 𝑉𝑉𝑑𝑑𝑑𝑑

Electronics 2020, 9, 2068 17 of 37

Electronics 2020, 9, x FOR PEER REVIEW 17 of 37

Vgs1 Vgs1

Vgs2 Vgs2

(a) (b)

Figure 15. Adjustable gate driver voltage for: (a) , measurement, (b) , measurement. Figure 15. Adjustable gate driver voltage for: (a) Rds,sat measurement, (b) Rds,on measurement. 𝑅𝑅𝑑𝑑𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠 𝑅𝑅𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜 InIn [91], [91], a a drain-sourcedrain-source on-state on-state resistance resistance is determinedis determined by usingby using an integrated an integrated module. module. The voltage The voltagebetween between the drain the and drain source andV sourceds and the drainand the current drainId currentof the switch of underthe switch test areunder measured test are to measureddetermine to the determine drain-source the on-state drain-source resistance on-stateR . Inresistance order to overcome. In theorder requirement to overcome of certain the 𝑉𝑉𝑑𝑑𝑑𝑑 ds 𝐼𝐼𝑑𝑑 requirementminimum on-state of certain times minimum during on drain-source-state times during on-state drain voltage-source monitoring, on-state voltage the authors monitoring, utilized the a 𝑅𝑅𝑑𝑑𝑠𝑠 authorsdiscontinuous utilized modulationa discontinuous during modulation a fundamental during a period fundamental of the modulationperiod of the signal modulation to implement signal tofor implement monitoring. for Themonitoring. utilization The of utiliz discontinuousation of discontinuous modulation modulation allows measuring allows themeasuring drain-source the drainon-state-source resistance on-state during resistance normal during operation normal of theoperation converter of withoutthe converter interruption without for interruption the CM process. for theFurthermore, CM process. the Furthermore, yielded Rds result the isyielded stable, and measurementresult is stable, accuracy and measurement is not compromised. accuracy However, is not compromised.the general output However, performance the general of the output converter performance might be a ffofected the converter due to the might discontinuous be affected modulation. due to 𝑅𝑅𝑑𝑑𝑑𝑑 theTherefore, discontinuous the trade-o modulation.ff should beTherefore, considered the carefully trade-off before should implementation. be considered carefully before implementation. 2.3.3. Monitoring Reverse Body Diode 2.3.3. Monitoring Reverse Body Diode In addition to common aging failure indicators as on-state resistance, threshold voltage, and leakage current,In addition the study to incommon [92] proposed aging afailure complete indicators CM method as on for-state SiC resistance, MOSFETs bythreshold using the voltage, reverse and body leakagediode voltage current, drop the atstudy different in [92] gate proposed bias levels. a complete The proposed CM method approach for can SiC indicate MOSFETs both by the using gate oxide the reverseand packaging body diode degradations voltage drop by monitoring at different a singlegate bias indicator. levels. InThe this proposed study, the app secondaryroach can conduction indicate bothmode the in gate the oxide third and quadrant packaging operation degradations is utilized by tomonitoring monitor the a single package-related indicator. In degradation this study, the and secondarygate oxide conduction degradation. mode When in athe gate third bias quadrant is between operation 0 to 4 V,is theutilized current to flowsmonitor through the package the MOS- − relatedchannel, degradation whereas at and a negative gate oxide voltage degradati of 5 V,on. the When current a gate path bias is through is between the PiN0 to diode,−4 V, the which current does − flowsnot include through the the channel MOS channel, as shown whereas in Figure at a16 negative[ 92]. By voltage combining of − this5 V, analysisthe current and path the resultsis through from thethe PiN accelerating diode, which aging does test, not it can include be concluded the channel that as the shown body diodein Figure voltage 16 [92]. drop By can combining detect the this gate analysioxides degradation and the results when from the gatethe accelerating bias voltage aging is 0 V, test, whereas it can the be package-relatedconcluded that the degradation body diode can voltagebe detected drop bycan monitoring detect the gate the body oxide diode degradation voltage when drop atthe 5gate V gate bias bias voltage voltage. is 0 FigureV, whereas 17 shows the − packagethe circuit-related diagram degradation of the gate can be driver detected circuit by boardmonitoring with athe complete body diode CM voltage technique drop for at gate−5 V oxidegate biasdegradation voltage. Figure monitoring 17 shows and the package-related circuit diagram degradation of the gate driver monitoring circuit [board92]. The with switches a completeS1–S CM4 are techniqueutilized to for toggle gate theoxide operation degradation mode monitoring of SiC MOSFET and package and the-related gate bias degradation voltage value monitoring to capture [92]. the Thebody switches diode voltage S –S drop.are utilized Consequently, to toggle gate the oxide operation degradation mode of and SiC package-related MOSFET and degradation the gate bias are voltagemonitored value independently. to1 capture4 the Although body diode the voltage proposed drop. method Consequently, can utilize gate a single oxide indicator degradation to monitor and packagetwo types-related of degradation, degradation further are studymonitored is required independently. to conduct theAlthough approach the during proposed converter method operation. can utAdditionally,ilize a single theindicator complex to drivemonitor control two circuittypes of is adegradation, drawback of further this proposed study is approach. required to conduct the approachAccording during to the converter discussion operation. above, the newAdditionally, findings of the CM complex regarding drive online control techniques circuit for is both a drawbackIGBT and of SiC this MOSFET proposed are approach. presented. The CM techniques are classified following the type of indicators for each type of power semiconductor devices. The benefits and drawbacks of each approach are also given.

Electronics 2020, 9, 2068 18 of 37

ElectronicsElectronics 20 202020, ,9 9, ,x x FOR FOR PEER PEER REVIEW REVIEW 1818 of of 37 37

GateGate SourceSource OxideOxide ((InsulatingInsulating thethe gategate))

++ ++ pp++ nn nn pp++

pp pp

+ + +

IIee + VVbdbd’’ VVgdgd’’ IIhh −− −−

DrainDrain

Figure 16. Current direction in third quadrant operation. FigureFigure 16.16. CurrentCurrent directiondirection inin thirdthird quadrantquadrant operation.operation.

SS VoltageVoltage GateGate 11 regulatorregulator driverdriver SS44 MonitoredMonitored SS11 SS33 switchswitch CurrentCurrent source source

Configuration of complete CM technique. FigureFigure 17.17. ConﬁgurationConfiguration ofof completecomplete CMCM technique.technique.

3. ActiveAccordingAccording Thermal toto the the Control discussiondiscussion above,above, thethe newnew findingsfindings ofof CMCM regardingregarding onlineonline techniquestechniques forfor bothboth IGBTIGBT andand SiCSiC MOSFETMOSFET areare presented.presented. TheThe CMCM techniquestechniques areare classifiedclassified ffollowingollowing thethe typetype ofof As depicted in Figure2, the degradation indicator information obtained from online CM techniques indicatorsindicators forfor eacheach typetype ofof powerpower semiconductorsemiconductor devices.devices. TheThe benefitsbenefits andand drawbacksdrawbacks ofof eacheach can be applied to not only passively update but also actively control the system lifetime. Therefore, approachapproach areare alsoalso given.given. ATC, which is a new idea lately introduced to adjust power losses and thermal stress, is discussed here. The common principle is to vary temperature-related control variables of the power converter to 3.3. ActiveActive ThermalThermal ControlControl vary the junction temperature, which will reduce damage caused by thermal cycling [16,93]. By using ATC,AsAs the depicteddepicted reliability inin of FigureFigure power devices2,2, thethe degradationdegradation is improved, indicatorindicator and the lifetime informationinformation of the obtainedobtained power system fromfrom isonlineonline extended. CMCM Basically,techntechniquesiques the cancan control bebe appliedapplied of junction toto notnot temperature, onlyonly passivelypassively temperature updateupdate butbut variation, alsoalso activelyactively peak controlcontrol temperature, thethe systemsystem and lifetime. averagelifetime. junctionTherefore,Therefore, temperature ATC,ATC, whichwhich has isis beenaa newnew targeted. ideaidea latelylately From introducedintroduced the perspective toto adjustadjust of powerpower converter losseslosses type, andand this thermalthermal paper stress,stress, divides isis thediscusseddiscussed ATC into here.here. three TheThe main commoncommon categories: principleprinciple single-converters, isis toto varyvary temperaturetemperature cascaded--relatedrelated converters, controlcontrol and variablesvariables parallel ofof converters thethe powerpower systems.converterconverter The toto vary classiﬁcationvary thethe junctionjunction can be temperature,temperature, described as whichwhich follows: willwill reducereduce damagedamage causedcaused byby thermalthermal cyclingcycling [[16,16,93].93]. ByBy usingusing ATC,ATC, thethe reliabilityreliability ofof powerpower devicesdevices isis improved,improved, andand thethe lifetimelifetime ofof thethe powerpower (1)systemsystem The isis single extended.extended. converter BaBasically,sically, systems thethe include controlcontrol the ofof two-level, junctionjunction three-level temperature,temperature, converters temperaturetemperature in ship power,variation,variation, machine peakpeak temperature,temperature,drive applications, andand averageaverage and junctionjunction buck/boost temperaturetemperature converters hashas in beenbeen the targeted. photovoltaictargeted. FromFrom application. thethe perspectiveperspective ofof converterconverter (2)type,type, The thisthis cascaded paperpaper dividesdivides converter thethe ATCATC systems intointo include threethree mainmain the cascaded categories:categories: H-bridge singlesingle--converters,converters, (CHB) converters cascascadedcaded and converters,converters, MMC. (3)andand parallelparallelThe parallel convertersconverters converter systems.systems. systems TheThe include classificationclassification the systems cancan bebe that describeddescribed utilize as parallelas follows:follows: structure based on two-, three-level converters, buck/boost converters in wind power, and machine drive applications. (1)(1) TheThe singlesingle converterconverter systemssystems includeinclude thethe twotwo--level,level, threethree--levellevel convertersconverters inin shipship power,power, 3.1. Singlemachinemachine Converter drivedrive applications, Systemapplications, andand buck/boostbuck/boost convertersconverters inin thethe photovoltaicphotovoltaic application.application. (2)(2) TheThe cascadedcascaded converterconverter systemssystems includeinclude thethe cascadedcascaded HH--bridgebridge (CHB)(CHB) convertersconverters andand MMC.MMC. A straightforward method to realize thermal control is to regulate the switching frequency, (3)(3) TheThe parallelparallel converterconverter systemssystems includeinclude thethe systemssystems thatthat utilizeutilize parallelparallel structurestructure basedbased onon twotwo--,, which has a direct impact on the power losses without considerably aﬀecting the working condition threethree--levellevel converters,converters, buck/boostbuck/boost convertersconverters inin windwind power,power, andand machinemachine drivedrive applications.applications.

3.1.3.1. SingleSingle CConverteronverter SSystemystem

Electronics 2020, 9, 2068 19 of 37 of theElectronics power 20 system20, 9, x FOR [93 PEER,94]. REVIEW In [95 ], a switching frequency reduction method based on the19 junctionof 37 Electronics 2020, 9, x FOR PEER REVIEW 19 of 37 temperature variation for a two-level inverter in an adjustable speed drive application was proposed. A straightforward method to realize thermal control is to regulate the switching frequency, The operatingwhichA hasstraightforward switchinga direct impact frequency method on the topower is realize determined losses thermal without through control considerably ais hysteretic to regulate affecting control the theswitching as workin follows: gfrequency, condition whichof the haspower a direct system impact [93,94]. on theIn [95], power a switching losses without frequency considerably reduction affecting method the based workin on theg condition junction of the power system [93,94]. In [95], a switchingf min frequency, ∆T > T reduction method based on the junction temperature variation for a two-level inverter sin an adjustable∗j 1 speed drive application was proposed.  temperatureThe operating variation switching for frequencya two-level is inverter determ inedin an through adjustable a hysteretic speed drive control application as follows: was proposed. fs =  fs∗, ∆T∗j < T2 , (19) The operating switching frequency is determined through a hysteretic control as follows:   unchange, T, 1 < >∆T∗j < T2 𝑚𝑚𝑚𝑚𝑚𝑚, ∗ > = 𝑠𝑠 , 𝑗𝑗< 1 , (19) 𝑓𝑓𝑚𝑚𝑚𝑚𝑚𝑚, ∆𝑇𝑇∗< 𝑇𝑇 where T and T are the upper and lower= limits𝑠𝑠 ∗ of, the∗𝑗𝑗 < hysteretic1 < , junction temperature variations,(19) 1 2 𝑠𝑠 𝑓𝑓 𝑠𝑠 ∆𝑇𝑇𝑗𝑗 𝑇𝑇2 𝑓𝑓 � 𝑓𝑓∗ ∆𝑇𝑇∗ 𝑇𝑇 𝑠𝑠 𝑠𝑠 , 𝑗𝑗 < 2 ∗ < respectively, adjusting the switching frequency as a1 function𝑗𝑗 of2 both the average temperature and where T1 and T2 are the upper and𝑓𝑓 lower� 𝑢𝑢𝑢𝑢 𝑢𝑢limitsℎ𝑎𝑎𝑓𝑓𝑎𝑎𝑎𝑎 𝑎𝑎∆of𝑇𝑇𝑇𝑇 the 𝑇𝑇∆hysteretic𝑇𝑇∗ 𝑇𝑇 junction temperature variations, 1 𝑗𝑗 2 the temperaturewhererespectively, T1 and variationadjusting T2 are the the together, upper switching and have lowerfrequency𝑢𝑢 better𝑢𝑢 𝑢𝑢limitsℎ𝑎𝑎𝑎𝑎 as reliability𝑎𝑎 𝑎𝑎 ofa 𝑇𝑇function the ∆hysteretic𝑇𝑇 improvement of both𝑇𝑇 junction the average comparedtemperature temperature with variations, and the the control of a singlerespectively,temperature parameter. adjustingvariation However, thetogether, switching the have combining frequency better reliability as of a controlfunction improvement parametersof both the com average increasespared temperaturewith the the complexitycontrol and ofthe a and calculationtemperaturesingle burdenparameter. variation of theHowever, together, control the system. have combining better reliability of control improvement parameters com increasespared withthe complexitythe control ofand a Asinglecalculation diff erentparameter. burden manner However, of isthe to control modify the system.combining the modulation of control methods parameters and increases utilize modern the complexity control methods.and In [96calculation], aA pulse-width different burden manner of modulation the iscontrol to modify system. (PWM) the modulation strategy formethods redistribution and utilize ofmodern losses control for the methods. three-level A different manner is to modify the modulation methods and utilize modern control methods. neutral-point-clampedIn [96], a pulse-width (3L-NPC) modulation inverter, (PWM) namedstrategy activefor redistribution lifetime extension of losses for (ALE), the three without-level any In [96], a pulse-width modulation (PWM) strategy for redistribution of losses for the three-level additionalneutral hardware-point-clamped for the(3L- modulationNPC) inverter, range named 0.5 active< m lifetime< 1 was extension proposed. (ALE), There without is a any total of neutraladditional-point hardware-clamped for (3L the- NPC)modulation inverter, range named 0.5 < m active < 1 was lifetime proposed extension. There is (ALE), a total ofwithout 27 different any 27 different arrangements of the switches in the 3L-NPC, as shown in Figure 18. The use of different additionalarrangements hardware of the forswitches the modulation in the 3L -rangeNPC, 0.5as shown< m < 1 wasin Figure proposed 18. The. There use is of a differenttotal of 27 switching different switching states allows reducing the switching losses or conduction losses. For example, the region, arrangementsstates allows reducing of the switches the switching in the 3Llosses-NPC, or conductionas shown in losses. Figure For 18 example,. The use theof differentregion, highlighted switching highlightedstatesin blue, allows in presents blue, reducing presents redundant the switching redundant switching losses switching states. or conduction If states.the conduction losses. If the For conduction example,losses have the losses region,to be have reduced, highlighted to be reduced,the the switchinginswitching blue, presents statesstates yieldingyieldingredundant higher higher switching conduction conduction states. losses If losses the are conduction are eliminated eliminated losses from from have the the switchingto switchingbe reduced, sequence. sequence. the Conversely,switchingConversely, if thestates if reduction the yielding reduction of higher switching of switchingconduction losses losses haslosses the has are priority, theeliminated priority, the corresponding fromthe correspondingthe switching states sequence.s aretates forbidden, are as shownConversely,forbidden, in Figure as if shown the19. reduction in Figure of19. switching losses has the priority, the corresponding states are forbidden, as shown in Figure 19. −11−1 01−1 11−1 −11−1 01−1 11−1

−110 010 110 10−1 −110 −10100−1 11000−1 10−1 −10−1 00−1 011 000 100 1−1−1 −111 −011100 111 −0001−1−1 1000−1−1 1−1−1 −111 −100 111 −1−1−1 0−1−1 001 101 1−10 −101 −1−00110 1010−10 1−10 −101 −1−10 0−10 1−11 −1−11 0−11 1−11 −1−11 0−11

Figure 18. Different combinations of switching states in three-level neutral-point-clamped (3L-NPC). FigureFigure 18. Di18.ﬀ Differenterent combinations combinations of of switching switching states in in three three-level-level neutral neutral-point-clamped-point-clamped (3L-NPC (3L-NPC).).

Higher switching losses Higher conduction losses Higher switching losses Higher conduction losses

0 0 1 1 1 0 0 1 1 1 −01 00 10 10 11 −01 00 10 10 11 −−11 −01 −01 00 10 −−11 −01 −01 00 10 −1 −1 −1 0 0 −1 −1 −1 0 0

Redundant states Redundant states Redundant states Redundant states Redundant states Redundant states Redundant states Redundant states

Figure 19. Redundant states and impact on switching losses and conduction losses. Figure 19. Redundant states and impact on switching losses and conduction losses. Figure 19. Redundant states and impact on switching losses and conduction losses. The author in [97,98] utilized the redundant switching states in the inner hexagon (region is highlighted in orange) of the space vector diagram to alter the current paths ﬂowing in the power ElectronicsElectronics2020, 209,20 2068, 9, x FOR PEER REVIEW 20 of 3720 of 37

The author in [97,98] utilized the redundant switching states in the inner hexagon (region is deviceshighlighted and thereby in orange) reducing of the the space conduction vector diagram losses to or alter switching the current losses paths of flowing the device. in the This power control schemedevices is especially and thereby suitable reducing for the the conduction ride-through losses operation,or switching during losses of the the grid device. faults This for control grid-tied scheme is especially suitable for the ride-through operation, during the grid faults for grid-tied converters, or the startup operation of motor drives where the modulation index is low, and the voltage converters, or the startup operation of motor drives where the modulation index is low, and the referencevoltage is locatedreference in is thelocated inner in hexagonthe inner hexagon in Figure in 18 Figure. 18. The controlThe control scheme scheme in Figurein Figure 20 20shows shows a junctiona junction temperature temperature controller using using the the finite ﬁnite control control set modelset predictive model predictive control (FCS-MPC)control (FCS to-MPC) control to contro the amplitudel the amplitude of thermal of thermal cycles incycles a two-level in a two three-phase-level inverter-basedthree-phase machine inverter- drivebased [machine99]. The drive load current,[99]. The junction load current, temperature, junction andtemperature, the resulting and the thermal stressresulting are predicted thermal for stress all space are predicted vectors offor the all nextspace sampling vectors of instant. the next These sampling predictions instant. areThese utilized to derivepredictions the FCS-MPC are utilized cost to derive function the FCS parameters-MPC cost that function include parameters the error that from include the the current error from reference, the thermalthe current stress reference, on the the device, thermal the stress temperature on the device, diﬀ erencethe temperature between difference the chips between on a power the chips module, and theon a total power power module, losses and from the total switching power losses and conduction from switching of the and semiconductors. conduction of the These semiconductors. parameters are These parameters are weighed, and the space vector with the lowest cost function is directly applied weighed, and the space vector with the lowest cost function is directly applied to the power converter. to the power converter.

Current Junction Generate temperature Tj predicted value Stress

Device stress

Power losses Cost function optimization Reference error

Tj spread Apply optimal switching state

Power system

FigureFigure 20. 20.Diagram Diagram of of ATC-based ATC-based ﬁnitefinite control set set model model predictive predictive control control (FCS (FCS-MPC).-MPC).

BasedBased on thison thi concept,s concept, a sequencea sequence of of control control forfor aa current-sourcecurrent-source active active rectifier rectifier was was utilized utilized as as a a control algorithm in [100]. The working principle of the sequence control approach is based on a control algorithm in [100]. The working principle of the sequence control approach is based on a finite finite number of switching states of the power converter. To select the optimal switching state, an numberobjective of switching function statesthat computes of the power the error converter. between To predicted select the values optimal and switchingreference values state, of an both objective functionelectrical that and computes thermal theobjectives. error betweenIt can be seen predicted that, by valuesminimizing and the reference multi-objective values weighted of both electricalcost and thermalfunction,objectives. the electrical It and can thermal be seen objectives that, by minimizingcan be achieved. the multi-objectiveHowever, it should weighted be noted cost that function,the the electricaloutput performance and thermal of the objectives power converter can be achieved.system might However, deteriorate it and should the computational be noted that burden the output performancemight be ofrelatively the power heavy. converter system might deteriorate and the computational burden might be relatively heavy. 3.2. Cascaded Converter System 3.2. CascadedModular/cascaded Converter System power converters have been gradually utilized in medium- and high- voltage/powerModular/cascaded applications. power The converters most popular have topologies been are gradually CHB converters utilized and inMMCs. medium- Due to and containing many cells/SMs in the power converter system, the unequal thermal stress among high-voltage/power applications. The most popular topologies are CHB converters and MMCs. cells/SMs exerts a negative impact on the switching devices and the lifetime of the power converter. Due to containingThe author many in [101] cells proposed/SMs in a the technique, power converternamed power system, routing, the to unequal implement thermal ATC stressthrough among cells/unevenlySMs exerts loading a negative the modules impact of onthe themodular/cascaded switching devices configuration. and the lifetime The power of therouti powerng method converter. is theThe optimization author in [ 101technique] proposed in which a technique, each module named processes power a quantified routing, amount to implement of power ATC with throughthe unevenly loading the modules of the modular/cascaded configuration. The power routing method is the optimization technique in which each module processes a quantified amount of power with the aim of improving the system’s efficiency and reliability [101], as depicted in Figure 21. The module can be connected in series or parallel or a combination of both. As for the series connection, the same Electronics 2020, 9, x FOR PEER REVIEW 21 of 37 Electronics 2020, 9, 2068 21 of 37 aim of improving the system’s efficiency and reliability [101], as depicted in Figure 21. The module can be connected in series or parallel or a combination of both. As for the series connection, the same current is shared among modules, but each module has the degree of freedom to control its output current is shared among modules, but each module has the degree of freedom to control its output voltage. Thus, the power of the individual module can be regulated by varying the module’s output voltage. Thus, the power of the individual module can be regulated by varying the module’s output voltage. Similarly, regarding the parallel configuration, the cells share the same voltage, but each voltage. Similarly, regarding the parallel configuration, the cells share the same voltage, but each module has the degree of freedom to control its output current, the parameter utilized to control cell module has the degree of freedom to control its output current, the parameter utilized to control cell power is the current instead of the voltage. Based on this technique, the power routing method is power is the current instead of the voltage. Based on this technique, the power routing method is applied to CHB converters [102], 3-stage modular smart transformer comprising a CHB for medium applied to CHB converters [102], 3-stage modular smart transformer comprising a CHB for medium voltage AC (MVAC) to medium voltage DC (MVDC) conversion [103], and dual active bridges (DAB) voltage AC (MVAC) to medium voltage DC (MVDC) conversion [103], and dual active bridges (DAB) for MVDC to low voltage DC (LVDC) conversion [104]. Thanks to this method, the most damaged for MVDC to low voltage DC (LVDC) conversion [104]. Thanks to this method, the most damaged cells can be preserved. cells can be preserved.

P Module 1 1

P P total Module 2 2

P Module 3 3

Power routing Ptotal = P1 + P2 + P3 P ≠ P ≠ P 1 2 3 FigureFigure 21. 21. PrinciplePrinciple of of power power routing routing method. method.

RegardingRegarding MMC, MMC, this this type type of of multilevel multilevel converter converter has has received received a a great great deal deal of of study study in in terms terms of of variousvarious aspects aspects as as o outpututput performance performance improvementimprovement [ 105[105–108–108],], reduced reduced computational computational burden burden [109 [109–111–], 111power], power losses losses balancing balancing among among SMs [104 SMs,112 [104,112,113],,113], etc. Due etc. to Due the relatively to the relatively large number large ofnumber SMs, the of ATCSMs, is theusually ATC conductedis usually conducted to achieve similarto achieve thermal similar stress thermal distribution stress amongdistribution the different among SMsthe different to enhance SMs the tolifetime enhance of thethe power lifetime system of the [104 power]. In [114 system], the unbalanced[104]. In [114], thermal the distributionunbalanced among thermal SMs, distribution induced by amongthe mismatch SMs, induced in the SM by parameters, the mismatch was in analyzed. the SM parameters, Due to the SM was capacitors analyzed. are Due not identical,to the SM the capacitors switching arelosses not andidentical, conduction the lossesswitching of associated losses an SMsd conduction will be different, losses resulting of associated in unbalanced SMs thermalwill be distributiondifferent, resultingamong SMs. in unbalanced In order tosolve thermal that problem,distribution an active among thermal SMs. balancingIn order controlto solve was that proposed problem, by an combining active thermalthe junction balancing temperature control of was lower proposed IGBT and by the combining capacitor voltage the junction to the sortingtemperature algorithm of lower by using IGBT a weight and thefunction. capacitor The voltage weight to factor the sorting is altered algorithm between zeroby using and aa predefinedweight function. value to The guarantee weight bothfactor the is capacitoraltered betweenvoltage balancezero and and a equalpredefined thermal value distribution to guarantee among SMs:both the capacitor voltage balance and equal thermal distribution among SMs: i i L = (1 α) v α T sign(iarm), (20) i − × norm − × norm × = (1 ) × × × ( ), (20) where α is the weighting factor, vi and𝑖𝑖 Ti are the𝑖𝑖 deviation in the capacitor voltage and the where is the weighting factor,𝑖𝑖 norm and𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 norm are the𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 deviation 𝑎𝑎𝑎𝑎𝑎𝑎in the capacitor voltage and the junction temperature, respectively.𝐿𝐿 − 𝛼𝛼 The𝑣𝑣 acquired− 𝛼𝛼 experimental𝑇𝑇 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 results𝑖𝑖 under different cases with junction temperature, respectively.𝑖𝑖 The acquired𝑖𝑖 experimental results under different cases with different𝛼𝛼 capacitances in SM capacitors𝑣𝑣𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 validated𝑇𝑇𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 the proposed thermal balancing control methods by different capacitances in SM capacitors validated the proposed thermal balancing control methods equally distributing the temperature among SMs. However, the capacitor voltages are less balanced, by equally distributing the temperature among SMs. However, the capacitor voltages are less which is a trade-off when the thermal balancing control approach is adopted. Another thermal balancing balanced, which is a trade-off when the thermal balancing control approach is adopted. Another strategy was presented in [115], integrated the junction temperature to the capacitor voltage balancing thermal balancing strategy was presented in [115], integrated the junction temperature to the algorithm to achieve similar thermal distribution among SMs. Different from [114], the temperature capacitor voltage balancing algorithm to achieve similar thermal distribution among SMs. Different of devices in SM is integrated separately to associated capacitor voltage, forming four cost functions from [114], the temperature of devices in SM is integrated separately to associated capacitor voltage, corresponding to the upper IGBT, upper diode, lower IGBT, and lower diode. The cost function is forming four cost functions corresponding to the upper IGBT, upper diode, lower IGBT, and lower selected for each sampling instant by taking into account the arm current direction and whether SMs diode. The cost function is selected for each sampling instant by taking into account the arm current have to be inserted or bypassed. The proposed control approach sharply reduced the inhomogeneity direction and whether SMs have to be inserted or bypassed. The proposed control approach sharply and temperature spread among the SMs. reduced the inhomogeneity and temperature spread among the SMs. A method proposed in [116] achieved SM thermal balancing by regulating the capacitor voltage of A method proposed in [116] achieved SM thermal balancing by regulating the capacitor voltage each SM in an arm while keeping the sum of the SM capacitor voltages at nominal value to control the of each SM in an arm while keeping the sum of the SM capacitor voltages at nominal value to control dc-link voltage. As shown in Figure 22, the temperature of each SM TSM,i is compared with the average the dc-link voltage. As shown in Figure 22, the temperature of each SM , is compared with the

𝑇𝑇SM 𝑖𝑖 Electronics 2020, 9, 2068 22 of 37

Electronics 2020, 9, x FOR PEER REVIEW 22 of 37 temperature of all SMs Tavg in the arm, and the diﬀerence fed to a proportional-integral (PI) controller, whichaverageElectronics will determine temperature 2020, 9, x FOR the PEER of voltage all REVIEW SMs di ﬀerential in the arm, to be and added the difference to each individual fed to a proportional SM voltage-integral reference22 of (PI)37 [116]. The capacitorcontroller,Electronics 20 voltages20which, 9, x FOR will arePEER determine regulated REVIEW the following voltage differential [117] but to with be added additional to each terms individual corresponding SM 22voltage of 37 to the 𝑇𝑇avg temperature.referenceaverage temperature Although[116]. The theofcapacitor all temperature SMs voltages in amongthe are arm, regulated SMsand the was differencefollowing balanced, fed[117] a to distorted abut proportional with multilevel additional-integral arm terms (PI) voltage average temperature of all SMs in the arm, and the difference fed to a proportional-integral (PI) waveformcorrespondingcontroller, was which produced to thewill temperature. determine from unbalanced avgthe Although voltage capacitor differentialthe temperature voltages. to be addedamong to SMs each was individual balanced, SM a distortedvoltage controller, which will determine𝑇𝑇 the voltage differential to be added to each individual SM voltage multilevelreference [116].arm voltage The capacitor waveform voltages𝑇𝑇avg was produced are regulated from unbalanced following [117]capacitor but voltages.with additional terms correspondingreference [116]. to The the temperature.capacitor voltages Although are theregulated temperature following among [117] SMs but was with balanced, additional a distorted terms corresponding to the temperature. Although the temperature among SMs was balanced, a distorted multilevel arm voltage waveformSM,i was produced from unbalanced capacitorSM ,voltages.i multilevel arm voltage waveform was produced from unbalanced capacitor voltages.

SM,i SM,i avg SM,i SM,i

FigureFigure 22. 22.The The SMSM avg temperature control control diagram. diagram.

avg In [118], the study revealedFigure that22. The thermal SM temperature stress distribution control diagram. inside the SMs of hybrid MMC In [118], the study revealedFigure that 22. The thermal SM temperature stress distribution control diagram. inside the SMs of hybrid MMC (Figure(Figure 23) 23) becomes becomes more more unbalanced unbalanced under under a high a high voltage voltage modulation modulation index. index.The ATC The for both ATC half forboth bridgeIn SMs [118], (HBSMs) the study and revealedfull-bridge that SMs thermal (FBSMs) stress was distribution proposed to insidesolve thisthe problemSMs of .hybrid As for FBSMs,MMC half-bridge(FigureIn SMs23)[118], becomes (HBSMs) the study more andrevealed unbalanced full-bridge that under thermal SMs a high (FBSMs)stress voltage distribution was modulation proposed inside index. the to The solveSMs ATC of this hybrid for problem. both MMC half- As for the two kinds of bypassed switching modes were altered to form a symmetrical switching FBSMs,bridge(Figure the SMs two23) becomes (HBSMs) kinds ofmore and bypassed full unbalanced-bridge switching SMs under (FBSMs) a high modes was voltage proposed were modulation altered to solve to index. this form problem The a symmetricalATC. As for for both FBSMs, half switching- arrangement when arm voltage is positive [118]; as shown in Figure 24, the same procedure is applied thebridge two SMs kinds (HBSMs) of bypassed and full- bridgeswitching SMs (FBSMs)modes werewas proposed altered to solveform this a symmetricalproblem. As forswitching FBSMs, arrangementwhen arm when voltage arm is voltage negative. is positiveThe symmetrical [118]; as switch showning in arrangement Figure 24, the does same not procedure deteriorate is the applied arrangementthe two kinds when of armbypassed voltage switching is positive modes[118]; as were shown altered in Figure to 24,form the samea symmetrical procedure switchingis applied whenconverter arm voltage output is performance, negative. Thewhereas symmetrical the distribution switching of power arrangement losses in FBSM does is notmore deteriorate balanced, the whenarrangement arm voltage when armis negative. voltage isThe positive symmetrical [118]; as switchshowning in Figure arrangement 24, the same does procedure not deteriorate is applied the converterresulting output in the performance, thermal reduction whereas of the themost distribution stressed devices. of power losses in FBSM is more balanced, converterwhen arm output voltage performance, is negative. whereasThe symmetrical the distribution switch ofing power arrangement losses in doesFBSM not is moredeteriorate balanced, the resulting in the thermal reduction of the most stressed devices. resultingconverter in output the thermal performance, reduction whereas of the mostthe distribution stressed devices. of power losses in FBSM is more balanced, Half-bridge resulting in the thermal reduction of the most stressedHBSM2 devices. Idc Submodule Half-bridge HBSMHBSM2N S1 Idc HalfSubmodule-bridge HBSM2 Idc Submodule HBSMN S1 vu FBSM1 S2 HBSMN S1

v FBSM1 u FBSMM S2 Vdc/2 vu FBSM1 S2 FBSMM Vdc/2 La iu FBSMM Vdc/2 icirc R L La A iu O La iu R iLo icirc A R L icirc A O La io il O Full-bridge io La il Submodule HBSM1 Full-bridge La il Vdc/2 SubmoduleFullS-bridgeS HBSM1 1 3 vl HBSMN Submodule Vdc/2 HBSM1 S1 S3 Vdc/2 vl HBSMN S2 S4 FBSM1 S1 S3 vl HBSMN S2 S4 FBSM1 FBSM S2 S4 FBSM N 1 FBSMN Figure 23. Single-FBSMphaseN hybrid MMC.

Figure 23. Single-phase hybrid MMC. FigureFigure 23. 23. Single-phaseSingle-phase hybrid hybrid MMC. MMC.

S1 S3 S1 S3 S1 S3 S1 S3

S1 S3 S1 S3 S1 S3 S1 S3 S1 S3 S1 S3 S1 S3 S1 S3 S2 S4 S2 S4 S2 S4 S2 S4 S2 S4 S2 S4 S2 S4 S2 S4 PositiveS2 insertedS4 BypassedS2 S4-I PositiveS2 insertedS4 BypassedS2 S4 -I Positive inserted Bypassed-I Positive inserted Bypassed-I Positive inserted Bypassed-I Positive inserted Bypassed-I Figure 24. Switching states arrangement when arm voltage is positive. Figure 24. Switching states arrangement when arm voltage is positive. Meanwhile,Figure a Figurethyristor 24. 24.Switching Switchingwith high states states current arrangement withstand when when capacity arm arm voltage was voltage connected is positive. is positive. in parallel with the lowerMeanwhile, IGBT/diode a inthyristor Figure with25. The high positive current arm withstand current capacity will be bypassedwas connected by the in thyristor parallel withto reduce the Meanwhile, a thyristor with high current withstand capacity was connected in parallel with the thMeanwhile,lowere thermal IGBT/diode stress a thyristor onin Figurethe lower with 25. The highIGBT. positive currentThe utilization arm withstand current of awill capacityparallel be bypassed thyristor was connectedby in the HBSM thyristor inis parallelalso to reduceapplied with the lower IGBT/diode in Figure 25. The positive arm current will be bypassed by the thyristor to reduce lower th IGBTe thermal/diode stress in Figureon the lower25. The IGBT. positive The utilization arm current of a parallel will be thyristor bypassed in HBSM by the is thyristor also applied to reduce the thermal stress on the lower IGBT. The utilization of a parallel thyristor in HBSM is also applied

Electronics 2020, 9, 2068 23 of 37 Electronics 2020, 9, x FOR PEER REVIEW 23 of 37 Electronics 2020, 9, x FOR PEER REVIEW 23 of 37 thein the thermal MMC stress high on voltage the lower DC (HVDC) IGBT. The system utilization to protect of a parallel the lower thyristor diode inunder HBSM the is DC also short applied-circuit in inthe the MMC MMC high high voltage voltage DC DC (HVDC) (HVDC) system system to protect to protect the lowerthe lower diode diode under under the DC the short-circuit DC short-circuit fault. fault.fault.

Figure 25. Half-bridge submodule (HBSM) with a parallel thyristor. Figure 25. HalfHalf-bridge-bridge submodule (HBSM) with a parallel thyristor. 3.3. Parallel Converter System 3.3.3.3. Parallel Parallel C Converteronverter S Systemystem The problem of high-current low-output-voltage conversion at the point-of-load is commonly TheThe problem problem of of high high-current-current low low-output-output-voltage-voltage conversion conversion at at the the point point-of-of-load-load is is commonly commonly resolved by using a parallel connection of multiple converter units. The parallel converter systems resolvedresolved by by using using a a parallel parallel connection connection of of multiple multiple converter converter units. units. The The parallel parallel converter converter systems systems oﬀer a reliability improvement as redundancy quite easily can be implemented. Although the offeroffer a a reliability reliability improvement improvement as as redundancy redundancy quite quite easily easily can can be be implemented. implemented. Although Although the the load load load sharing technique is utilized to distribute the load current and achieve equal sharing of load, sharingsharing technique technique is is utilized utilized to to distribute distribute the the load load current current and and achieve achieve equal equal sharing sharing of of load, load, it it does does it does not guarantee even distribution of thermal stress among parallel converters. The cause of notnot guaranteeguarantee eveneven distributiondistribution ofof thermalthermal stressstress amongamong paralparallellel converters.converters. TheThe causecause ofof thisthis this problem might be the variation in the parameters in the power converters and also the aging problemproblem might might be be the the variation variation in in the the parameters parameters in in the the power power converters converters and and also also the the aging aging effect, effect, eﬀect, which produces the temperature mismatches. In order to overcome this problem, an active whichwhich produces produces the the temperature temperature mismatches. mismatches. In In order order to to overcome overcome this this problem, problem, an an active active thermal thermal thermal sharing was proposed [119–121] for a parallel DC-DC converters system. In this method, sharingsharing was was proposed proposed [119 [119––121121] ]for for a a parallel parallel DC DC-DC-DC converters converters system. system. In In this this method, method, the the load load the load current is redistributed between parallel converters using the temperature values of the power currentcurrent isis redistributedredistributed betweenbetween parallelparallel convertersconverters usingusing thethe temperaturetemperature valuesvalues ofof thethe powerpower converters. The current and temperature information were mixed together, and the new information is converters.converters. The The current current and and temperature temperature information information were were mixed mixed together, together, and and the the new new inform informationation utilized in the average load sharing (Figure 26). This control scheme tends to equalize the thermal isis utilized utilized in in the the average average load load sharing sharing ( Figure(Figure 26). 26). This This control control scheme scheme tends tends to to equalize equalize the the thermal thermal stress among the parallel converters. The advantage of this approach is straightforward to implement stressstress among among the the parallel parallel converters. converters. The The advantage advantage of of this this approach approach is is straightforward straightforward to to implement implement in the existing system; however, there might be a possibility of a slight increase in the individual inin the the existing existing system; system; however, however, there there might might b bee a a possibility possibility of of a a slight slight increase increase in in the the individual individual converter failure rate. converterconverter failure failure rate. rate.

DC/DC converter DC/DC converter Temperature Temperature Load control Load control

DC/DC converter DC/DC converter Temperature Temperature Load control Load Load control Load Load sharingLoad bus

DC/DC converter sharingLoad bus DC/DC converter Temperature Temperature Load control Load control Figure 26. Thermal loading control. Figure 26. Thermal loading control.

TheThe system systemsystem reliability reliability reliability can can can be be beimproved improved improved by by using byusing using an an ATC ATC an method ATCmethod method-based-based-based droop droop control droopcontrol scheme controlscheme [122,123].scheme[122,123]. [122 In In, 123[124], [124],]. In a a [load 124load], sharing asharing load sharing control control control scheme scheme scheme among among among converters converters converters was was reported. reported. was reported. The The droop droop The droop gain gain willgainwill be willbe updated updated be updated according according according to to the the to calculated calculated the calculated consumed consumed consumed lifetime lifetime lifetime of of the the of converters. converters. the converters. Here, Here, Here, the the droop droop the droop gain gain wasgainwas calculated wascalculated calculated following following following the the accumulated accumulated the accumulated consumed consumed consumed lifetime lifetime lifetime (ACL) (ACL) (ACL) by by: : by:

, = ( ) × , (21) , = ( ) × , (21) Rd,k = ACLk(pu) Rdo, (21) where is the maximum allowable 𝑑𝑑droop𝑘𝑘 gain.𝑘𝑘 𝑝𝑝𝑝𝑝 ×Following𝑑𝑑𝑑𝑑 the ACL of each converter, the where is the maximum allowable𝑅𝑅𝑅𝑅 𝑑𝑑droop𝑘𝑘 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 𝐴𝐴𝐴𝐴gain.𝑘𝑘 𝑝𝑝𝑝𝑝 Following𝑅𝑅𝑅𝑅𝑑𝑑𝑑𝑑 the ACL of each converter, the correspondingR droop gains need to be adjusted to achieve an equal ACL for all converters. Thus, the wherecorrespondingdo𝑑𝑑𝑑𝑑 is droop the maximum gains need allowable to be adjusted droop to achieve gain. an Following equal ACL the for ACL all converters. of each converter,Thus, the 𝑅𝑅𝑅𝑅𝑑𝑑𝑑𝑑 loadtheload corresponding sharingsharing amongamong droop thethe converters gainsconverters need is tois achievedachieved be adjusted basedbased to achieveonon thermalthermal an equal stressstress ACL onon thethe for semiconductor allsemiconductor converters. switches;switches; hencehence, , byby activelyactively controllingcontrolling thethe loadingloading ofof converters,converters, thethe ACLACL ofof convertersconverters cancan bebe equalized,equalized, and and the the overall overall system system reliability reliability can can be be enhanced. enhanced.

Electronics 2020, 9, 2068 24 of 37

Thus, the load sharing among the converters is achieved based on thermal stress on the semiconductor switches;Electronics 20 hence,20, 9, x FOR by activelyPEER REVIEW controlling the loading of converters, the ACL of converters can24 of be 37 equalized, and the overall system reliability can be enhanced. In addition to the thermal control based load sharing technique, the power routing method is In addition to the thermal control based load sharing technique, the power routing method is also adopted in the parallel converter system to balance the aging of converter cells. Similar to the also adopted in the parallel converter system to balance the aging of converter cells. Similar to the power routing principle in the cascaded/modular converter system, the authors in [125,126] utilized power routing principle in the cascaded/modular converter system, the authors in [125,126] utilized power routing in parallel DC-DC converters system and two-level voltage source inverter (2L-VSI) power routing in parallel DC-DC converters system and two-level voltage source inverter (2L-VSI) in a in a triple modular permanent magnet synchronous motor (PMSM) drive system, respectively. The triple modular permanent magnet synchronous motor (PMSM) drive system, respectively. The power power routing method, based on the aging status of each converter cell in a parallel system, routing method, based on the aging status of each converter cell in a parallel system, redistributes redistributes the power to each converter cell by adjusting the duty cycle to generate the switching the power to each converter cell by adjusting the duty cycle to generate the switching patterns in the patterns in the modulation stage. Consequently, the lifetime of the most aging converter cell is modulation stage. Consequently, the lifetime of the most aging converter cell is increased to improve increased to improve the reliability of the whole system. the reliability of the whole system. The parallel converters system for wind power applications in Figure 27 has suffered from a The parallel converters system for wind power applications in Figure 27 has suffered from a considerable temperature variation due to the wind speed fluctuation. In [127–130], the ATC is considerable temperature variation due to the wind speed fluctuation. In [127–130], the ATC is applied applied in the wind power system by means of reactive power to smooth the temperature fluctuation in the wind power system by means of reactive power to smooth the temperature fluctuation of power of power devices during wind speed variation, as shown in Figure 27. In the parallel converter, the devices during wind speed variation, as shown in Figure 27. In the parallel converter, the reactive reactive power delivered can significantly influence the loading of components, and it is not power delivered can significantly influence the loading of components, and it is not restrained to the restrained to the existing mechanical/electrical power processed by the converter system so that it is existing mechanical/electrical power processed by the converter system so that it is suitable to achieve suitable to achieve ATC. The reactive power will not only adjust the phase angle between the output ATC. The reactive power will not only adjust the phase angle between the output voltage and current voltage and current of the converter but also change the current amplitude flowing in the power of the converter but also change the current amplitude flowing in the power devices, which are all devices, which are all associated with the power loss and thermal stress of power devices. By associated with the power loss and thermal stress of power devices. By introducing a certain amount of introducing a certain amount of underexcited reactive power to heat up the device during the low underexcited reactive power to heat up the device during the low power period, the overall fluctuation power period, the overall fluctuation of device temperature can be significantly reduced. The of device temperature can be significantly reduced. The disadvantage of reactive power cycling is that disadvantage of reactive power cycling is that it can only be applied in the parallel converter system, it can only be applied in the parallel converter system, and the thermal load of the diode is increased. and the thermal load of the diode is increased.

P 1 Sub-converter 1 VSC1 Lo dv/dt Cd Cf ig1 Transformer P P GB IG Q Grid Lg ig

Lo ig2 dv/dt Cd Cf VSC1 Sub-converter 2 P 2 FigureFigure 27. 27.Parallel Parallel converter converter system system for for wind wind turbine turbine applications. applications. 4. Remaining Useful Lifetime Estimation 4. Remaining Useful Lifetime Estimation The RUL of an asset is deﬁned as the length of time from the present time to the end of useful The RUL of an asset is defined as the length of time from the present time to the end of useful life [131]. The need for RUL estimation is evident because it relates to a frequently asked question life [131]. The need for RUL estimation is evident because it relates to a frequently asked question in in the industry, which is how long a monitored asset can survive based on the available information. the industry, which is how long a monitored asset can survive based on the available information. Based on the RUL estimation, appropriate actions can be planned. The reported RUL techniques Based on the RUL estimation, appropriate actions can be planned. The reported RUL techniques include both model-based and data-driven approaches. include both model-based and data-driven approaches. 4.1. Model-Based Methods 4.1. Model-Based Methods AtypicalflowchartofRULestimationmodel-basedtechniquesisillustratedinFigure28. Inmodel-based A typical flow chart of RUL estimation model-based techniques is illustrated in Figure 28. In approaches, typically, junction temperature information is mandatory and utilized in analytical lifetime model-based approaches, typically, junction temperature information is mandatory and utilized in models such as Coffin–Manson [132] or more detailed Bayerer [133] models, which estimate the number of analytical lifetime models such as Coffin–Manson [132] or more detailed Bayerer [133] models, which estimate the number of cycles to failure under given junction temperature swing amplitude. The junction temperature is estimated by computing the power losses and thermal impedance model of the switch following a mission profile of the power converter system. Meanwhile, temperature cycles are counted using the rain-flow counting algorithm [134]. The accumulated damage as a result of

Electronics 2020, 9, 2068 25 of 37 cycles to failure under given junction temperature swing amplitude. The junction temperature is estimated by computing the power losses and thermal impedance model of the switch following a mission profile Electronics 2020, 9, x FOR PEER REVIEW 25 of 37 of the power converter system. Meanwhile, temperature cycles are counted using the rain-flow counting algorithm [134]. The accumulated damage as a result of different thermal swings is found by using simple different thermal swings is found by using simple linear damage models such as the Palmgren–Miner linear damage models such as the Palmgren–Miner model [135]. model [135].

Wind-speed mission profile Power converter in wind-turbine application system

GB IG

Electrical parameters

Power loss model

Power losses Rainflow counting algorithm

Thermal model Junction temperature Palmgren- Miner Lifetime linear accumulation Temperature damage model cycle distribution

Temperature fluctuation Number of cycle to failure Analytical lifetime model

FigureFigure 28. TypicalTypical diagram of remaining useful lifetime ( (RUL)RUL) estimation technique.

As analyzedanalyzed in in [136 [136,137],,137], correct correct transforming transforming the mission the mission profile profile of the converter of the converter in the real in application the real applicationas wind power as intowind the correspondingpower into the loading corresponding profile of the loading power devicesprofile is of a challengingthe power task. devices According is a challengingto the main causestask. According of loading into a the power main converter causes ofof windloading turbine in a applications, power converter the thermal of wind behavior turbine of applications,power electronic the componentsthermal behavior can be of generally power electronic classified intocomponents three times can constant: be generally long term,classified medium into threeterm, times and short constant: term. long Normally, term, medium a 1-year term, mission and profile short andterm. hourly Normally, mission a 1 profile-year mission are utilized profile to andestimate hourly the mission RUL of profile the power are utilized converters. to estimate In order the to RUL exact of the the temperature power converters. profile fromIn order the to mission exact theprofile, temperature in [138], the profile electrical from parameters the mission are profile, extracted in [138], from the the electrical mission profileparameters by using are extracted the mechanical from thesystem, mission power profile converter by using system, the mechanical and controller. system, The power loss models converter are used system, to calculate and controller. the losses The in loss the modelsswitches are and used diodes to using calculate extracted the electricallosses in parameters. the switches The and thermal diodes loading using or junctionextracted temperature electrical parameters.can be extracted The fromthermal the loading power losses or junction by using temperature the thermal can model be extracted as Cauer from model the or power Foster losses model by in usingFigure the 29a,b thermal [139]. Inmodel [138], as the Cauer utilized model thermal or Foster model model use mix in ofFigure both 29a Cauer,b [139]. and Foster In [138], thermal the utilized models thermalto solve themodel shortcoming use mix of of both the twoCauer stated and models,Foster thermal as shown models in Figure to solve 29c. the Consequently, shortcoming the of junctionthe two sttemperatureated models, of poweras shown devices in Figure can be 29c. obtained. Consequently, the junction temperature of power devices can be obtained.As mentioned earlier, the lifetime of the power converter is related to the magnitude and the frequency of these temperature cycles. Each cycle applies different stresses to the module and further leads to a particular lifetime consumed. ThereRth1 are severalRth2 cycleR countingth,n methods being developed for the study of fatigue damage, such as level crossing counting, peak counting, simple range counting, and the rainflow counting. The rainflow counting algorithm in Figure 30 is usually adopted to extract Ploss Cth1 Cth2 Cth,n Tcase the thermal cycles from the acquired thermal profile. This algorithm was initially named the “Pagoda Roof Method.” It can be explained as a random stress S(t) representing a series of roofs onto which water falls, with time being the vertical axis. The(a detailed) principle of using the rainflow counting algorithm is presented in [140] and not repeated here.

Rth1 Rth2 Rth,n

Ploss Tcase

Cth1 Cth2 Cth,n

(b)

Electronics 2020, 9, x FOR PEER REVIEW 25 of 37

different thermal swings is found by using simple linear damage models such as the Palmgren–Miner model [135].

Wind-speed mission profile Power converter in wind-turbine application system

GB IG

Electrical parameters

Power loss model

Power losses Rainflow counting algorithm

Thermal model Junction temperature Palmgren- Miner Lifetime linear accumulation Temperature damage model cycle distribution

Temperature fluctuation Number of cycle to failure Analytical lifetime model

Figure 28. Typical diagram of remaining useful lifetime (RUL) estimation technique.

As analyzed in [136,137], correct transforming the mission profile of the converter in the real application as wind power into the corresponding loading profile of the power devices is a challenging task. According to the main causes of loading in a power converter of wind turbine applications, the thermal behavior of power electronic components can be generally classified into three times constant: long term, medium term, and short term. Normally, a 1-year mission profile and hourly mission profile are utilized to estimate the RUL of the power converters. In order to exact the temperature profile from the mission profile, in [138], the electrical parameters are extracted from the mission profile by using the mechanical system, power converter system, and controller. The loss models are used to calculate the losses in the switches and diodes using extracted electrical parameters. The thermal loading or junction temperature can be extracted from the power losses by using the thermal model as Cauer model or Foster model in Figure 29a,b [139]. In [138], the utilized Electronicsthermal2020, 9model, 2068 use mix of both Cauer and Foster thermal models to solve the shortcoming of the two 26 of 37 stated models, as shown in Figure 29c. Consequently, the junction temperature of power devices can be obtained.

Rth1 Rth2 Rth,n

Ploss Cth1 Cth2 Cth,n Tcase Electronics 2020, 9, x FOR PEER REVIEW 26 of 37

(a) Module 4-layer Foster model (From datasheetR ) R R Power th1 th2 th,n R R R R losses th1 th2 th3 th4 Tref Ploss + − Tcase

Pin Cth1 Cth2 Cth,n

Electronics 2020, 9, x FORC PEERth1 REVIEWCth2 Cth3 Cth4 Thermal 26 of 37 (b) grease

Rth1" Rth2" ModuleRth1 4' -layer Foster model (From datasheet) Power Pout Tc Rth1 Rth2 Rth3 Rth4 Cth1' losses Cth1" Cth2" + − Tref Heat sink P in 2-layer Foster model Module 1C-layerth1 equivalentCth2 CauerCth 3 Cth4 Thermal (From datasheet) model (Calculated from Foster model) grease (c) Rth1" Rth2" Rth1' Figure 29. Thermal network: (a) Cauer model, (b) Foster model, (c) Combined model. Pout Tc Cth1' As mentioned earlier, the lifetime of the power converter is related to theCth1 "magnitudeCth2" and the frequency of these temperature cycles. Each cycle applies different stresses to theHeat module sink and further leads to a particular lifetime consumed. There are several cycle counting methods2-layer Foster being model developed Module 1-layer equivalent Cauer for the study of fatigue damage, such as level crossing counting, peak (counting,From datasheet simple) range model (Calculated from Foster model) counting, and the rainflow counting. The rainflow counting algorithm in Figure 30 is usually adopted to extract the thermal cycles from the acquired thermal(c) profile. This algorithm was initially named the “Pagoda Roof Method.” It can be explained as a random stress S(t) representing a series of roofs onto whichFigure Figurewater 29. Thermal 29.falls, Thermal with network: time network: being (a ()a ) Cauerthe Cauer vertical model,model, axis. ( (bb) )TheFoster Foster detailed model, model, (princc) (Combinedc)iple Combined of usingmodel. model. the rainflow counting algorithm is presented in [140] and not repeated here. As mentioned earlier, the lifetime of the power converter is related to the magnitude and the frequency of these temperature cycles. Each cycle applies different stresses to the module and further Stress leads to a particular lifetime consumed. There are several cycle counting methods being developed for the study of fatigue damage, such as level crossing counting, peak counting, simple range A counting, and the rainflow counting. The rainflow counting Balgorithm in Figure 30 is usually adopted to extract the thermal cycles from the acquired thermalC profile. This algorithm was initially named the “Pagoda Roof Method.” It can be explained as a random stressD S(t) representing a series of roofs onto which water falls, with time being the vertical axis. The detailed principle of using the rainflow E counting algorithm is presented in [140] and not repeatedF here. G H Stress I J K A L M B C N D Time

E FigureFigure 30. 30.Example Example of of thethe rainflowrainflow Fcounting counting algorithm. algorithm. G H By employing the rainflow counting algorithm, the decomposed temperature cycles distributed By employing the rainflow counting algorithm,I the decomposedJ temperature cycles distributed into the rainflow histogram according to their amplitudes are acquired. In order to calculate the into the rainflow histogram according to their amplitudesK are acquired. In order to calculate the lifetime, the analytical model is adopted to describe the dependenceL on the number of cycles to lifetime,failure. the analytical Among the model analytical is adopted modeling to methods,M describe the the Coffin dependence–Manson onmodel the [124] number is the of most cycles widely to failure. utilized technique, presented as: N Time

Figure 30. Example of the rainflow counting algorithm.

By employing the rainflow counting algorithm, the decomposed temperature cycles distributed into the rainflow histogram according to their amplitudes are acquired. In order to calculate the lifetime, the analytical model is adopted to describe the dependence on the number of cycles to failure. Among the analytical modeling methods, the Coffin–Manson model [124] is the most widely utilized technique, presented as:

Electronics 2020, 9, 2068 27 of 37

Among the analytical modeling methods, the Coffin–Manson model [124] is the most widely utilized technique, presented as: n N = α ∆T − , (22) f × j where ∆Tj is the fluctuation of the junction temperature, whereas coefficients α and n can be fitted by simulation or cyclic experiment. Although the Coffin–Manson model is the simplest model, it does not take the frequency of cycles and heating and cooling times into account, resulting in a low accurate result. Another model from Coffin–Mason–Arrhenius [141] considers the mean junction temperature besides the temperature variation, described as:

n Ea N = α ∆T − e kTj,m , (23) f × j × where k is the Boltzmann constant and Ea is the activation energy parameter. The Norris–Landzberg model is based on (23) and additionally takes into account the cycling frequency of the junction temperature, as shown in (24):

n1 n Ea/(kTj m) N = A f − 2 ∆T − e , , (24) f × × j × where f is the frequency of the junction temperature; n1 and n2 are constant ﬁtted by experimental data. The most complicated model, the Bayerer model [134], has a large number of parameters and considers more detailed information during the power cycling tests and power module characteristics, written as follow:

β1 β2/(Tj max+274K) β3 β β β N = K ∆T − e , t + I− 4 + V− 5 + D− 6 , (25) f × j × × on where Tj,max is the maximum junction temperature, ton is the heating time, I is the applied DC current, V is the blocking voltage, and D is the diameter of the bond wire. These constants β are ﬁtted by experimental data. Then, the lifetime is presented as the inverse of the total damage accumulated within a power module until the suspension of its normal operation by using Miner’s rule [127], whereas the total consumed lifetime (CL) or damage can be deﬁned as the sum of all the fractional damages, described as following: X N Damage = CL = i , (26) N f where Ni is the number of cycles in the stress range and N f is the number of cycles to failure. The lifetime of the devices LF can be simply calculated as follows:

1 LF = . (27) CL

4.2. Data-Driven Based Methods Different from the model-based method, the data-driven methods involve the processing of experimental data to derive an empirical degradation model from estimating the RUL of the power module. The degradation data are usually the on-state resistance variation for the power MOSFETs [142,143], on-state voltage [144]. The author of [142,143] proposed an RUL estimation approach for MOSFETs based on the on-state resistance variation. In the first step, cyclic thermal stress is conducted for several days to a few weeks to measure the on-state resistance. In this experiment, the thermal swing amplitude has been kept constant throughout the aging. In order to observe the on-state variation under thermal swings with variable amplitudes, another test has been performed on the power MOSFET, which experienced ten consecutive thermal cycles of different amplitudes. Electronics 2020, 9, 2068 28 of 37

In the second step, from the collected on-state resistance data through the exhaustive experiments, an empirical model is built to estimate the RUL of the switches. In [142], an exponential degradation model is generated from the experimental data, described as the following:

R (k + 1) = R (k) (1 + ∆tβ) R β∆t. (28) ds,on ds,on × − init A Kalman filter is applied to the empirical model given in (28) to calculate the empirical coefficients by the least-squares method. KF is a widely acknowledged optimal state estimator assuming a Gaussian distribution through minimizing the mean square error (mse) of the estimates considering the errors in the measurements and the model. Using the computed empirical coefficients up to the current time step, the RUL of the degraded switch is predicted. Another aging precursor is the collector-emitter voltage drop utilized in [144] to estimate the RUL of discrete IGBT devices based on the Gaussian process. Similar to the utilization of on-state resistance in [142], the impact of accelerated thermal aging test on the on-state voltage drop is analyzed. The resulted behavior of the on-state voltage drop can be generalized, as illustrated in [144]. This generic behavior is critical to analyze for generating an early warning signal to the end-utilizer before complete device failure. Based on the collected data from accelerated thermal aging tests, an RUL estimation model based on Bayesian inference under the notion of Gaussian process regression was utilized. The data-driven methods do not require the junction temperature measurement, they utilize the physical parameters as on-state resistance or on-state voltage drop instead. However, the variation of on-state resistance or on-state voltage drop under thermal tests is sensitive to the applied power level and changes in the temperature. Due to this fact, although the physical parameters as on-state resistance or on-state voltage drop can be utilized to get the RUL indication, it requires applying modern methods to increase the accuracy of RUL results.

5. Discussion of Enhancing Reliability Techniques The performance of CM techniques varies with different application domains as it is corresponds to the maintenance availability, measurement uncertainties, and cost. In terms of maintenance availability, because the power systems need to be maintained as quickly as possible after the degradation has been detected since the degradation will speed up the wear-out process. If the maintenance cannot be achieved quickly, the converter may break down first, making it unreliable. This means that the more difficult the maintenance available, the poorer the performance of CM. Regarding measurement uncertainties, it can be noticed that the CM indicators can be affected by numerous degradation mechanisms instead of a specific one. For example, resolving junction temperature from the measurement of TSEPs can be challenging due to many reasons as the low sensitivity of junction temperature, dependence on loading conditions, and measurement inaccuracies. The ideal TSEPs can be applicable to any device type, any converter topology, suitable for any application. However, for the case of online TSEPs measurements, the proposed solutions may only be adaptable to particular converter topologies. Therefore, some TSEPs have advantageous qualities, but due to implementation issues, they may only be able to be sampled periodically without causing unacceptable disruption to normal converter operation. Furthermore, some indicators are difficult to measure under real working conditions. This leads to the current state of online CM technique development not being technically feasible enough. In some practical applications, as in industry, the cost is an indispensable factor in addition to the performance. Regarding CM techniques, the complicated external circuits might be the trouble in practical implementing. In this sense, the CM approaches with simple and low-cost external hardware are better for those applications that are cost-limited, volume-limited, and weight-limited. Based on the CM result of power semiconductor devices, the output of the converter can be reduced to avoid significant stress on the components. This allows the power system can work for a longer time than expected. However, the reduced output of the converter exerts a negative impact on the overall performance of the power system. In this case, the ATC can be applied to extending Electronics 2020, 9, 2068 29 of 37 the lifetime of the power system without modifying the design of the converter or external hardware, meaning that there is an additional cost. However, the trade-off between the output performance of the power system and extending lifetime should be carefully considered. The utilization of ATC without deteriorating the power system performance is a critical aspect. The potential of a specific ATC algorithm is highly dependent on the type of converter and corresponding applications. For example, electric drive applications require an immediate effect. Thus, the switching frequency control is promising. Meanwhile, the change of the modulation method is limited and might affect the losses of power semiconductor devices. Further quantitative comparison among different ATC methods should be investigated to make a reasonable tradeoff among lifetime, efficiency, and power density for various applications of power converter system. The CM and ATC techniques are proposed to extend the lifetime of the power converter system. Meanwhile, the RUL estimation techniques can be used to decide whether to apply maintenance or ATC and verify the effect of ATC. The basic advantage of the data-driven-based method is that it does not require junction temperature information but involving the processing of experimental data to derive an empirical degradation model. Furthermore, the data-driven-based method can be integrated into a low-cost controller for real-time failure prognosis, which would significantly increase the reliability of the power converter system. According to the discussion above, it can be noticed that the correlation among techniques aims at increasing the reliability of the power converter system to be closed.

6. Conclusions The reliability of the power converter system is becoming increasingly important for power electronics and has attracted much interest. A literature overview of the reliability improvement for the power converter system based on increasing the reliability of the power semiconductor devices is presented. The IGBT and SiC MOSFET chip-level, package-level structure, and associating failure modes and mechanisms are summarized. The power semiconductor devices are the most fragile components to examine. Based on the individual failure mode, the failure indicators and corresponding CM techniques are discussed. Although CM techniques have been developed in earlier work, they are mainly implemented in controlled offline conditions, which makes high cost and infeasible implementation. The recent CM methods, which can be implemented in real-time operation of the converters, concerning TSEPs and other failure indicators, for both IGBT and SiC MOSFET, are reviewed. Furthermore, the ATC techniques, classified into three main categories following the structure of power converter systems, are investigated. In addition to the converter type, the application and the trade-off between thermal controllability and general output performance should be investigated further. Finally, the two types of RUL estimation techniques for the power converter are summarized. The model-based lifetime estimation approach is preferred over the data-driven based method due to its simplicity and accuracy. Based on the aforementioned analysis, in addition to the advances in reliability improvement techniques, some challenges are discussed to address in the future. Challenges: (1) Based on the basics of existing CM techniques, it is still required to find out more failure indicators that can more accurately indicate the health condition, especially for the SiC devices—understanding the effect of failure and other impacts such as temperature on changes of failure indicators. (2) It is significantly required to find a method to monitor many failures at the same time by using one or more failure indicators. Therefore, an accurate and reliable decoupling of the failure indicators and TSEPs should be investigated. (3) In addition to the CM at the device level, the converter-based or system-level CM techniques need to be further developed to find out more failure indicators based on the power system output performance. Furthermore, an approach utilized to locate the failure devices should be investigated to assist the system-level CM approaches. Electronics 2020, 9, 2068 30 of 37

(4) The need for a CM method when the power converter is working is significant. Apparently, the variation of electrical and thermal parameters during system operation, especially in photovoltaic and wind turbine applications, complicates the CM techniques. (5) In terms of the ATC, the trade-off among ATC efficiency, output performance, and cost should be considered. The utilization of ATC without deteriorating the power system performance is a critical aspect. Furthermore, the verification of ATC with practical applications should be more investigated. (6) The linear damage accumulation method, such as the Palmgre–Miner model, is widely utilized. Besides, the non-linear damage accumulation methods need to be developed to increase the accuracy of the lifetime modes. Opportunities: (1) The advances in semiconductor materials and packaging technologies provide more aspects for exploring them as far as reliability issues are concerned. (2) New technologies with measurement circuitry for high-frequency applications are further developed, which provide an open window to apply them in terms of CM techniques without interrupting the operation of the power converter system. (3) Further development of a real-time monitoring system helps obtain better mission profile data for various types of power converter systems to improve RUL estimation accuracy.

Author Contributions: Conceptualization, S.K.; methodology, S.K., M.H.N.; software, M.H.N.; validation, S.K., M.H.N.; formal analysis, M.H.N.; investigation, M.H.N.; resources, S.K.; data curation, M.H.N.; writing—original draft preparation, M.H.N.; writing—review and editing, S.K.; visualization, M.H.N.; supervision, S.K.; project administration, S.K.; funding acquisition, S.K. All authors have read and agreed to the published version of the manuscript. Funding: This research was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (No. 2020R1A2C1013413), and funded and conducted under the Competency Development Program for Industry Specialists of the Korean Ministry of Trade, Industry and Energy (MOTIE), operated by Korea Institute for Advancement of Technology (KIAT) (No. P0012453, Next-generation Display Expert Training Project for Innovation Process and Equipment, Materials Engineers). Conﬂicts of Interest: The authors declare no conﬂict of interest.

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