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AMD64 Architecture Programmer's Manual, Volume 2, System

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AMD64 Architecture Programmer's Manual, Volume 2, System AMD64 Technology AMD64 Architecture Programmer’s Manual Volume 2: System Programming Publication No. Revision Date 24593 3.11 December 2005 Advanced Micro Devices AMD64 Technology 24593—Rev. 3.11—December 2005 © 2002–2005 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular pur- pose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD Arrow logo, AMD Athlon, AMD Opteron and combinations thereof, 3DNow!, nX586, and nX686 are trademarks, and AMD-K6 is a registered trademark of Advanced Micro Devices, Inc. MMX is a trademark and Pentium is a registered trademark of Intel Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 24593—Rev. 3.11—December 2005 AMD64 Technology Contents Figures . xv Tables . .xxi Revision History . xxv Preface . xxvii About This Book . xxvii Audience . xxvii Contact Information. xxvii Organization . .xxviii Definitions. .xxix Related Documents . xli 1 System-Programming Overview . 1 1.1 Memory Model. 1 Memory Addressing. 2 Memory Organization . 4 Canonical Address Form. 5 1.2 Memory Management . 6 Segmentation . 6 Paging . 8 Mixing Segmentation and Paging . 10 Real Addressing. 11 1.3 Operating Modes . 12 Long Mode . 14 64-Bit Mode . 15 Compatibility Mode . 15 Legacy Modes. 16 System Management Mode (SMM) . 17 1.4 System Registers . 17 1.5 System-Data Structures . 20 1.6 Interrupts . 22 1.7 Additional System-Programming Facilities . 24 Hardware Multitasking . 24 Machine Check . 25 Software Debugging . 26 Performance Monitoring. 26 2 x86 and AMD64 Architecture Differences . 29 2.1 Operating Modes . 29 Long Mode . 29 Legacy Mode . 30 System-Management Mode . 30 Contents iii AMD64 Technology 24593—Rev. 3.11—December 2005 2.2 Memory Model. 31 Memory Addressing. 31 Page Translation . 31 Segmentation . 33 2.3 Protection Checks . 35 2.4 Registers. 35 General-Purpose Registers . 35 128-Bit Media Registers . 36 Flags Register . 36 Instruction Pointer . 36 Stack Pointer . 36 Control Registers. 36 Debug Registers. 36 Extended Feature Register (EFER) . 37 Memory Type Range Registers (MTRRs) . 37 Other Model-Specific Registers (MSRs) . 37 2.5 Instruction Set . 37 REX Prefixes . 37 Segment-Override Prefixes in 64-Bit Mode. 38 Operands and Results . 38 Address Calculations. 38 Instructions that Reference RSP . 39 Branches . 40 NOP Instruction. 43 Single-Byte INC and DEC Instructions . 43 MOVSXD Instruction . 43 Invalid Instructions . 44 FXSAVE and FXRSTOR Instructions . 45 2.6 Interrupts and Exceptions . 46 Interrupt Descriptor Table . 46 Stack Frame Pushes . 46 Stack Switching . 47 IRET Instruction . 47 Task-Priority Register (CR8) . 48 New Exception Conditions . 48 2.7 Hardware Task Switching . 48 2.8 Long-Mode vs. Legacy-Mode Differences . 49 3 System Resources. 51 3.1 System-Control Registers . 51 CR0 Register . 53 CR2 and CR3 Registers. 56 CR4 Register . 58 CR1 and CR5–CR7 Registers . 62 64-Bit-Mode Extended Control Registers . 62 CR8 (Task Priority Register, TPR). 63 RFLAGS Register . 63 Extended Feature Enable Register (EFER) . 68 iv Contents 24593—Rev. 3.11—December 2005 AMD64 Technology 3.2 Model-Specific Registers (MSRs) . 71 System Configuration Register (SYSCFG) . 72 System-Linkage Registers . 74 Memory-Typing Registers . 74 Debug-Extension Registers . 75 Performance-Monitoring Registers . 75 Machine-Check Registers . ..
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