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Nxvl™ System Controller Databook NxVL™ System Controller Databook PRELIMINARY March 4, 1994 PROPRIETARY and CONFIDENTIAL COPYING is FORBIDDEN NexGen"" Microproducts, Inc. 1623 Buckeye Drive Milpitas, CA 95035 Order # NxDOC-DB002-01-W NexGen, Nx586, Nx587, RISC86, NexBus, NxPCI, and NxVL are trademarks of NexGen Microproducts, Inc. NOTICE: THESE MATERIALS ARE PROPRIETARY TO NEXGEN AND ARE PROVIDED PURSUANT TO A CONFIDENTIALITY AGREEMENT FOR YOUR EVALUATION QfiL.'{, ANY VIOLATION IS SUBJECT TO LEGAL ACTION. Copyright © 1993,1994 by NaGen Microproducts, Inc. The goal of this databook is to enable our customers to make informed purchase decisions and to design systems around our described products. Every effort is made to provide accurate information in support of these goals. However, representations made by this data book are not intended to describe the internal logic and physical design. Wherever product internals are discussed, the information should be construed as conceptual in nature. No presumptions should be made about the internal design based on this document. Infor:mation about the internal design ofNexGen products is provided via nondisclosure agreement ("NDA") on a need to know basis. The material in this document is for information only and is subject to change without notice. NexGen reserves the right to make changes in the product specification and design without reservation and without notice to its users. THIS DOCUMENT DOES NOT CONSTITUTE A WARRANTY OF ANY KIND WITH RESPECT TO THE NEXGEN INC. PRODUCTS, AND NEXGEN INC. SHALL NOT BE LIABLE FOR ANY ERRORS THAT APPEAR IN THIS DOCUMENT. All purchases of NexGen products shall be subject to NexGen's standard terms and conditions of sale. THE WARRANTIES AND REMEDIES EXPRESSLY SET FORTH IN SUCH TERMS AND CONDITIONS SHALL BE THE SOLE WARRANTIES AND THE BUYER'S SOLE AND EXCLUSIVE REMEDIES, AND NEXGEN INC. SPECIFICALLY DISCLAIMS ANY AND ALL OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE, AGAINST INFRINGEMENT AND OF MERCHANTABILITY. No person is authorized to make any other warranty or representation concerning the performance of the NexGen products. In particular, NexGen's products are not specifically designed, manufactured or intended for sale as components for the planning, design, construction, maintenance, operation or use of any nuclear facility or other ultra-hazardous activity, and neither NexGen nor its suppliers shall have any liability with respect to such use Trade11UlTk Acknowledgments NexGen, NxS86, NxS87, RISC86, NexBus, NxPCI, and NxVL are trademarks of NexGen Microproducts, Inc.. IBM, AT, and PS/2 are registered trademarks of International Business Machines, Inc. Intel is a registered trademark of Intel Corporation. B86, B87, i486 and Pentium are trademarks of Intel Corporation. Tri-state is a registered trademark of National Semiconductor Corporation. VL-Bus is a trademark of Video Electronics Standards Association. Restricted Rights and LimiUltWns Use, duplication, or disclosure by the Government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in technical Data and Computer Software clause at 252.2777-7013 NexGen, Nx586, Nx587, RISC86, NexBus, NxPCI, and NxVL are trademarks of NexGen Microproducts, Inc. NOTICE: THESE MATERIALS ARE PROPRIETARY TO NEXGEN AND ARE PROVIDED PURSUANT TO A CONFIDENTIALITY AGREEMENT FOR YOUR EVALUATION ONLY. ANY VIOLATION IS SUBJECT TO LEGAL ACTION. Contents Contents Preface ................................................................................................... vii Notation ............................................................................................................. vii Related Publications ........................................................................................... ix NxVL Features and Signals .................................................................... 1 NxVL Pinouts by Signal Names ........................................................................... 4 NxVL Pinouts by Pin Numbers ............................................................................ 6 NexBus Signals ................................................................................................... 10 NexBus Arbitration ...................................................................................... 10 NexBus Cycle Control ................................................................................. 11 NexBus Cache Control ................................................................................ 12 NexBus Transceiver Control ....................................................................... 13 NexBus Address and Data Bus .................................................................... 13 VL-Bus Signals ................................................................................................... 14 VL-Bus Arbitration ...................................................................................... 14 VL-Bus Cycle Control ................................................................................. 14 VL-Bus Address .......................................................................................... 16 VL-Bus Data ................................................................................................ 16 ISA Bus Signals .................................................................................................. 17 ISA-Bus Cycle Control. ............................................................................... 17 ISA-Bus Transceiver Control ...................................................................... 19 ISA-Bus Address, Refresh, and Oock......................................................... 20 Memory-Bus Signals .......................................................................................... 21 Integrated Peripheral Controller (IPC) Signals ................................................... 22 NxVL System Signals ......................................................................................... 23 NxVL Alphabetical Signal Summary ................................................................. 25 Hardware Architecture.... ~ ..................................................................... 29 System Overview ................................................................................................ 29 Internal Architecture ........................................................................................... 34 Main-Memory Write Queue ........................................................................ 36 Bus Structure ...................................................................................................... 37 PRELIMINARY NxVLTIl Systems Logic III NexGen, Nx585, Nx587, RISC85, NexBus, NxPCI, and NxVL are trademarks of NexGen Microproducts, Inc. NOTICE: THESE MATERIALS ARE PROPRIETARY TO NEXGEN AND ARE PROVIDED PURSUANT TO A CONFIDENTIALITY AGREEMENT FOR YOUR EVALUATION ONLY. ANY VIOLATION IS SUBJECT TO LEGAL ACT/ON. Contents NexGenTII NexBus ....................................................................................................... 37 VL-Bus ....................................................................................................... 40 ISA-bus ....................................................................................................... 41 Bus Arbitration .................................................................................................. 47 Bus-Crossing Operations ......................................... , ......................................... 48 Memory .............................................................................................................. 49 Organization ............................................................................................... 49 Read/Write Reordering ............................................................................... 50 DMA Transfers ........................................................................................... 50 Bus Snooping and Cache Coherency ................................................................. 51 Design Example ................................................................................................. 52 Bus Operations ......................................................................................53 Arbitration Protocols .......................................................................................... 53 Bus-Arbitration Protocol ............................................................................ 54 Main-Memory Arbitration ProtocoL ......................................................... 57 Nx586 Processor Operations .............................................................................. 59 Bus Arbitration, Address Phase, and Data Phase........................................ 59 Processor Write to Main Memory .............................................................. 64 Processor Read from Main Memory ........................................................... 65 Processor Write to VL Slave ...................................................................... 68 Processor Read from VL Slave ................................................................... 71 Processor Write to ISA Slave ..................................................................... 72 Processor Read from ISA Slave .................................................................. 75 Snooping and Processor Intervention .....................................................
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