Parallel Thread Execution Isa

PARALLEL THREAD EXECUTION ISA v5.0 | June 2017 Application Guide TABLE OF CONTENTS Chapter 1. Introduction.........................................................................................1 1.1. Scalable Data-Parallel Computing using GPUs....................................................... 1 1.2. Goals of PTX...............................................................................................2 1.3. PTX ISA Version 5.0...................................................................................... 2 1.4. Document Structure...................................................................................... 2 Chapter 2. Programming Model............................................................................... 4 2.1. A Highly Multithreaded Coprocessor...................................................................4 2.2. Thread Hierarchy......................................................................................... 4 2.2.1. Cooperative Thread Arrays........................................................................ 4 2.2.2. Grid of Cooperative Thread Arrays...............................................................5 2.3. Memory Hierarchy........................................................................................ 6 Chapter 3. PTX Machine Model................................................................................9 3.1. A Set of SIMT Multiprocessors with On-chip Shared Memory...................................... 9 Chapter 4. Syntax.............................................................................................. 12 4.1. Source Format........................................................................................... 12 4.2. Comments.................................................................................................12 4.3. Statements................................................................................................13 4.3.1. Directive Statements.............................................................................. 13 4.3.2. Instruction Statements............................................................................ 13 4.4. Identifiers.................................................................................................14 4.5. Constants................................................................................................. 15 4.6. Integer Constants........................................................................................15 4.6.1. Floating-Point Constants.......................................................................... 15 4.6.2. Predicate Constants............................................................................... 16 4.6.3. Constant Expressions.............................................................................. 16 4.6.4. Integer Constant Expression Evaluation........................................................ 17 4.6.5. Summary of Constant Expression Evaluation Rules........................................... 18 Chapter 5. State Spaces, Types, and Variables...........................................................20 5.1. State Spaces..............................................................................................20 5.1.1. Register State Space.............................................................................. 21 5.1.2. Special Register State Space.....................................................................22 5.1.3. Constant State Space..............................................................................22 5.1.3.1. Banked Constant State Space (deprecated)..............................................22 5.1.4. Global State Space................................................................................ 23 5.1.5. Local State Space..................................................................................23 5.1.6. Parameter State Space............................................................................23 5.1.6.1. Kernel Function Parameters................................................................ 24 5.1.6.2. Kernel Function Parameter Attributes.................................................... 25 5.1.6.3. Kernel Parameter Attribute: .ptr.......................................................... 25 5.1.6.4. Device Function Parameters................................................................ 26 www.nvidia.com Parallel Thread Execution ISA v5.0 | ii 5.1.7. Shared State Space................................................................................ 27 5.1.8. Texture State Space (deprecated).............................................................. 27 5.2. Types.......................................................................................................28 5.2.1. Fundamental Types................................................................................ 28 5.2.2. Restricted Use of Sub-Word Sizes............................................................... 29 5.3. Texture Sampler and Surface Types..................................................................29 5.3.1. Texture and Surface Properties..................................................................30 5.3.2. Sampler Properties.................................................................................31 5.3.3. Channel Data Type and Channel Order Fields.................................................33 5.4. Variables.................................................................................................. 34 5.4.1. Variable Declarations.............................................................................. 34 5.4.2. Vectors............................................................................................... 34 5.4.3. Array Declarations................................................................................. 35 5.4.4. Initializers........................................................................................... 35 5.4.5. Alignment............................................................................................37 5.4.6. Parameterized Variable Names.................................................................. 37 5.4.7. Variable Attributes.................................................................................37 5.4.8. Variable Attribute Directive: .attribute........................................................ 38 Chapter 6. Instruction Operands............................................................................ 39 6.1. Operand Type Information............................................................................. 39 6.2. Source Operands.........................................................................................39 6.3. Destination Operands................................................................................... 40 6.4. Using Addresses, Arrays, and Vectors................................................................40 6.4.1. Addresses as Operands............................................................................40 6.4.2. Arrays as Operands................................................................................ 40 6.4.3. Vectors as Operands...............................................................................41 6.4.4. Labels and Function Names as Operands...................................................... 41 6.5. Type Conversion......................................................................................... 41 6.5.1. Scalar Conversions................................................................................. 42 6.5.2. Rounding Modifiers.................................................................................42 6.6. Operand Costs........................................................................................... 43 Chapter 7. Abstracting the ABI.............................................................................. 44 7.1. Function Declarations and Definitions............................................................... 44 7.1.1. Changes from PTX ISA Version 1.x.............................................................. 47 7.2. Variadic Functions.......................................................................................47 7.3. Alloca......................................................................................................48 Chapter 8. Instruction Set.................................................................................... 50 8.1. Format and Semantics of Instruction Descriptions.................................................50 8.2. PTX Instructions......................................................................................... 50 8.3. Predicated Execution................................................................................... 51 8.3.1. Comparisons.........................................................................................51 8.3.1.1. Integer and Bit-Size Comparisons.......................................................... 51 8.3.1.2. Floating Point Comparisons................................................................. 52 www.nvidia.com Parallel Thread Execution ISA v5.0 | iii 8.3.2. Manipulating Predicates...........................................................................53 8.4. Type Information for Instructions and Operands................................................... 53 8.4.1. Operand Size Exceeding Instruction-Type Size................................................ 54 8.5. Divergence of Threads in Control

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