An Improved Voltage Clamp Circuit Suitable for Accurate Measurement of the Conduction Loss of Power Electronic Devices

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Article An Improved Voltage Clamp Circuit Suitable for Accurate Measurement of the Conduction Loss of Power Electronic Devices

Qiuping Yu, Zhibin Zhao *, Peng Sun, Bin Zhao and Yumeng Cai

State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources, North China Electric Power University, Beijing 102206, China; [email protected] (Q.Y.); [email protected] (P.S.); [email protected] (B.Z.); [email protected] (Y.C.) * Correspondence: [email protected]

Abstract: Power electronic devices are essential components of high-capacity industrial converters. Accurate assessment of their power loss, including switching loss and conduction loss, is essential to improving electrothermal stability. To accurately calculate the conduction loss, a drain–source voltage clamp circuit is required to measure the on-state voltage. In this paper, the conventional drain–source voltage clamp circuit based on a transistor is comprehensively investigated by theoretical analysis, simulations, and experiments. It is demonstrated that the anti-parallel diodes and the gate-shunt capacitance of the conventional drain–source voltage clamp circuit have adverse impacts on the accuracy and security of the conduction loss measurement. Based on the above analysis, an improved drain–source voltage clamp circuit, derived from the conventional drain–source voltage clamp circuit, is proposed to solve the above problems. The operational advantages, physical structure, and design guidelines of the improved circuit are fully presented. In addition, to evaluate the inﬂuence of component parameters on circuit performance, this article comprehensively extracts three electrical Citation: Yu, Q.; Zhao, Z.; Sun, P.; quantities as judgment indicators. Based on the working mechanism of the improved circuit and Zhao, B.; Cai, Y. An Improved Voltage the indicators mentioned above, general mathematical analysis and derivation are carried out to Clamp Circuit Suitable for Accurate give guidelines for component selection. Finally, extensive experiments and detailed analyses are Measurement of the Conduction Loss of Power Electronic Devices. Sensors presented to validate the effectiveness of the proposed drain–source voltage clamp circuit. Compared 2021, 21, 4285. https://doi.org/ with the conventional drain–source voltage clamp circuit, the improved drain–source voltage clamp 10.3390/s21134285 circuit has higher measurement accuracy and working security when measuring conduction loss, and the proposed component selection method is veriﬁed to be reasonable and effective for better Academic Editor: Toan Phung utilizing the clamp circuit.

Received: 3 June 2021 Keywords: power electronic devices; drain–source voltage clamp circuit; power loss; conduction Accepted: 21 June 2021 loss; on-state voltage Published: 23 June 2021

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in 1. Introduction published maps and institutional affil- iations. High-voltage, large-capacity power electronic conversion equipment dramatically improves the transmission capacity of the flexible AC/DC grid as well as the electric trac- tion control ability [1]. As the voltage withstand ability and switching frequency of power semiconductor devices continue to increase, and the volume continues to decrease, power electronic converters have higher efficiency and power density [2–4]. However, converters Copyright: © 2021 by the authors. face reliability challenges. The overheating failure of the internal power electronic devices Licensee MDPI, Basel, Switzerland. is one of the main reasons for damage to the converter [5–7], and most heat comes from This article is an open access article the power loss of power semiconductor devices. Imprecise power loss measurement will distributed under the terms and lead to the wrong design of the thermal management system (TMS), which will affect the conditions of the Creative Commons Attribution (CC BY) license (https:// reliability and cause premature failure of the equipment [8,9]. Accurately obtaining the creativecommons.org/licenses/by/ power loss of the device is a crucial prerequisite for determining the thermal solution, 4.0/). which will affect the efficiency, cost, and power density of the entire system.

Sensors 2021, 21, 4285. https://doi.org/10.3390/s21134285 https://www.mdpi.com/journal/sensors Sensors 2021, 21, 4285 2 of 19

Common methods for obtaining power loss are calorimetry [10,11], building a physical model [12,13], establishing a loss look-up table or fitting power loss as a function [14,15], and directly integrating the product of the square of the on-state current root mean square and the on-state resistance [16]. However, the above methods often introduce significant errors due to model or measurement problems. At present, an accurate way to calculate power loss, including switching loss and conduction loss, is to measure the on-state drain–source voltage (vds_on) across the device and the current (id) flowing through the device and then integrate their product. How- ever, when calculating the conduction loss, it is difficult to measure the on-state voltage accurately. It is directly related to the operating characteristics of the power semiconductor device that frequently converts between the on state and the off state. The off-state drain– source voltage (vds_off) can reach hundreds or thousands of volts, while the on-state voltage vds_on is only a few volts [17], making it challenging to select a suitable oscilloscope range. An excessive range will lead to a significant error in the on-state voltage measurement, and more seriously, the measurement result may be negative due to the influence of noise. If the oscilloscope range is set too small, the “oscilloscope saturation” phenomenon will be seen [18]. The drain–source voltage clamp circuit (DVCC) is frequently used to measure the on-state voltage vds_on by clamping the off-state voltage of the device under test (DUT) to a lower value. In existing research, six types of DVCCs have been proposed for the measurement of vds_on. The DVCC proposed in [19,20] clamps the off-state voltage of the DUT by using the high-voltage breakdown characteristics of the Zener diode. It is simple to implement. However, its measurement error due to the leakage current of the Zener diode and its measurement delay due to the resistance–capacitance (RC) loop limit its further application. Gelagaev [18] analyzed the DVCC based on a current mirror in detail, and this circuit solved the problem of measurement delay. However, it has been shown that since the output currents on both sides of the current mirror cannot be entirely consistent, the current flowing through the diodes on both sides may be different, which may cause measurement errors. Furthermore, in [21], a DVCC based on one diode is described. The forward voltage of its diode is affected by temperature and current, leading to cumbersome corrections for vds_on. This problem was resolved in [22,23]. The DVCC proposed in [22,23] introduced two diodes and a proportional amplifier circuit to improve measurement accuracy. However, due to the difference in the physical positions and forward current of the two diodes, it is difficult to ensure that the voltage drop of the two diodes is equal, which may lead to inaccurate results. Yu et al. [24] presented an innovative design for the DVCC with improved real-time measurement accuracy. Guacci et al. described a DVCC in [25], which can accurately correct the voltage offset caused by the diode voltage drop and has a higher measurement accuracy. Both of these circuits in [24,25] introduce operational amplifiers, which increases the complexity of the course. A DVCC integrated with a half-bridge circuit was employed in [26] for device evaluation in the hard-switching test and the soft-switching conditions. However, this DVCC ignores the influence of diode leakage current on the on-state voltage measurement, and there may be measurement errors. The DVCC based on the transistor is analyzed in [27]. It avoids most of the problems mentioned earlier. However, the gate–source spike voltage due to the instantaneous high current of the transistor gate resistance may damage the DVCC itself. Additionally, the purpose of designing this circuit is to measure on-state resistance Rds_on, and it is not suitable for conduction loss measurement. In summary, these existing DVCCs, in terms of measurement accuracy, work complexity, and design aim, cannot be used for conduction loss (Ploss_on) measurement of power semiconductor devices. Therefore, this paper concerns the drawbacks of the conventional DVCC based on the transistor (hereinafter referred to as “conventional DVCC”) and proposes an improved DVCC (hereinafter referred to as “improved DVCC”) architecture suitable for the Ploss_on measurement. The new circuit is derived from the conventional DVCC. The remainder of this paper is organized as follows. In Section2, the circuit struc- Sensors 2021, 21, 4285 3 of 19

ture, work principle, and drawbacks of the conventional DVCC are analyzed in detail. Then, the schematic and the advantages of the improved DVCC are presented. Furthermore, the inﬂuence of the components’ parameters on the circuit performance of the improved DVCC is analyzed in Section3. Here, component selection guidelines are also given. In Section4, the measurement accuracy and work security improvement of the improved DVCC are veriﬁed through simulated and experimental comparisons with the conventional DVCC. Simultaneously, the effectiveness of the selection theory is also investigated and proven. Finally, Section5 concludes this paper.

2. Design of the Improved DVCC Compared with the existing DVCCs, which are mainly applied to the on-state resistance measurement of the DUT, more problems need to be considered when designing a DVCC suitable for conduction loss measurement. After the DUT is turned on, it will go through two typical states, enter the oscillation state (on-oscillation state), and gradually reach steady state (on-steady state). The measurement results of these existing DVCCs can well reﬂect the on-state voltage vds_on_ste when the DUT is in the on-steady state. However, when measuring the conduction loss, in addition to the above-mentioned on-steady state voltage, the DVCC must be able to accurately measure the on-state voltage vds_on_osc when the DUT is in the on-oscillation state. Any error at any stage will cause errors in the calculation of the device conduction loss. In addition, many common problems need to be avoided in both on-state resistance and conduction loss measurement. First of all, the DVCCs cannot have measurement delays. Once the voltage data lag or lead the current data, errors will occur in the loss integral calculation. Secondly, power electronic devices, such as diodes, metal–oxide– semiconductor ﬁeld–effect transistors (MOSFET), etc., are often introduced into DVCCs to realize the voltage clamping function. Due to the faster switching speed and higher operating voltage of the DUT, it is easy to make these auxiliary devices out of safe working conditions. Therefore, when designing a DVCC, it is necessary to focus on the security of these auxiliary devices.

2.1. The Structure and Working Principle of the Conventional DVCC The schematic diagram of the conventional DVCC is shown in Figure1. The auxiliary device MOSFET (M) is used to withstand the high off-state voltage of the DUT, thereby limiting the potential of the voltage measurement point A. The DC voltage supply Vcc and the gate resistor R2 are located at the gate of M, and together with the resistor R3, they control the turn-on and turn-off of M. The D and S terminals of the circuit are connected Sensors 2021, 21, x FOR PEER REVIEWto the drain and source of the DUT, respectively, while the A and B terminals are used4 of to19

measure output voltage (vout).

M D A - vgs_M + D1 D3

R2 i2 i3 C0 D2 R3 Vcc

S B FigureFigure 1.1. TheThe schematicschematic diagramdiagram ofof thethe conventionalconventional DVCC.DVCC.

2.2. DrawbacksWhen the of DUT the Conventional is in the off-state, DVCCD 3 is broken down, causing the current ﬂowing throughIn viewR3 to of increase the fact sharply. that the Atpurpose this time, of the the conventional source potential DVCC of M is rises,to measure and the the gate- on- sourcestate resistance, voltage v gs_Mwhendecreases. it is applied When to conducvgs_M istion less loss than measurement, the threshold there voltage are someVth_M severeof M, Mproblems, is turned which off and are shares further most discussed of the in off-state the following voltage, subsections. limiting vout to a small voltage

2.2.1. Low Measurement Accuracy To reduce the voltage negative overshoot between A and B when the DUT is turned on, the conventional DVCC connects the diodes D1 and D2 in reverse parallel between the measurement points A and B and utilizes their unidirectional conductivity characteristics to eliminate the voltage overshoot. Assume that the forward voltage drops of diodes are VD1 and VD2, respectively. Dur- ing the on-oscillation state, if vds_on_osc is greater than −(VD1 + VD2), D1 and D2 are reversely cut off. Therefore, vout = vds_on_osc. Once vds_on_osc is less than −(VD1 + VD2), D1 and D2 will immediately switch to the forward conduction state, and the output voltage will remain unchanged at −(VD1 + VD2), resulting in vout ≠ vds_on. The two diodes limit the negative voltage overshoot and do not affect the on-state resistance measurement. However, when measuring the conduction loss, the loss during oscillation cannot be ignored [28]. The conventional DVCC cannot measure vds_on_osc accurately nor can it accurately measure the conduction loss.

2.2.2. Low Working Security

To reduce the current flowing through the DC voltage supply (Vcc) and ensure the safety of Vcc, the conventional DVCC shown in Figure 1 has a capacitor C0 connected in parallel to the gate of M [22]. However, the existence of C0 seriously affects the work security of auxiliary device M. When the DUT is turned off, the drain–source voltage vds and the current on R3 increases sharply, which will cause an instantaneous negative overshoot Vgs_M(max) at the gate–source of M. If Vgs_M(max) exceeds the gate−source voltage withstand limit of M (Vgs_limit), M will be burned. If negative overshoot Vgs_M(max) occurs at time t0, the gate−source voltage vgs_M of M will be a negative value in the time interval [t0 − Δt, t0 + Δt]. According to Figure 1, it can be known from KVL that during this period, vgs_M can be written as in Equation (1), and Vgs_M(max) = vgs_M(t0):

vgs_M = Vcc + i2R2 − VD3 − i3R3, (1)

where VD3 is the breakdown voltage of Zener diode D3; i2 and i3 are the current flowing through R2 and R3, respectively. Adding C0 to the gate of M will reduce i2(t0), which can protect Vcc. However, since Vgs_M(max) is negative, the decrease in i2(t0) will cause the absolute value of Vgs_M(max) to increase significantly, which will endanger the safety of the MOSFET. In contrast, the impulse current withstand capability of the widely used DC voltage supply can reach several amperes or tens of amperes. Even without C0, i2(t0) is not enough to cause harm to Vcc. Therefore, the benefit of C0 is far less than the harm it causes.

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value. When the DUT is turned on, the source potential of M decreases, causing the vgs_M to become higher than Vth_M, bringing the M into conduction. As a result, vout is equal to vds_on.

2.2. Drawbacks of the Conventional DVCC In view of the fact that the purpose of the conventional DVCC is to measure the on-state resistance, when it is applied to conduction loss measurement, there are some severe problems, which are further discussed in the following subsections.

2.2.1. Low Measurement Accuracy To reduce the voltage negative overshoot between A and B when the DUT is turned on, the conventional DVCC connects the diodes D1 and D2 in reverse parallel between the measurement points A and B and utilizes their unidirectional conductivity characteristics to eliminate the voltage overshoot. Assume that the forward voltage drops of diodes are VD1 and VD2, respectively. During the on-oscillation state, if vds_on_osc is greater than −(VD1 + VD2), D1 and D2 are reversely cut off. Therefore, vout = vds_on_osc. Once vds_on_osc is less than −(VD1 + VD2), D1 and D2 will immediately switch to the forward conduction state, and the output voltage will remain unchanged at −(VD1 + VD2), resulting in vout 6= vds_on. The two diodes limit the negative voltage overshoot and do not affect the on-state resistance measurement. However, when measuring the conduction loss, the loss during oscillation cannot be ignored [28]. The conventional DVCC cannot measure vds_on_osc accurately nor can it accurately measure the conduction loss.

2.2.2. Low Working Security

To reduce the current ﬂowing through the DC voltage supply (Vcc) and ensure the safety of Vcc, the conventional DVCC shown in Figure1 has a capacitor C0 connected in parallel to the gate of M [22]. However, the existence of C0 seriously affects the work security of auxiliary device M. When the DUT is turned off, the drain–source voltage vds and the current on R3 increases sharply, which will cause an instantaneous negative overshoot Vgs_M(max) at the gate–source of M. If Vgs_M(max) exceeds the gate−source voltage withstand limit of M (Vgs_limit), M will be burned. If negative overshoot Vgs_M(max) occurs at time t0, the gate−source voltage vgs_M of M will be a negative value in the time interval [t0 − ∆t, t0 + ∆t]. According to Figure1, it can be known from KVL that during this period, vgs_M can be written as in Equation (1), and Vgs_M(max) = vgs_M(t0):

vgs_M= Vcc+i2R2 − VD3 − i3R3, (1)

where VD3 is the breakdown voltage of Zener diode D3; i2 and i3 are the current flowing through R2 and R3, respectively. Adding C0 to the gate of M will reduce i2(t0), which can protect Vcc. However, since Vgs_M(max) is negative, the decrease in i2(t0) will cause the absolute value of Vgs_M(max) to increase significantly, which will endanger the safety of the MOSFET. In contrast, the impulse current withstand capability of the widely used DC voltage supply can reach several amperes or tens of amperes. Even without C0, i2(t0) is not enough to cause harm to Vcc. Therefore, the benefit of C0 is far less than the harm it causes.

2.3. Proposal of the Improved DVCC The schematic of the improved DVCC for conduction loss measurement is described in Figure2. By conducting two changes in the structure of the conventional DVCC, the problems existing in the conventional DVCC are solved. Sensors 2021, 21, x FOR PEER REVIEW 5 of 19

2.3. Proposal of the Improved DVCC

Sensors 2021, 21, 4285 The schematic of the improved DVCC for conduction loss measurement is described5 of 19 in Figure 2. By conducting two changes in the structure of the conventional DVCC, the problems existing in the conventional DVCC are solved.

D M A - vgs_M + D3

R2 i2 i3 R3 Vcc S B

Figure 2. The schematic diagram of the improved DVCC.DVCC.

Firstly, to accurately accurately measure measure vvds_on_oscds_on_osc of theof theDUT, DUT, the improved the improved DVCC DVCC removes removes anti- anti-parallelparallel diodes diodes (i.e., (i.e.,D1 andD1 Dand2 in DFigure2 in Figure 1) from1) fromthe output the output voltage voltage measurement measurement point. point.Under Underthis arrangement, this arrangement, the on-state the on-state voltage voltage of the of two the stages, two stages, on-steady on-steady state state and andon- on-oscillationoscillation state, state, both both have have high high measurement measurement accuracy. accuracy. Furt Furthermore,hermore, the thecalculation calculation er- errorror of of conduction conduction loss loss is islimited limited to to a asmall small value. value. In addition, addition, considering considering the the harmfulness harmfulness of ofC0 toC0 theto core the coredevice device M, another M, another improve- im- provementment is to remove is to remove the gate-shunt the gate-shunt capacitance capacitance (i.e., C0 (i.e.,in FigureC0 in 1). Figure This 1measure). This measure dramati- dramaticallycally improves improves the operating the operating environment environment of M. In of addition, M. In addition, there is there no need is no to need worry to worryabout aboutthe safety the safety of Vcc of. VForcc. typical For typical DC DCsources, sources, their their impulse impulse current current tolerance tolerance oftenoften reaches severalseveral ampsamps oror tenstens ofof amps,amps, whilewhile thethe maximummaximum currentcurrent ﬂowingflowing through throughV Vcccc isis usually hundreds ofof milliamps.milliamps. Therefore, thethe workwork safetysafety ofof VVcc willwill not not be be threatened. threatened.

3. Component Selection In SectionSection2 ,2, the the pros pros of of the the improved improved DVCC DVCC and and the consthe cons of conventional of conventional DVCC DVCC were highlighted.were highlighted. In this In section, this section, the inﬂuence the influe of componentnce of component parameters parameters on the performance on the perfor- of themance improved of the DVCCimproved is analyzed DVCC is in analyzed detail. Furthermore, in detail. Furthermore, guidelines for guidelines component for selection compo- arenent given selection to utilize are given the improved to utilize circuitthe improved better. circuit better. 3.1. Evaluation Indicators 3.1. Evaluation Indicators Theoretically, there are three conditions that the circuit must meet to perform the Theoretically, there are three conditions that the circuit must meet to perform the functions of clamping and measuring normally, as listed below. functions of clamping and measuring normally, as listed below. 1. Ensure the security of core MOSFET (M); 1. Ensure the security of core MOSFET (M); 2. M should be in the proper working state when the DUT is in the on-state; 2. M should be in the proper working state when the DUT is in the on-state; 3. M should be in the proper working state when the DUT is in the off-state. 3. M should be in the proper working state when the DUT is in the off-state. Considering the above three restrictions,restrictions, thisthis articlearticle comprehensivelycomprehensively extractsextracts threethree electrical quantitiesquantities asas thethe judgmentjudgment indicators indicators of of the the circuit circuit performance performance to to guide guide compo- com- nentponent selection: selection: 1. Gate−source voltage negative overshoot (Vgs_M(max)) of M, which is denoted as EI1. 1. Gate−source voltage negative overshoot (Vgs_M(max)) of M, which is denoted as EI1. As As indicated in Section2, it is necessary to avoid Vgs_M(max) exceeding the gate– indicated in Section 2, it is necessary to avoid Vgs_M(max) exceeding the gate–source tol- source tolerance of core M. Therefore, the low EI1 value is of greater signiﬁcance for erance of core M. Therefore, the low EI1 value is of greater significance for improving improving the security of M. the security of M. 2. Gate−source voltage of M (vgs_M(on)) when the DUT is in the on-state, which is 2. Gate−source voltage of M (vgs_M(on)) when the DUT is in the on-state, which is denoted denoted as EI2. If the DUT is in the on-state, M should also be in the on-state to satisfy as EI2. If the DUT is in the on-state, M should also be in the on-state to satisfy vout = vout = vds_on. Therefore, the second evaluation indicator should meet EI2 > Vth_M. vds_on. Therefore, the second evaluation indicator should meet EI2 > Vth_M. 3. Gate−source voltage of M (vgs_M(off)) when the DUT is in the off-state, which is 3. Gate−source voltage of M (vgs_M(off)) when the DUT is in the off-state, which is denoted denoted as EI3. When the DUT is in the off-state, the working state of M should also as EI3. When the DUT is in the off-state, the working state of M should also be con- be consistent with the DUT to withstand high off-voltage and reduce the potential sistent with the DUT to withstand high off-voltage and reduce the potential of the of the measurement point A. Under this condition, EI3 should be less than Vth_M, so that M can be turned off reliably [29].

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3.2. Selection of MOSFET Since the parameters of M are closely related to the safe operation of the entire circuit, criteria for selecting the subject are proposed based on the working principle of the improved DVCC. As stated before, with the transitions of DUT from the on-state to the off-state, M also changes its state rapidly so as to prevent the continuous increase of the source current of M and prevent EI1 from being too large. Similarly, when the DUT changes from the off-state to the on-state, M needs to be turned on immediately to avoid measurement delay. Therefore, it is recommended that the switching speed of M be consistent with or faster than DUT, which is the ﬁrst criterion for the selection of M. In addition, since the improved DVCC utilizes the high blocking voltage characteristic of M to exercise the clamping function, during the off-state of the DUT, the drain–source withstand voltage of M is almost the same as that of the DUT. To increase the operational reliability of M, it is advised that the blocking voltage level of M is consistent with or higher than the DUT, which is considered the second criterion.

3.3. Selection of DC Voltage Supply Vcc and Zener Diode Breakdown Voltage VD3 3.3.1. Selection Principle of VD3

Since Zener diode D3 is in the gate−source loop of M, EI1 is one of the vital evaluation indicators for selecting VD3. The inﬂuence of VD3 on the work security of M is analyzed in this subsection. According to Figure2, the gate −source negative overshoot of M can be expressed as follows: EI1= Vcc+I2R2 − VD3 − I3R3, (2)

where I2 and I3 are the currents ﬂowing through R2 and R3 at time t0, respectively. According to Equation (2), VD3 increases, and the absolute value of EI1 increases accordingly. Based on the interpretation content of the ﬁrst evaluation indicator, for high security of M, VD3 should be as small as possible.

3.3.2. Voltage Constraint for Effective Work

The DC voltage supply Vcc and the Zener diode D3 jointly control the turn-on and turn-off of M to make it follow the steps of the state change of DUT. Therefore, it can be seen that the values of vgs_M(on) and vgs_M(off) are closely related to Vcc and VD3. Based on the supplementary content when the second and third evaluation indicators are proposed, it can be estimated that Vcc and VD3 have a mutually restrictive relationship. In this paper, this speciﬁc constraint is called the “voltage constraint for effective work (VCEW)” and is further discussed in the subsequent sections. When the DUT is in the on-state, EI2 can be expressed as in the equation below:

EI2= Vcc+i2_onR2 − vds_on, (3)

where i2_on is the current ﬂowing through the resistor R2 when the DUT is in the on-state. Since M is also in the on-state, i2_on can be obtained as follows:

i2_on= ig_M ≈ 0, (4)

where ig_M is the gate current of M. Therefore, Equation (3) can be simpliﬁed to

EI2= Vcc − vds_on. (5)

If the working condition of the DUT is known, the maximum on-state voltage Von_max of the DUT is determined. At this time, the size of EI2 depends on the value of the DC Sensors 2021, 21, 4285 7 of 19

voltage supply (Vcc). To ensure that M is in the on-state, it should meet the following condition: Vcc > Von_max+Vth_M. (6)

When the DUT is in the off-state, EI3 can be described as follows:

EI3= Vcc+i2_offR2 − VD30 − i3_offR3, (7)

where i2_off and i3_off are the currents ﬂowing through R2 and R3, respectively, when the 0 DUT is in the off-state; VD3 is the voltage across the Zener diode D3. Since M is in the off-state, i2_off and i3_off can be obtained as follows:

i3_off= ileak_M ≈ 0, (8)

i2_off= ig_M ≈ 0, (9)

where ileak_M is the leakage current of M. Equation (7) is further simpliﬁed to

0 EI3 = Vcc−VD3 . (10)

When the DUT is in the off-state, D3 has two possible scenarios [30]. If the leakage 0 current of D3 is more signiﬁcant than M, D3 is in the reverse cut-off state, and VD3 meets the condition: 0 VD3 ≤ VD3. (11) 0 In this scenario, a voltage equilibrium will be established: as Vcc changes, VD3 changes accordingly, so that EI3 is always maintained at a voltage less than Vth_M. According to Equation (11), when selecting Vcc, its value should satisfy the following condition:

Vcc − VD3 < Vth_M. (12)

In another scenario, if the leakage current of D3 is less than M, D3 is in the breakdown 0 state and VD3 = VD3. Obviously, in this circumstance, Vcc is selected based on the below equation: EI3= Vcc − VD3 < Vth_M. (13) Considering Equations (6), (12), and (13) and adding in a margin of error, Equation (14) is written to reveal the mechanism of VCEW.

V > V +V cc on_max th_M . (14) Vcc−VD3 < 0

3.4. Selection of Gate Resistance R2 and Source Resistance R3 3.4.1. Selection Principle of R2 and R3

R2 and R3 are located in different branches of the gate−source loop of M, so that they have the opposite effect on EI1 (Vgs_M(max)). Therefore, by choosing appropriate R2 and R3 values, the gate−source voltage negative overshoot (Vgs_M(max)) of M can be suppressed as much as possible. At t0, when the Vgs_M(max) occurs, M has been completely turned off, and the improved DVCC can be equivalent to the course shown in Figure3[29]. Sensors 2021, 21, 4285 8 of 19 Sensors 2021, 21, x FOR PEER REVIEW 8 of 19

Cd Cs D I d_M Cg D3 R I2 2 I3 R3 Vcc S

Figure 3. Equivalent circuit of the improved DVCC.DVCC.

According to FigureFigure3 3,, the the ﬁrst first evaluation evaluation indicator indicator can can be be expressed expressed as as

a(b-jc) EI1=Vcc − VD3a+(b2− jcId_M) , (15) EI = V − V + b +c2 I , (15) 1 cc D3 b2+c2 d_M a = R2Cg − R3Cs,  = b = C− + C ,  a R2Cg g R3sCs, (16) c = wCb =sCCgRg2+ +C wCs, sCgR3, (16)  c = wCsCgR2+wCsCgR3, where Id_M is the drain current of M. whereAccordingId_M is the to drain [29], currentat this time, of M. Cg << Cs. The coefficient of the third term in Equation (15) isAccording abbreviated to [29 as], e at + this jf. Then, time, Ctheg << realCs .and The imaginary coefficient ofparts the of third EI1 term can be in Equationwritten as (15) in isEquations abbreviated (17) and as e (18),+ jf. respectively; Then, the real and imaginary parts of EI1 can be written as in Equations (17) and (18), respectively; Re ( EI1) = eId_M + |Vcc − VD3|, (17) Re(EI 1) =|eId_M| + |Vcc − VD3|, (17) Im ( EI1) = jfId_M, (18)

Im(EI 1(R)2 =Cg-Rj 3fC Is)(Cd_Ms+C g,) (18) |e| = 2 2, (19) (Cg+Cs) +(wCsCgR2+wCsCgR3) (R 2Cg−R3Cs)(C s+Cg |e| = (R2Cg-R3Cs)(wCsCgR2+wCsCgR3) 2 , (19) ( f += ) +( 2 + 2 . )2 (20) C g Cs(Cg+Cs)wC+(wCsCsCggR22+wCwCsCgRs3C) gR3

−12 Since the parasitic capacitance of MOSFET is pF level (10 ), and the oscillation fre- (R 2Cg−R3Cs)(wC sCgR2+wCsCgR3) quency of drain current| f | is= generally MHz level (106~108). Therefore, . (Cg + Cs) >> (wCsC (20)gR2 ( + )2+( + )2 + wCsCgR3). Based on this, Equations C g C s(21) andwC (22sCg)R can2 wC be sderived;CgR3 Since the parasitic capacitance of MOSFET|e| ≫ f, is pF level (10−12), and the oscillation(21) 6 8 frequency of drain current is generally(R MHzC -R C level)(C +C ) (10 R~10C -R).C Therefore, (Cg + Cs) >> | | | | 2 g 3 s s g 3 s 2 g (wCsCgR + wCsCgR ). BasedEI on1 ≈ this, e ≈ Equations (21)2 and = (22) can. be derived; (22) 2 3 (Cg+Cs) Cg+Cs

According to Equation (22), |EI1| is|e positively| |f|, correlated with R3 and negatively (21)correlated with R2. Therefore, the selection guide for these two resistors is to increase R2 and decrease R3 as much as possible. ( RIt Cis worth−R C noting)(C + Cthat thisR increaseC −R C or decrease is not | | ≈ | | ≈ 2 g 3 s s g = 3 s 2 g unlimited, whichEI is1 describede in more detail in the2 following subsection. . (22) + ) Cg+Cs (C g Cs

3.4.2.According Measurement to Equation Error Constraint (22), |EI 1| is positively correlated with R3 and negatively correlatedDuring with the Ron-oscillation2. Therefore, state, the selection with R3 guidedecreasing, for these the twomeasurement resistors is accuracy to increase of theR2 andon-state decrease voltageR3 asvds_on_osc much asgradually possible. decreases. It is worth To noting make that the this relative increase error or decreaseof the vds_on_osc is not unlimited,measurement which less is than described r%, R3 incannot more be detail too insmall. the followingThis paper subsection. refers to this constraint relationship as the “measurement error constraint” (MEC). 3.4.2. Measurement Error Constraint During the on-oscillation state, vds_on_osc can be described as follows: During the on-oscillation state, with R3 decreasing, the measurement accuracy of the v = v +v , (23) on-state voltage vds_on_osc gradually decreases.ds_on_osc Tods_M makeout the relative error of the vds_on_osc r R measurementwhere vds_M is the less drain–source than %, 3 cannotvoltage beof M. too small. This paper refers to this constraint relationship as the “measurement error constraint” (MEC).

Sensors 2021, 21, 4285 9 of 19

During the on-oscillation state, vds_on_osc can be described as follows:

vds_on_osc= vds_M+vout, (23)

where vds_M is the drain–source voltage of M. During this process, vds_on_osc gradually shifts from the on-oscillation state to the on-steady state in the form of a second-order oscillation. According to the structure of the improved DVCC, D3 is connected in reverse between A and B. Therefore, when vds_on_osc > 0, D3 is in the reverse cut-off state, and vout can be expressed as follows:

RD3_off+R3 vout= vds_on_osc × , (24) RD3_off+R3+Rds_M

where RD3_off is the equivalent resistance of D3 when it is in the reverse cut-off state; Rds_M is the equivalent resistance of M. Since M has been fully turned on at this stage, Rds_M has the same value as the on-state resistance of M. In addition, considering that D3 can be regarded as an open circuit at this time, the relationship between vout and vds_on_osc can be expressed as follows:

vout ≈ vds_on_osc. (25)

However, when vds_on_osc < 0, D3 is in the forward conduction state, and vout can be expressed as follows:

RD3_on+R3 vout= vds_on_osc × , (26) RD3_on+R3+Rds_M

where RD3_on is the equivalent resistance of D3 when it is in the forward conduction state. In this case, it is essential that the resistance of R3 not be too small, so that the measurement accuracy is not compromised due to the partial voltage of Rds_M. Therefore, restricted by MEC, R3 needs to meet the following condition:

RD3_on+R3 vds_on_osc×(1 − ) < vds_on_osc×r%. (27) RD3_on+R3+Rds_M

Furthermore, Equation (27) is simpliﬁed to

1 − r% R > R × ( ) − R , (28) 3 ds_M r% D3_on where r% is generally around 5%.

3.4.3. Switching Speed Constraint

R2 is located at the gate of M. Therefore, when R2 increases, the gate charging and discharging speed of the gate driver are slowed down accordingly [29]. In an attempt to ensure that the switching speed of M is not slower than that of the DUT, R2 cannot be too large. This paper calls this constraint relationship the “switching speed constraint” (SSC). In order to obtain the limit of R2, the influence of R2 on the rising speed of vgs_M is simplified as the influence of R2 on the charging time constant when M is turned on. According to Equations (5) and (10), when M is turned on, the amount of change in vgs_M 0 is ((Vcc − vds_on) − (Vcc − VD3 )). Therefore, restricted by SSC, R2 needs to meet the following condition:

0 (V −v ) − (V −V ) Vg_max−V cc ds_on cc D3 < th_DUT , (29) A B Sensors 2021, 21, 4285 10 of 19

( 1 A = R C 2 gs_M (30) B = 1 RgCgs_DUT

where Vg_max is the gate−source voltage stability value of the DUT; Rg and Vth_DUT are the gate drive resistance and the threshold voltage of the DUT, respectively; and Cgs_M and Cgs_DUT are the gate−source parasitic capacitances of M and DUT, respectively. 0 Considering that VD3 ≤ VD3, Equation (30) can be further simpliﬁed to RgCgs_DUT(V g_max−Vth_DUT Sensors 2021, 21, x FOR PEER REVIEW R < .10 of 19 (31) 2 Cgs_M((V cc−vds_on) − (V cc−VD3))

4. Simulation and Experimental Veriﬁcation 4. Simulation and Experimental Verification This paper set up a test platform integrating conventional DVCC and improved DVCC,This as shownpaper inset Figure up a 4test, to evaluateplatform theintegrating measurement conventional accuracy DVCC and work and safetyimproved of the improvedDVCC, as DVCC shown and in Figure the correctness 4, to evaluate of the th selectione measurement theory. accuracy The primary and work circuit safety of the of test the improved DVCC and the correctness of the selection theory. The primary circuit of the platform is a double pulse test circuit (DPTC), including a DUT, freewheeling diode D0, test platform is a double pulse test circuit (DPTC), including a DUT, freewheeling diode bus capacitor Cbus, digital signal processing (DSP), and drive module Vg. DSP is used to D0, bus capacitor Cbus, digital signal processing (DSP), and drive module Vg. DSP is used transmit drive signals to control the turn-on and turn-off of the DUT. to transmit drive signals to control the turn-on and turn-off of the DUT. The voltage clamp circuit comprises a MOSFET (M), DC source Vcc, gate resistance The voltage clamp circuit comprises a MOSFET (M), DC source Vcc, gate resistance R2, source resistance R3, and Zener diode D3. In order to facilitate the comparison between R2, source resistance R3, and Zener diode D3. In order to facilitate the comparison between the improved DVCC and conventional DVCC, the connectors for the gate-shunt capacitor the improved DVCC and conventional DVCC, the connectors for the gate-shunt capacitor C0 and the anti-parallel diodes D1 and D2 are reserved. C0 and the anti-parallel diodes D1 and D2 are reserved.

Bus capacitor Freewheeling diode DUT Driver module

CDVCC and NDVCC DSP

(a) (b) (c) Figure 4. Test platform. (a) Test platform overview; (b) DVCC section; (c) gate driver. Figure 4. Test platform. (a) Test platform overview; (b) DVCC section; (c) gate driver.

TheThe speciﬁcspecific experimental conditions conditions are are listed listed in Table in Table 1. Both1. Boththe DUT the and DUT the and aux- the auxiliaryiliary device device M are M arethe the1200 1200 V/31.6 V/31.6 A SiC A MOSFET SiC MOSFET produced produced by CREE, by CREE,while the while free- the wheeling diode D0 is the SiC Schottky diode of the unified manufacturer. freewheeling diode D0 is the SiC Schottky diode of the uniﬁed manufacturer. Table 1. Test conditions. Table 1. Test conditions. Parameters Value Parameters Value VDC 400 V/500 V Cbus VDC 200 μF400 V/500 V µ Lload Cbus 0.7 mH 200 F Lload 0.7 mH Vg +20 V/−5 V Vg +20 V/−5 V According to the experimental platform shown in Figure 4, the corresponding equivalent simulation circuit is extracted, as shown in Figure 5. Inside the dotted frame on the right is the DVCC, while the double pulse circuit is in the dotted frame on the left, and its circuit components are shown in Table 2. The simulation models of DUT, M, and D0 are all from the semiconductor company that produces the device, and the parasitic parameters are extracted by finite element simulation software.

Table 2. Circuit parameter index.

Symbol Parameters Lg1 Parasitic inductance of the gate of the DUT Ld1 Parasitic inductance of the drain of the DUT Ls1 Parasitic inductance of the source of the DUT Rd1 Parasitic resistance of the drain of the DUT Rs1 Parasitic resistance of the source of the DUT Rg Gate drive resistance of the DUT

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According to the experimental platform shown in Figure4, the corresponding equivalent simulation circuit is extracted, as shown in Figure5. Inside the dotted frame on the right is the DVCC, while the double pulse circuit is in the dotted frame on the left, and its circuit components are shown in Table2. The simulation models of DUT, M, and D0 are all from the semiconductor company that produces the device, and the parasitic parameters are extracted by ﬁnite element simulation software.

Table 2. Circuit parameter index.

Symbol Parameters

Lg1 Parasitic inductance of the gate of the DUT L Parasitic inductance of the drain of the DUT Sensors 2021, 21, x FOR PEER REVIEW d1 11 of 19 Ls1 Parasitic inductance of the source of the DUT Rd1 Parasitic resistance of the drain of the DUT Rs1 Parasitic resistance of the source of the DUT Rg Gate drive resistance of the DUT D0 Freewheeling diode D0 Freewheeling diode VDC Bus voltage VDC Bus voltage

DPTC

Lload Rd1

CF Ld1 DVCC D0 M A

VDC Cbus DUT

Rg Lg1 D1 D3

R2 D R3 C0 2

Vg Vcc Rs1 B

Ls1

Figure 5. Equivalent simulation circuit. Figure 5. Equivalent simulation circuit.

4.1.4.1. ConductionConduction LossLoss MeasurementMeasurement AccuracyAccuracy 4.1.1. Quantitative Simulation Analysis 4.1.1. Quantitative Simulation Analysis Since the oscilloscope cannot measure the accurate value of the on-state voltage vds_on, Since the oscilloscope cannot measure the accurate value of the on-state voltage vds_on, it is hard to quantitatively analyze the relative error between the output voltage vout it is hard to quantitatively analyze the relative error between the output voltage vout and and vds_on through experiments. Therefore, this work uses the simulation circuit shown invds_on Figure through5 to compare experiments. the on-state Therefore, voltage this work and conductionuses the simulation loss measurement circuit shown accuracy in Fig- betweenure 5 to compare the conventional the on-state DVCC voltage and and the improvedconduction DVCC. loss measurement Under the working accuracy condition between DC thatthe conventionalVDC is set to 500DVCC V, the and simulation the improved results DVCC. are shown Under in the Figure working6. condition that V is set to 500V, the simulation results are shown in Figure 6.

900 900 v v Conventional DVCC Improved DVCC out ds vout vds

600 600 (V) (V) ds ds v 300 v 300

On−oscillation state On−steady state On−oscillation state On−steady state 0 0

8101214 8 101214 time(μs) time(μs) (a) (b) 40 40 vout vds Conventional DVCC vout vds Improved DVCC

20 20 (V) (V) ds ds v v 0 0

T T2 T T1 T2 T -20 1 3 -20 3 11.55 11.60 11.65 11.70 11.7 11.55 11.60 11.65 11.70 11.7 time(μs) time(μs) (c) (d)

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900 900 v v Conventional DVCC Improved DVCC out ds vout vds

600 600

(V)

ds v 300 v 300

On−oscillation state On−steady state On−oscillation state On−steady state 0 0

8 10 12 14 8 10 12 14 time(μs) time(μs) (a) (b) 40 40 vout vds Conventional DVCC vout vds Improved DVCC

20 20

(V)

v v 0 0

T T T T1 T2 T -20 1 2 3 -20 3 11.55 11.60 11.65 11.70 11.75 11.55 11.60 11.65 11.70 11.75 time(μs) time(μs) (c) (d)

3.0 3.0 v v Conventional DVCC out ds vout vds Improved DVCC

2.5 2.5

(V) (V)

ds 2.0 ds

v 2.0 v

1.5 T4 T5 T6 1.5 T4 T5 T6

1.0 12.0 12.2 12.4 12.6 1.0 12.0 12.2 12.4 12.6 time(μs) time(μs) (e) (f)

Figure 6. vout and vds waveform comparison. (a) Waveform overview of the conventional DVCC; (b) waveform overview Figure 6. v and v waveform comparison. (a) Waveform overview of the conventional DVCC; (b) waveform overview of of the improvedout DVCC;ds (c) waveform of the conventional DVCC during the on-oscillation state; (d) waveform of the theimproved improved DVCC DVCC; during (c) waveform the on-oscillation of the conventional state; (e) waveform DVCC during of the conventional the on-oscillation DVCC state; during (d) waveformthe on-steady of the state; improved (f) DVCCwaveform during of the improved on-oscillation DVCC state; during (e) waveform the on-steady of the state. conventional DVCC during the on-steady state; (f) waveform of the improved DVCC during the on-steady state. In Figure 6, vds is the voltage waveform measured directly at the drain and source of the DUT.In Figure When6 ,thevds DUTis the is in voltage the on waveformstate, vds = v measuredds_on. As shown directly in Figure at the 6 drainc, the conven- and source oftional the DVCC DUT. Whencannot themeasure DUT a is voltage in the less on than state, −1v.ds7 V=, whilevds_on the. As improved shown inDVCC Figure solves6c, the conventionalthis problem ( DVCCsee Figure cannot 6d). measureTable 3 selects a voltage three less measurement than −1.7 V, points, while which the improved are located DVCC solvesat the moments this problem when (see the Figurefirst, second,6d). Table and 3third selects negative three peaks measurement of the drain points,–source which volt- are locatedage of the at DUT the moments occur, to whencompare the the ﬁrst, vds second,(actual value) and third and the negative output peaks voltage of v theout. As drain– sourceshown voltagein Table of3, theduring DUT the occur, on-oscillation to compare state, the thevds max(actual voltage value) measurement and the output relative voltage verrorout. Asof the shown conventional in Table3 DVCC, during can the reach on-oscillation up to 78.8%, state, while the the max error voltage value measurementof the im- relativeproved DVCC error ofis thereduced conventional to less than DVCC 17.6%. can The reach comparison up to 78.8%, results while of vds the(actual error value) value of theand improvedvout during DVCC the on is-steady reduced state to are less shown than 17.6%.in Table The 4, comparisonwhich shows resultsthat the of relativevds (actual value)errors of and thev outon-duringsteady state the on-steadyvoltage measured state are by shown the conventional in Table4, whichDVCC showsand the that im- the relativeproved DVCC errors ofare the both on-steady within 1%. state Furthermore, voltage measured the conduction by the conventionalloss measurement DVCC errors and the improvedof the conventional DVCC are DVCC both withinand the 1%. improved Furthermore, DVCC, the as conductionshown in Table loss 5, measurement are 6.42% and errors of the conventional DVCC and the improved DVCC, as shown in Table5, are 6.42% and

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0.78%, respectively, which proves the high accuracy of the conduction loss measurement of the improved circuit.

Table 3. Comparison of vds and vout during the on-oscillation state.

Time Circuit vds/V vout/V Relative Error Conventional −6.9 −1.7 75.4% T 1 Improved −14.3 −15.3 7.0% Conventional −8.0 −1.7 78.8% T 2 Improved −10.3 −8.5 17.5% Conventional −5.6 −1.7 77.0% T 3 Improved −7.4 −6.1 17.6%

Table 4. Comparison of vds and vout during the on-steady state.

Time Circuit vds/V vout/V Relative Error Conventional 1.710399 1.717680 0.43% T 4 Improved 1.715286 1.724388 0.53% Conventional 1.753108 1.752805 0.02% T 5 Improved 1.752987 1.752228 0.04% Conventional 1.800825 1.800813 0.0007% T 6 Improved 1.800945 1.800930 0.0009% Sensors 2021, 21, x FOR PEER REVIEW 13 of 19

Table 5. Comparison of conduction loss measurement. Table 5. Comparison of conduction loss measurement. Circuit Measure Directly/µJ Measure by DVCC/µJ Relative Error ConventionalCircuit Measure Directly/ 35.733μJ Measure by 38.027 DVCC/μJ Relative 6.42% Error ConventionalImproved 35.733 37.010 38.027 36.721 6.42% 0.78% Improved 37.010 36.721 0.78% To more powerfully illustrate the reduction of conduction loss and on-state voltage measurementTo more error,powerfully simulations illustrate under the reduction different of voltages conduction are supplemented.loss and on-state During voltage the measurement error, simulations under different voltages are supplemented. During the test, the VDC is set to 400 V and 600 V, respectively, and the measurement results are shown intest, Figure the V7.DC is set to 400 V and 600 V, respectively, and the measurement results are shown in Figure 7.

40 40 v v Conventional DVCC ds out vds vout Conventional DVCC 20 20 T T T

(V) 1 3 (V) T1 T2 T3 2 ds ds 0 0 v v vds vout relative error vds vout relative error T −6.55 −1.7 73.59% T −5.3 −1.74 67.42% 1 -20 1 -20 − − − − T2 7.56 1.6 78.31% T2 7.2 1.63 77.33% − − − − T3 4.97 1.6 68.21% T3 4.6 1.59 65.73% -40 -40 11.55 11.60time(μs) 11.65 11.70 11.60time(μs) 11.65 11.70 40 40 v v ds out Improved DVCC vds vout Improved DVCC 20 20 (V) T (V) T ds T T ds 0 1 2 3 0 T T2 3 v

v 1 vds vout relative error vds vout relative error T −11.87 −13.7 15.16% T −11.4 −13.9 21.84% -20 1 -20 1 − − − − T2 9.81 8.02 18.25% T2 9.77 8.75 10.44% − − − − T 6.31 5.11 19.02% T3 6.33 5.65 10.74% -40 3 -40 11.55 11.60 11.65 11.70 11.60 11.65 11.70 time(μs) time(μs)

(a) (b)

FigureFigure 7. v ds7. andvds andvout voutwaveform waveform comparison comparison during during thethe on-oscillationon-oscillation state. ( (aa) )VVDCDC = 400= 400 V; V;(b)( VbDC) V =DC 600= V. 600 V.

The relative error between vds (actual value) and vout during the on-oscillation state is shown in Figure 7. Compared with the conventional DVCC, the measurement relative error of the improved DVCC is significantly reduced. When VDC is 400 V and 600 V, the maximum relative errors are reduced from 78.31% and 77.33% to 19.02% and 21.84%, respectively. Furthermore, by comparing the conduction loss value measured by the conventional DVCC and the improved DVCC, it can be known that when the VDC is 400 V and 600 V, the relative errors are reduced from 6.60% and 6.85% to 1.07% and 1.65%, respectively, which is shown in Table 6.

Table 6. Comparison of conduction loss measurement under different voltages.

Voltage Circuit Measure Directly/μJ Measure by DVCC/μJ Relative Error Conventional 22.40 23.87 6.60% 400 V Improved 23.32 23.07 1.07% Conventional 52.92 56.55 6.85% 600 V Improved 54.52 53.62 1.65%

4.1.2. Qualitative Experimental Verification The comparative experiment of the on-oscillation state voltage measurement is carried out in this section. Under the same working condition, the conventional DVCC and

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The relative error between vds (actual value) and vout during the on-oscillation state is shown in Figure7. Compared with the conventional DVCC, the measurement relative error of the improved DVCC is signiﬁcantly reduced. When VDC is 400 V and 600 V, the maximum relative errors are reduced from 78.31% and 77.33% to 19.02% and 21.84%, respectively. Furthermore, by comparing the conduction loss value measured by the conventional DVCC and the improved DVCC, it can be known that when the VDC is 400 V and 600 V, the relative errors are reduced from 6.60% and 6.85% to 1.07% and 1.65%, respectively, which is shown in Table6.

Table 6. Comparison of conduction loss measurement under different voltages.

Voltage Circuit Measure Directly/µJ Measure by DVCC/µJ Relative Error Conventional 22.40 23.87 6.60% 400 V Improved 23.32 23.07 1.07% Conventional 52.92 56.55 6.85% 600 V Improved 54.52 53.62 1.65%

4.1.2. Qualitative Experimental Veriﬁcation Sensors 2021, 21, x FOR PEER REVIEW 14 of 19 The comparative experiment of the on-oscillation state voltage measurement is carried out in this section. Under the same working condition, the conventional DVCC and improved DVCC are used to measure the on-state voltage of the DUT, respectively. The voltageimproved negative DVCC overshoot are used to measured measure by the the on-sta twote circuits voltage is of compared, the DUT, andrespectively. the result The is shownvoltage in negative Figure8. overshoot measured by the two circuits is compared, and the result is shown in Figure 8.

20 improved DVCC conventional DVCC

VDC=500V 10

(V) 0 out v

-10 −9.3V − -20 20.6V

-30 22.00 22.05 22.10 22.15 22.20 time(μs)

Figure 8. vout waveform comparison during the on-oscillation state. Figure 8. vout waveform comparison during the on-oscillation state.

ItIt can can be be seen seen from from Figure Figure8 8that that compared compared to to the the improved improved DVCC, DVCC, the the drain–source drain–source voltagevoltage negative negative overshoot overshoot measured measured by by the the conventional conventional DVCC DVCC is is signiﬁcantly significantly reduced. reduced. UnderUnder the the testtest voltagevoltage conditions of of 500 500 V, V, th thee measurement measurement result result of of the the voltage voltage negative nega- tiveovershoot overshoot is reduced is reduced by 11.3 by 11.3V, which V, which is consistent is consistent with the with theoretical the theoretical analysis analysis in Section in Section2.2.1 and 2.2.1 the and simulation the simulation verification veriﬁcation in Section in Section 4.2.1. 4.2.1.

4.2.4.2. Working Working Security Security of of Auxiliary Auxiliary Device Device MOSFET MOSFET 4.2.1.4.2.1. Comparison Comparison of of Work Work Security Security of of M M in in Conventional Conventional DVCC DVCC and and Improved Improved DVCC DVCC TheThe experiments experiments are are carried carried out out utilizing utilizing the the test test platform platform shown shown in in Figure Figure4 ,4, with with thethe primary primary circuit circuit (DPTC) (DPTC) operating operating conditions conditions unchanged. unchanged. DueDue to to the the presence presence of of the the gate-shuntgate-shunt capacitance, capacitance, the the gate–source gate–source voltage voltage negative negative overshoot overshoot of of M M may may exceed exceed its its tolerance limit. Therefore, the VDC is set to 400 V to ensure the safety of M. The current tolerance limit. Therefore, the VDC is set to 400V to ensure the safety of M. The current waveform ﬂowing through Vcc and the gate−source voltage waveform of M are shown in waveform flowing through Vcc and the gate−source voltage waveform of M are shown in Figure9. Figure 9.

1.2 20 Improved DVCC Improved DVCC Conventional DVCC Conventional DVCC 0.71A 0.8 10 0.43A 0.4 (V) 0 (A) 2 gs_M

i − v 0.78V 0.0

-10 -0.4 −14.12V -0.8 -20 15.9 16.0 16.1 16.2 16.3 16.4 15.9 16.0 16.1 16.2 16.3 time(μs) time(μs) (a) (b)

Figure 9. The current waveform flowing through Vcc and the gate−source voltage waveform of M. (a) Current waveform; (b) voltage waveform.

The improved DVCC reduces the absolute value of Vgs_M(max) from 14.12 to 0.78 V but increases the max current flowing through Vcc from 0.43 to 0.71 A. As seen, the increase in

Sensors 2021, 21, x FOR PEER REVIEW 14 of 19

improved DVCC are used to measure the on-state voltage of the DUT, respectively. The voltage negative overshoot measured by the two circuits is compared, and the result is shown in Figure 8.

20 improved DVCC conventional DVCC

VDC=500V 10

(V) 0 out v

-10 −9.3V − -20 20.6V

-30 22.00 22.05 22.10 22.15 22.20 time(μs)

Figure 8. vout waveform comparison during the on-oscillation state.

It can be seen from Figure 8 that compared to the improved DVCC, the drain–source voltage negative overshoot measured by the conventional DVCC is significantly reduced. Under the test voltage conditions of 500 V, the measurement result of the voltage negative overshoot is reduced by 11.3 V, which is consistent with the theoretical analysis in Section 2.2.1 and the simulation verification in Section 4.2.1.

4.2. Working Security of Auxiliary Device MOSFET 4.2.1. Comparison of Work Security of M in Conventional DVCC and Improved DVCC The experiments are carried out utilizing the test platform shown in Figure 4, with Sensors 2021, 21, x FOR PEER REVIEW 15 of 20 the primary circuit (DPTC) operating conditions unchanged. Due to the presence of the gate-shunt capacitance, the gate–source voltage negative overshoot of M may exceed its tolerance limit. Therefore, the VDC is set to 400V to ensure the safety of M. The current Sensors 2021, 21, 4285 15 of 19 tolerance limit. Twaveformherefore, flowingthe VDC throughis set to V 400Vcc and to the ensure gate−source the safety voltage of waveformM. The current of M are shown in waveform flowingFigure through 9. Vcc and the gate−source voltage waveform of M are shown in Figure 9.

1.2 20 Improved DVCC Improved DVCC20 1.2 Conventional DVCC Conventional DVCC 0.71A Improved DVCC 0.8 Improved DVCC 10 Conventional DVCC Conventional DVCC 0.8 0.71A 0.43A 0.4 10 (V) 0.43A 0 (A) 2 gs_M

i −

0.4 v 0.78V (V)

0.0 0

(A)

gs_M i

v −0.78V 0.0 -10 -0.4 -10 −14.12V -0.4 -0.8 -20 15.9 16.0 16.1 16.2 16.3 16.4−14.12V15.9 16.0 16.1 16.2 16.3 time(μs) time(μs) -0.8 -20 15.9 16.0 16.1 16.2 16.3 16.4 15.9 16.0 16.1 16.2 16.3 (a) time(μs) (b) time(μs) Figure 9. The current waveform flowing through Vcc and the gate−source voltage waveform of M. (a) Current waveform; Figure 9. The current waveform flowing through V and the gate−source voltage waveform of M. (b) voltage waveform.(a) cc (b) (a) Current waveform; (b) voltage waveform. Figure 9. The current waveform flowing through Vcc and the gate−source voltage waveform of M. (a) Current waveform; (b) voltage waveform. The improved DVCC reduces the absolute value of Vgs_M(max) from 14.12 to 0.78 V but The improved DVCC reduces the absolute value of Vgs_M(max) from 14.12 to 0.78 V but increases the max current flowing through Vcc from 0.43 to 0.71 A. As seen, the increase in increases the max current flowing through Vcc from 0.43 to 0.71 A. As seen, the increase The improved DVCC reduces the absolute value of Vgs_M(max) from 14.12 to 0.78 V but in current can be ignored because it is still far less than the impulse tolerance of the DC increasesvoltage supply. the max However, current flowing according through to the V datasheet,cc from 0.43 the to gate0.71− A.source As seen, withstand the increase voltage in current can be ignored because it is still far less than the impulse tolerance of the DC volt- limit Vgs_limit of M is only −10 V. Therefore, the reduction of Vgs_M(max) from −14.12 to age−0.78 supply. V makes However M out, ofaccording unsafe conditions, to the datasheet, which the significantly gate−source improves withstand the workvoltage security limit Vofgs_limit M. of M is only −10 V. Therefore, the reduction of Vgs_M(max) from −14.12 to −0.78 V makes M out of unsafe conditions, which significantly improves the work security of M. 4.2.2. Work Security of M and Vcc at Higher Voltages 4.2.2. Work Security of M and Vcc at Higher Voltages To study the working safety of Vcc and M in the improved DVCC under higher voltagesTo study (500 the V, 600working V, 700 safety V, 800 of V),Vcc and related M in experiments the improved are DVCC carried under out. higher The circuit volt- agescomponents (500 V, 600 are V, selected 700 V, based800 V) on, related the selection experiments theory are proposed carried out. in this The article circuit to compo- ensure nentsthe safety are selected of the experiments.based on the selection Since the theory target proposed maximum in experimentalthis article to ensure voltage the is safety 800 V, ofV D3theis experiments set to 7.5 V,.V Sincecc is setthe to target 7 V, R maximum2 is selected experimental to 50 Ω, and voltageR3 is selected is 800 V, to V 5D3Ω isfor set the to 7.5experiment. V, Vcc is set The to results7 V, R2 areis selected shown into Figure50 Ω, and10. R3 is selected to 5 Ω for the experiment. The results are shown in Figure 10. 1.2 15 500V 600V 700V 800V 500V 600V 700V 800V V (V) i (A) 0.8 DC 2 10 500  600  700  5

0.4 (V)

800 

(A)

gs_M v

0.0 0 VDC(V) EI1(V) 500 −1.46 600 −1.88 -0.4 -5 700 −2.49 800 −3.57 16.0 16.1 16.2 16.3 16.4 16.00 16.05 16.10 16.15 16.20 time(μs) time(μs) (a) (b)

Figure 10. The current waveform flowing through Vcc and the gate−source voltage waveform of M under higher voltages. Figure 10. The current waveform ﬂowing through Vcc and the gate−source voltage waveform of M under higher voltages. (a) Current waveform; (b) voltage waveform. (a) Current waveform; (b) voltage waveform.

As shown in Figure 10, at higher voltages, the gate–source voltage negative overshoot of M (EI1) is always within the maximum rating of the gate–source voltage of M. In addition, Sensors 2021, 21, 4285 16 of 19

at the moment of turning off, the maximum current ﬂowing through the DC source (Vcc) is about 0.8 A, which is much smaller than the impulse current tolerance of the DC source. Therefore, the improved circuit proposed in this article can still work effectively and safely under high-voltage conditions.

4.3. Selection Method of Vcc and VD3 According to the working principle of the double pulse circuit and the device parameters of the DUT, when the off-state voltage of the DUT is 800 V, the maximum on-state voltage Von_max can reach 3.2 V. Based on the selection mechanism and detailed analyses Sensors 2021, 21, x FOR PEER REVIEWin Section3, set Vcc to 7 V and VD3 to 7.5 V for the experiment. The results are depicted16 of in19 Figure 11.

15 500V 600V 700V 800V 10 5 (V)

gs_M 0 DUT is in the off−state DUT is in the v v =EI -5 gs_M 3 on−state vgs_M=EI2 -10 0 102030time(μs) 5 8 4 7 Vth_M 3 6 (V) (V) 5 gs_M 2 gs_M v v 4 1 Vth_M 3 0 16 18 20 22 22 24 26 time(μs) time(μs)

Figure 11. The gate-source voltage waveform of M under different voltages (Vcc = 7 V, VD3 = 7.5 V). Figure 11. The gate-source voltage waveform of M under different voltages (Vcc = 7 V, VD3 = 7.5 V).

AsAs shownshown inin FigureFigure 1111,, underunder differentdifferent voltages,voltages, whenwhen thethe DUTDUT isis inin thethe onon state,state, itit alwaysalways meetsmeetsEI EI22 >> VVth_Mth_M, ,ensuring ensuring that that M M is is normally normally turned on. When thethe DUTDUT isis inin thethe offoff state,state, itit satisﬁessatisfiesEI EI33< < VVth_Mth_M, ,so so that that M M is is also in thethe offoff state.state. TheThe experimentalexperimental resultsresults proveprove thethe rationalityrationality ofof thethe selectionselection methodmethod ofofV Vcccc and VD3. .

4.4.4.4. SelectionSelection MethodMethod ofof RR22 and R3

AccordingAccording toto EquationsEquations (28)(28) andand (31),(31),R R33 >> 1.521.52 ΩΩ andandR R22 << 5555 ΩΩ whilewhile meetingmeeting SSCSSC andand MEC.MEC. UsingUsing the the controlled controlled variable variable method, method, when whenV ccVcc, V, VD3D3,, andand RR33 are determined,determined, setset RR22 toto 55 ΩΩ,, 10 ΩΩ, 20 ΩΩ, and and 30 30 ΩΩ forfor the the experiments. experiments. Figure 1212aa demonstrates thethe measuredmeasured EIEI11 inin thethe casecase ofof differentdifferentR R22.. Moreover,Moreover, whenwhenR R22 isis determined,determined, setset thethe resistanceresistance of ofR R33to to 55 ΩΩ,, 1010 ΩΩ,, 2020Ω Ω,, andand 30 30Ω Ωfor for the the experiments. experiments.The The variation variation of ofEI EI11 withwithR R33 isis shownshown inin FigureFigure 1212b.b.

(a) (b)

Figure 12. The variation of EI1 with R2 and R3. (a) With R2; (b) with R3.

Sensors 2021, 21, x FOR PEER REVIEW 16 of 19

15 500V 600V 700V 800V 10 5 (V)

Figure 11. The gate-source voltage waveform of M under different voltages (Vcc = 7 V, VD3 = 7.5 V).

As shown in Figure 11, under different voltages, when the DUT is in the on state, it always meets EI2 > Vth_M, ensuring that M is normally turned on. When the DUT is in the off state, it satisfies EI3 < Vth_M, so that M is also in the off state. The experimental results prove the rationality of the selection method of Vcc and VD3.

4.4. Selection Method of R2 and R3

According to Equations (28) and (31), R3 > 1.52 Ω and R2 < 55 Ω while meeting SSC and MEC. Using the controlled variable method, when Vcc, VD3, and R3 are determined, set R2 to 5 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. Figure 12a demonstrates the measured Sensors 2021, 21, 4285 EI1 in the case of different R2. Moreover, when R2 is determined, set the resistance of17 R of3 to 19 5 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. The variation of EI1 with R3 is shown in Figure 12b.

(a) (b)

Sensors 2021, 21, x FOR PEER REVIEWFigure 12. The variation of EI1 with R2 and R3. (a) With R2; (b) with R3. 17 of 19 Figure 12. The variation of EI1 with R2 and R3.(a) With R2;(b) with R3.

As described in Figure 12, EI1 decreases with the increase in R2, and it increases with theAs increasedescribed in inR Figure3. The 12, experimental EI1 decreases results with the effectively increase in verify R2, and the it correctness increases with of the theoreticalthe increase analysis in R3. The indicated experimental in Section results3. When effectively choosing verifyR the2, the correctness resistance of should the theo- be as largeretical as analysis possible indicated while meeting in Section SSC. 3. InWhen contrast, choosing when R2, choosing the resistanceR3, the should resistance be as large should beas as possible small aswhile possible meeting while SSC. completing In contrast, MEC. when choosing R3, the resistance should be as small as possible while completing MEC. 4.5. Error Analysis 4.5. TheError size Analysis of the error in on-state voltage and conduction loss measurement, using the improvedThe size DVCC, of the is error further in on-state analyzed voltage to highlight and conduction the accuracy loss measurement, over different using working the conditions.improved DVCC, Based is on further the circuit analyzed shown to high in Figurelight 5the, the accuracy on-state over voltage different of the working DUT is measuredconditions. by Based the improved on the circuit DVCC shown under in Figu the reVDC 5, theof 300on-state V, 400 voltage V, 500 of V, the 600 DUT V, 700 is V, andmeasured 800 V. Subsequently,by the improved utilizing DVCC under the measured the VDC of on-state 300 V, 400 voltage, V, 500 theV, 600 conduction V, 700 V, and loss is calculated.800 V. Subsequently, Furthermore, utilizing the measurement the measured resultson-state of voltage, improved the conduction DVCC are comparedloss is calcu- with thelated. actual Furthermore, value to get the the measurement relative error, result whichs of isimproved shown in DVCC Figure are 13 compared. with the actual value to get the relative error, which is shown in Figure 13.

30 3.5 Maximun relative error of the 2.0 Relative error of the conduction loss Relative error of the first negative peak measurement measurement in the on-oscillation state on-steady voltage measurement 25 2.8 <2.75% 1.5 <25% <1.7% 2.1 20 1.4

1.0 Relative error(%) Relative error(%)

Relative error(%) 15 0.7 0.5 10 300 400 500 600 700 800 300 400 500 600 700 800 300 400 500 600 700 800 V (V) V (V) V (V) DC DC DC (a) (b) (c)

FigureFigure 13. 13.The The measurementmeasurement relative relative error error of ofimproved improved DVCC. DVCC. (a) Conduction (a) Conduction loss; (b loss;) on-oscillation (b) on-oscillation state voltage; state (c voltage;) on- steady state voltage. (c) on-steady state voltage. It can be seen from Figure 13 that when using the improved DVCC to measure the conduction loss of the DUT, the relative error between the measurement result and the actual value remains below 1.7%. In addition, at the moment of turning on, the measurement relative error of the first negative peak is kept within 25%. Moreover, in the on- steady state, the maximum relative error of the on-steady state voltage measurement is within 2.75%. The above data effectively prove the high measurement accuracy of the improved DVCC.

Sensors 2021, 21, 4285 18 of 19

It can be seen from Figure 13 that when using the improved DVCC to measure the conduction loss of the DUT, the relative error between the measurement result and the actual value remains below 1.7%. In addition, at the moment of turning on, the measurement relative error of the ﬁrst negative peak is kept within 25%. Moreover, in the on-steady state, the maximum relative error of the on-steady state voltage measurement is within 2.75%. The above data effectively prove the high measurement accuracy of the improved DVCC.

5. Conclusions An improved DVCC topology for measuring the conduction loss of power semiconductor devices is proposed and fully characterized in this article. The proposed DVCC, in comparison with the existing designs (conventional DVCC) through simulation and experimentation, shows better accuracy and higher security. During the on-oscillation state, the maximum relative error of the on-state voltage measurement decreased from 78.8% to 17.6%, and the on-state voltage measurement accuracy is greatly improved. Furthermore, the relative error of the total conduction loss measurement of the two on-state stages is reduced from 6.42% to 0.78%, which is one of the critical contributions of the proposed approach. Another key advantage of the improved DVCC is that it improves the working security of M, which is embodied in the reduction of the gate−source voltage negative overshoot of the auxiliary device MOSFET from −14.12 to 0.78 V. In addition, the inﬂuence of component parameters on the circuit performance of the improved DVCC is discussed, and three electrical quantities are extracted as the judgment indicators for the component selection, including the gate−source voltage negative overshoot (Vgs_M(max)) of M, the gate−source voltage vgs_M(on) of M when the DUT is in the on state, and the gate−source voltage vgs_M(off) of M when the DUT is in the off state. Finally, the component selection criteria are given and validated by experimental results. First, the switching speed and blocking voltage level of M should be consistent with or better than the DUT. Second, in the case of meeting VCEW, the breakdown voltage of the Zener diode (D3) should be selected to be a small value. Third, under the conditions of fulﬁlling MEC and SSC, the selection guide for these two resistors is to increase R2 and decrease R3 as much as possible.

Author Contributions: Conceptualization, Q.Y., Z.Z., P.S., and B.Z.; methodology, Q.Y.; software, Q.Y. and Z.Z.; validation, Q.Y., P.S., and Z.Z.; formal analysis, Q.Y. and Y.C.; investigation, Q.Y.; resources, Q.Y.; data curation, B.Z.; writing—original draft preparation, Q.Y. and P.S.; writing—review and editing, Q.Y.; visualization, Z.Z.; supervision, B.Z.; project administration, Q.Y., and P.S.; funding acquisition, Z.Z. All authors have read and agreed to the published version of the manuscript. Funding: This work was supported by State Grid science and technology projects (Electrical characterization and screening method of press-pack IGBT chip (grant no. 5455GB190007). Institutional Review Board Statement: Not applicable. Informed Consent Statement: Not applicable. Data Availability Statement: The data used for the manuscript are available for researchers on request. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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