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Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Datasheet – Volume 1 of 2 March 2020 Document Number: 332690-006EN You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel technologies may require enabled hardware, specific software, or services activation. Check with your system manufacturer or retailer. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. Warning: Altering PC clock or memory frequency and/or voltage may (i) reduce system stability and use life of the system, memory and processor; (ii) cause the processor and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat or other damage; and (v) affect system data integrity. Intel assumes no responsibility that the memory, included if used with altered clock frequencies and/or voltages, will be fit for any particular purpose. Check with memory manufacturer for warranty and additional details. Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user. I2C is a two-wire communications bus/protocol developed by NXP. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including NXP Semiconductors N.V. Intel® Active Management Technology (Intel® AMT) requires activation and a system with a corporate network connection, an Intel® AMT-enabled chipset, network hardware and software. For notebooks, Intel AMT may be unavailable or limited over a host OS-based VPN, when connecting wirelessly, on battery power, sleeping, hibernating or powered off. Results dependent upon hardware, setup & configuration. For more information, visit http://www.intel.com/technology/platform-technology/intel-amt Intel® High Definition Audio (Intel® HD Audio) Requires an Intel® HD Audio enabled system. Consult your PC manufacturer for more information. Sound quality will depend on equipment and actual implementation. For more information about Intel HD Audio, visit http://www.intel.com/design/chipsets/hdaudio.htm. Intel® Rapid Storage Technology (Intel® RST) requires a select Intel® processor, enabled chipset, and Intel® Rapid Storage Technology (Intel® RST) software. Intel® Smart Response Technology requires a Intel® Core™ processor, select Intel® chipset, Intel® Rapid Storage Technology software version 12.5 or higher, and a solid state hybrid drive reporting at least 16GB capacity and supporting SATA-IO hybrid information feature. Depending on system configuration, your results may vary. Contact your system manufacturer for more information. No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible Measured Launched Environment (MLE). Intel TXT also requires the system to contain a TPM v1.s. For more information, visit http://www.intel.com/technology/security. Intel® Virtualization Technology requires a computer system with an enabled Intel processor, BIOS, virtual machine monitor (VMM). Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all operating systems. Consult your PC manufacturer. For more information, visit http:// www.intel.com/go/virtualization Intel, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2016 - 2020, Intel Corporation 2 Datasheet, Volume 1 Contents 1Introduction............................................................................................................ 23 1.1 About this Manual ............................................................................................. 23 1.2 References ....................................................................................................... 23 1.3 Overview ......................................................................................................... 23 1.4 PCH SKUs ........................................................................................................ 25 2 PCH Controller Device IDs ....................................................................................... 27 2.1 Device and Revision ID Table .............................................................................. 27 3 Flexible I/O............................................................................................................. 32 3.1 Acronyms......................................................................................................... 32 3.2 References ....................................................................................................... 32 3.3 Overview ......................................................................................................... 32 3.4 Description....................................................................................................... 32 3.4.1 PCH-H Flexible I/O ................................................................................. 33 3.5 HSIO Port Selection ........................................................................................... 34 3.5.1 PCIe/SATA Port Selection ........................................................................ 34 4Memory Mapping..................................................................................................... 35 4.1 Overview ......................................................................................................... 35 4.2 Functional Description........................................................................................ 35 4.2.1 PCI Devices and Functions....................................................................... 35 4.2.2 Fixed I/O Address Ranges ....................................................................... 36 4.2.3 Variable I/O Decode Ranges .................................................................... 38 4.3 Memory Map..................................................................................................... 39 4.3.1 Boot Block Update Scheme ...................................................................... 41 5 System Management ............................................................................................... 43 5.1 Acronyms......................................................................................................... 43 5.2 References ....................................................................................................... 43 5.3 Overview ......................................................................................................... 43 5.4 Features .......................................................................................................... 43 5.4.1 Theory of Operation................................................................................ 44 5.4.1.1 Detecting a System Lockup ........................................................ 44 5.4.1.2 Handling an Intruder ................................................................. 44 5.4.1.3 Detecting Improper Flash Programming ....................................... 44 5.4.2 TCO Modes............................................................................................ 45 5.4.2.1 TCO Compatible Mode ............................................................... 45 5.4.2.2 Advanced TCO Mode ................................................................. 46 6 High Precision Event Timer (HPET).......................................................................... 47 6.1 References ....................................................................................................... 47 6.2 Overview ......................................................................................................... 47 6.2.1 Timer Accuracy ...................................................................................... 47 6.2.2 Timer Off-load ....................................................................................... 48 6.2.3 Off-loadable Timer.................................................................................. 48 6.2.4 Interrupt Mapping .................................................................................
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