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Digital Pixel Image Sensors with Linear and Wide-Dynamic-Range Response Developed by Pixel-Wise 3-D Integration

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Digital Pixel Image Sensors with Linear and Wide-Dynamic-Range Response Developed by Pixel-Wise 3-D Integration R05 Digital Pixel Image Sensors with Linear and Wide-Dynamic-Range Response Developed by Pixel-Wise 3-D Integration Masahide Goto1, Yuki Honda1, Toshihisa Watabe1, Kei Hagiwara1, Masakazu Nanba1, Yoshinori Iguchi1, Takuya Saraya2, Masaharu Kobayashi2, Eiji Higurashi3, Hiroshi Toshiyoshi2, and Toshiro Hiramoto2 1 NHK Science and Technology Research Laboratories, 1-10-11 Kinuta, Setagaya-ku, Tokyo 157-8510, Japan, Tel: +81-3-5494-3224, Fax: +81-3-5494-3278, Email: [email protected], 2 The University of Tokyo, Tokyo, Japan, 3 National Institute of Advanced Industrial Science and Technology, Ibaraki, Japan. Abstract resolution. To solve the problem, we have developed We report a digital pixel image sensor developed a pixel-parallel 3-D integrated image sensor as by using pixel-wise 3-D integration technology. The shown in Fig. 1 [5-8], which achieves both wide pulse-frequency modulation (PFM) analog-to-digital dynamic range and high resolution. converter (ADC) provides in-pixel digital output, Column-parallel which overcomes signal saturation due to the well signal processing capacity of a photodiode (PD). We have designed a Photodetector Pixel CMOS image sensor (CIS)-type PFM-ADC suitable for pixels with a pinned PD. PDs, logic circuits, and counters were integrated into two silicon-on- insulator (SOI) layers via hybrid bonding using 5- Signal processor μm-diameter Au electrodes. The developed sensor Conventional 2-D image sensor exhibited a linear and wide dynamic range response ranging more than 96 dB, demonstrating the high- Pixel Pixel-parallel Photodetector fidelity image sensing. We also have developed signal processing triple-layer technology to further reduce the pixel footprint. Introduction The importance of CIS has increased with the Stack development of image input devices for the Internet- SOI layers Signal processor of-Things era. Conventional CIS limits its dynamic Pixel-parallel 3-D Integrated image sensor range to approximately 60–70 dB [1] owing to the PD well capacity. Moreover, recent trends of Figure 1: Pixel-parallel 3-D integrated image sensor shrinking pixels [2] further reduce the dynamic compared with the conventional 2-D image sensor. range. Pixel-level image sensing with PFM-ADC is a promising candidate for enhancing the dynamic Design and Implementation range without PD saturation [3-4]. However, the Figure 2 shows the newly designed CIS-type PFM- large area of pulse counters degraded sensor ADC. The transfer gate is switched ON during the charge storage period and OFF during the reset period for the floating diffusion (FD) to keep the PD & logic array potential gradient between the PD and the FD. Logic circuits provides event-driven operation, which generates triggers for TG and RST by a pulse output Pixel-wise signal. Figure 3 shows a schematic of the sensor. interconnects The upper PD and the logic array are developed by CIS process. The lower 16-bit counter array is by fully-depleted SOI process. All pixels are 16 bit interconnected with Au electrodes via Au/SiO2 Vertical scanner 16-bit counter array hybrid bonding. Photographs of the developed Horizontal sensor are shown in Fig. 4, which confirms 1-μm- scanner alignment accuracy. (a) VRST PD FD Logic NOR Delay P N Reset Upper layer P+ (RST) Pulse Au Transfer gate NAND (TG) Lower V FD - layer Pinned Counter 16-bit counter PD + FD VOUT Comparator VTH (b) (a) Figure 3: (a) Schematic of the 3-D integrated sensor and (b) cross-sectional diagram of the pixel. VOUT VFD Upper layer Lower layer 4 Pixel Pixel V 2 RST Voltage (V) Voltage VTH 100 μm 100 μm 0 0 4 8 12 16 Time (s) Before bonding Upper layer Upper 4 PD VOUT 0 Voltage (V) Au 4 TG SiO 0 2 Lower layer Lower RST 4 0 0 20 40 60 80 100 Time (s) 5 µm Counter Cross-sectional interface of bonded chip (b) Figure 2: (a) Circuit diagram and (b) simulation results Figure 4: Photographs of the developed sensor. for CIS type PFM-ADC. Measurement Results and Discussion Figure 5 shows the measured output of the sensor as a function of the illuminance. We confirmed an excellent linearity and a wide dynamic range of 96 dB as shown in Fig. 5 (a), which corresponds to the in-pixel 16-bit counter. The response was also examined using an off-chip 20-bit counter, showing a wider dynamic range of 120 dB as shown in Fig. 5 (c)犬丸りん・NHK・NEP (b). Figure 6 shows captured images. Figure 6 (a) shows a 256-gradation image from the lower 8-bit (a) signals, whereas Fig. 6 (b) is from the higher eight bits. Figure 6 (c) shows a 256-gradation image composed from the above two images after histogram equalization, thereby demonstrating the ability for capturing the full range of illuminance. 105 104 (c)犬丸りん・NHK・NEP 3 10 (b) 102 1 Pulse frequency (Hz) frequency Pulse 10 1 10-1 1 101 102 103 104 Illuminance (lx) (a) 106 105 (c)犬丸りん・NHK・NEP 104 (c) 103 Figure 6: Examples of captured images. (a) Image from lower 8 bits. (b) Image from higher 8 102 bits. (c) Composed image after histogram equalization. Pulse frequency (Hz) frequency Pulse 101 The SOI-based 3-D integration can increase the 1 10-1 1 101 102 103 104 105 number of stacked layers to increase the resolution Illuminance (lx) and to improve multifunctionality. We are now (b) developing triple-layer sensors, wherein 16-bit Figure 5: Measured output of the developed sensor by counters are separated into two layers, whose using (a) in-pixel counter and (b) off-chip counter. schematic and simulation results are shown in Fig. 7. a wide dynamic range of more than 96 dB. The VRST sensor is promising for next-generation video Pulse systems because it can capture precise information in the real world. Light 1~8 bit 9~16 bit counter counter References PD [1] J. Ohta, Smart CMOS Image Sensors and Upper Middle Lower Applications. Boca Raton, FL, USA: CRC Press, 2007, pp. 187–188. Pulse [2] P. Chou et al., “A 1.1μm-Pitch 13.5Mpixel 3D- Stacked CMOS Image Sensor Featuring 230fps Upper Full-High-Definition and 514fps High- Comp. Definition Videos by Reading 2 or 3 Rows Pulse PD Simultaneously Using a Column-Switching signal Matrix,” in IEEE Int. Solid-State Circuits Conf. Middle Dig. Tech. Papers (ISSCC), pp. 88–90, Feb. Carry from 2018. 8th bit Lower 8bit [3] W. Yang, “A Wide-Dynamic-Range, Low- Lower counter Power Photosensor Array,” in IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers (ISSCC), pp. 230–231, Feb. 1994. Upper 8bit [4] F. Andoh, H. Shimamoto, and Y. Fujita, “A counter Digital Pixel Image Sensor for Real-Time (a) Readout,” IEEE Trans. Electron Devices, vol. VFD 2V 47, no. 11, pp. 2123–2127, 2000. [5] M. Goto et al., “Three-Dimensional Integrated 0 CMOS Image Sensors with Pixel-Parallel A/D Upper Pulse 2V Converters Fabricated by Direct Bonding of SOI Layers,” in IEEE Int. Electron Devices Meeting 0 0 2μs 4μs 6μs 8μs (IEDM) Tech. Dig., Dec. 2014, pp. 4.2.1–4.2.4. Counter 1 bit [6] M. Goto et al., “A Three-Dimensional 2V Integration Technology with Embedded Au Middle Electrodes for stacked CMOS Image Sensors,” 0 0 2μs 4μs 6μs 8μs in Proc. 2015 Int. Image Sensor Workshop (IISW), 2015, pp. 48–50. Counter 16 bit [7] M. Goto et al., “Quarter Video Graphics Array 2V Lower Full-Digital Image Sensing with Wide Dynamic 0 Range and Linear Output Using Pixel-Wise 3D 0 20ms 40ms 60ms Integration,” in IEEE Int. Symp. Circuits and (b) Systems Dig. Tech. Papers (ISCAS), pp. 1–4, Figure 7: (a) Schematic and (b) simulation results 2018. of pixel for the triple-layer sensor. [8] M. Goto et al., “Quarter Video Graphics Array Digital Pixel Image Sensing With a Linear and Conclusion Wide-Dynamic-Range Response by Using Pixel-Wise 3-D Integration,” IEEE Trans. We developed digital pixel image sensor by using Electron Devices, vol. 66, no. 2, pp. 969–975, in-pixel PFM-ADCs and pixel-wise 3D integration. 2019. Measurement results demonstrated both linearity and .
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