ALGORITHMS FOR TEST GENERATION AND
FAULT SIMULATION OF PATH DELAY FAULTS IN
LOGIC CIRCUITS
A Thesis
Submitted For the Degree of
Doctor of Philosophy
in the Faculty of Engineering
by
ANANTA KUMAR MAJHI
Department of Electrical Communication Engineering
INDIAN INSTITUTE OF SCIENCE
BANGALORE INDIA
NOVEMBER
To Bhai
Perfection is the goal of human life but human e orts are limited Happiness does not
come merely through human endeavour but comes through grace Blessed are those who
have the grace of both God and master
Swami Rama
i
Acknowledgments
It gives me immense pleasure to sincerely thank every one who help ed me in various
ways to complete this dissertation First and foremost I bow b efore the Lord Almighty
with a grateful heart for His blessings which have made me what Iam
I express my deep sense of gratitude to my research sup ervisor Dr James Jacob of
the ECE Department He has b een an excellent teacher counseller and guide to me and
has given me continual encouragement and wise guidance throughout the course of my
research work I am also indebted to him and his family for their p ersonal care love and
understanding during many di cult times
heartfelt gratitude to my research co sup ervisor Prof L M
I place on record my
Patnaik of the CSA Department for his encouragement moral supp ort and valuable
suggestions I am obliged to him not only for providing the computing facilities in Micro
pro cessor Applications Lab oratory but also for his p ersonal care and fatherly guidance
which will always b e rememb ered and treasured by me
My heartfelt thanks to Dr Vishwani D Agrawal of the AT T Bell Labs USA
for acting as an uno cial research co sup ervisor by always being there for me with his
and encouragement during the entire course valuable advice suggestions keen interest
of this work His comments and suggestions have greatly help ed me in improving my
thinking presenting and writing skills I thank him also for providing me the most recent
pre prints and publications and for having gone through the entire manuscript
I would like to thank Prof V U Reddy past Chairman and Prof A Selvara jan
present Chairman of the ECE Department and Prof N Balakrishnan the Chairman of
SERC for providing the nancial assistance and necessary computing facilities for my
edavathy for allowing researchwork Imust also thank Prof A Kumar and Prof T S V
me to use their lab oratory facilities during the initial period of my research career and
also for their love and concern over the years
I have greatly b ene ted by the scholarly advice and suggestions from Dr M K
Srinivas Rutgers Univ USA Pradip Mandal Jacob Augustine and P R Sureshkumar
ii
I thank them for their friendship and encouragement during my research work I would
also like to thank Dr Srinivas Patil Dr Ankan Pramanick Dr Ira Pramanick and Dr
L N Reddy all of IBM USA and Keerthi Heragu of Univ of Illinois USA for providing
me copies of their theses and recent publications in the area of my work
I ISc has b een a stimulating environment esp ecially b ecause of myloving friends Ani
mesh Ratikanta Lo chan Purna Mano j Prasant Saro j Barada Krutibas Himansu Ni
ra j Venkatesh Ra jendra Raghu Pradipta Dillip Pratap Chidananda Subhra Radha
Gowri Nanda Namita Shorey Prem Sai Mala and others They have truly shared
my life enjoyable during my stay on the campus My many a lighter moment and made
sp ecial thanks to Animesh for being always with me in pain and pleasure and sharing
my feelings at my monotonous moments
I am esp ecially grateful to Biswa jit Biswamohan Moharana and family Ra jesh and
family Rout and family for their love and concern as a younger brother and for making
my stay comfortable in Bangalore Uninvited app earances in their houses on various
o ccasions will always be remembered by me
It is my pleasure to thank Chandramouli Mahadevan Pro ject Manager Pro duct
Division Texas Instruments India Bangalore for his kind help and un Engineering
derstanding during the nal phase of the work Life is always cheerful in TI I due to
friends like Bala jee SriVidhya Debaleena Baskar Swagata Swathi Vinayak Sara ja
RSR Palani and Prakash The nancial assistance from Texas Instruments India for
printing and xeroxing the nal manuscript is greatly acknowledged
Finally words cannot express my feelings of gratitude to my beloved mother uncle
their unwavering encouragement moral supp ort and sac and other family members for
ri ce without which this work would not have been completed Their love and blessings
were a p erp etual source of inspiration to me
Ananta
iii
Abstract
Ascertaining correct op eration of digital logic circuits requires veri cation of functional
behavior as well as correct op eration at desired clo ckspeed The maximum allowable clo ck
rate in a digital circuit is determined by the propagation delays of the combinational logic
network b etween latches If the delay of the manufactured network exceeds sp eci cations
due to some physical defects or pro cess variations unstabilized and p ossibly incorrect logic
values maybelatched in memory elements Delay fault testing can b e used to ensure that
manufactured digital circuits meet their timing sp eci cations In this thesis we present
novel and e cient algorithms for test generation and fault simulation of path delay faults
in combinational logic circuits
We have develop ed a novel delay fault simulator for combinational logic circuits
both robust and nonrobust tests for path which is capable of simultaneously analyzing
delay faults Only a simple binary logic is used instead of the multi valued algebra as
is used in most existing simulators A rule based approach is develop ed to identify all
robust and nonrobust paths tested byatwo pattern test while backtracing from primary
outputs to primary inputs in a depth rst manner Rules identify probable glitches as
they propagate through the circuit and thus determine when a test b ecomes nonrobust
Exp erimental results for benchmark circuits determine the p erformance of the simulator
For coverage all path delay faults are for deterministic as well as random test vectors
implicitly considered
We have also develop ed an e cient automatic test generation algorithm for path
delay faults in combinational circuits To facilitate simultaneous consideration of robust
and nonrobust tests we employ a value logic system Once a robust test is found
for a path with a given transition our algorithm derives another test for the opp osite
transition with minimal extra e ort The derived test in most cases is either a robust or
ktrace pro cedure is employed nonrobust test for the same path An e cient multiple bac
for satisfying the test generation ob jectives A path selection metho d is prop osed which
covers all lines in the logic circuit by the longest as well as the shortest p ossible paths
iv
through them The fault simulator integrated with the test generation system gives
information on robust and nonrobust detection of faults either from a given target set
or all path faults Exp erimental results on several b enchmark circuits substantiate the
e ciency of our algorithm A comparison with other published results is given
We prop ose a new coverage metric and a two pass test generation metho d for delay
faults in combinational circuits The coverage metric termed as line delay fault coverage
on paths passing through each line in the circuit one for the considers two delay faults
rising transition and the other for the falling transition However the test criterion is
di erent from that of the slow to rise and slow to fall transition faults The new test
called line delay test is a path delay test for the longest robustly testable path pro ducing
a given transition on the target line The maximum numb er of tests and faults is limited
to twice the number of lines Using a two pass test generation pro cedure we b egin with
a minimal set of longest paths covering all lines and generate tests for them Fault
the line delay fault coverage The second pass considers simulation is used to determine
those lines for which line delay tests could not b e generated in the rst pass and attempts
to generate robust tests for successively shorter paths through these lines until a test for
the longest robustly testable path is found We present a theorem stating that a redundant
stuck at fault makes all path delay faults involving that faulty line untestable for either
a rising or falling transition dep ending on the typ e of the stuck at fault The use of this
theorem considerably reduces the e ort of delay test generation An implementation of
our algorithm achieved very high line delay coverage e ciency for most of the
benchmark circuits
We hop e that the novel ideas and algorithms prop osed in this thesis will nd appli
cation in the development of e cient CAD to ols for delay fault testing and simulation
of real life VLSI circuits The new delay fault coverage metric has the advantages of
reduced complexity and high coverage e ciency We discuss its limitations with resp ect
to the conventional path delay fault mo del Future exp erimental work should establish
the validity of our fault coverage metric
Contents
Intro duction
Design and Test of Integrated Circuits
DelayFault Testing
Why Delay Fault Testing
Contribution of the Thesis
Organization of the Thesis
Prior Work
DelayFault Mo dels
Transition Fault Mo del
Gate Delay Fault Mo del
Path DelayFault Mo del
Prior Work on Path DelayFault Simulation
Path DelayFault Simulation by Logic Value Propagation
Parallel Pattern Fault Simulation of Path DelayFaults
Non Enumerative Estimation of Path DelayFault Coverage
Fault Coverage Estimation by Test Vector Sampling
Delay Fault Coverage Estimation by Selective Path Search
Exact Path DelayFault Coverage Estimation
SPADES A Path DelayFault Simulator for Sequential Circuits
Prior Work on Test Generation for Path DelayFaults v
vi Contents
Test Generation for Path DelayFaults Using PODEM
DYNAMITE
DelayFault Testing Using Bo olean Expressions
NEST Non Enumerative Test Generation Metho d for Path Delay
Faults
Compact DelayTests by Multiple Path Activation
RESIST Recursive Test Generation for Path Delay Faults
Test Generation for Path DelayFaults in Non Scan Sequential Circuits
Conclusion
Path Delay Fault Simulation Using Binary Logic
Intro duction
Theoretical Background and Basic De nitions
Hardware Mo del and Clo ck Timings
Robust and Nonrobust Paths
Sensitivity and Gate Evaluation
Path Delay Fault Simulation Using Binary Logic
Glitch Generation and Propagation
Glitch Generation
Glitch Propagation
Backtracing for Robust and Nonrobust Paths
aluating the Inputs of a Robust Gate Rules for Ev
Rules for Evaluating the Inputs of a Nonrobust Gate
Rule for Evaluating the Input of an IS Gate
Simulation Results
Conclusion
An E cient Automatic Test Generation System for Path Delay Faults
in Combinational Circuits
Intro duction
vii
A Value Logic System
Derivation of Value Logic
Path Selection
Test Generation
Pro cedure for Test Generation
Robust Nonrobust Test for Opp osite Transition
Exp erimental Benchmark Results
Conclusion
Line Delay Fault Mo del and Its Coverage
Intro duction
Line DelayTests and Coverage Metric
Two Pass Test Generation
N Longest Path Selection
Elimination of Untestable Path Faults
Exp erimental Results
Limitations of the Fault Mo del
Conclusion
Conclusions
Summary of Work Presented
Future Work
Bibliography
Good manners without sincerity are like a beautiful dead lady Straightforwardness
without civility is like a surgeon s knife e ective but unpleasant Candour with courtsey
is helpful and admirable
Sri Yukteswar
List of Figures
Hardware mo del and clo ck timings
Example of a fault that requires knowledge of circuit delays
Example of robust and nonrobust tests
Examples of robust and nonrobust paths
aluation of gate sensitivity CO and NC inputs Ev
Glitch generation
Examples of glitch generation
Glitch propagation
Example illustrating glitch generation and propagation
Robust and nonrobust inputs of a robust gate
Nonrobust inputs of a nonrobust gate
Example of robustly and nonrobustly tested paths
Prop osed value logic
Examples of glitch generation
Glitch causing a nonrobust test
Example of path selection
Example of con ict at a stem
Pseudo co de for the test generation algorithm
Test generation Example
Derivation of test for opp osite transition Example ix
x List of Figures
Nonrobust test derived from robust test Example
Test generation for longest path through line
Test generation for second longest path through line
Elimination of untestable path delay faults
Limitation of the fault mo del
List of Tables
Numberofpossiblephysical paths PIs POs and levels
Test generation results
Path delay fault simulation results
Overall statistics
Path delay fault simulation results for ISCAS circuits
Enumeration of logic states
Signal value representation
Longest path selection
Delaytest results for ISCAS b enchmarks
Comparison with other results
of ISCAS b enchmarks Test results for scan hold versions
Two pass test generation results for ISCAS b enchmark circuits
Statistics for line delayfaulte ciency xi
By three methods we may learn wisdom First by re ection which is noblest second by
imitation which is easiest and third by experience which is the bitterest
Confucius
Chapter
Intro duction
The primary ob jective of this thesis is to develop e cient algorithms for test generation
and fault simulation of path delay faults in combinational logic circuits We present a
novel path delay fault simulator using binary logic rather than using the multi valued
logic as presented in most of the literature An e cient automatic test generation system
for path delay faults in combinational logic circuits is develop ed which employs a new
value logic system for generating robust and nonrobust tests simultaneously A new
fault coverage is prop osed for path delay faults and a coverage metric called line delay
two pass test generation metho d is develop ed to obtain almost line delay coverage
e ciency
In this chapter we provide a brief background of design and test of integrated cir
cuits and the motivation for the research rep orted in this thesis Ma jor contributions
of the thesis are summarized and the organization of the thesis is outlined at the end of
this chapter
Design and Test of Integrated Circuits
Rapid advances in integrated circuit technology have made it p ossible to fabricate digital
hip Very Large Scale Integration circuits with a very large numb er of devices on a single c
VLSI is the fabrication of millions of comp onents and interconnections at once by a
Chapter Intro duction
common set of manufacturing steps Its advantages are reduced system cost b etter
p erformance and greater reliability These advantages would b e lost unless VLSI devices
can be economically tested The testing pro cess detects the physical defects pro duced
during fabrication of a VLSI chip Testing is an exp eriment in which the system under
test is exercised and its resulting resp onse is analyzed to ascertain the correct b ehavior
If an incorrect behavior is detected the second goal of the testing exp eriment may be
of misb ehavior Diagnosis assumes knowledge of the to diagnose or to lo cate the cause
internal structure of the system under test
Manufacturing of a pro duct consists of fabrication and testing Design and test
development precede manufacture While design is a synthesis of manufacturable details
test development sp eci es the test data and details of the testing pro cedure Design links
the abstract sp eci cations to the physical device through a synthesis or assembly of known
parts and generates data necessary to drive the equipment that physically pro duces the
assembly Veri cation consisting of analysis and simulation checks correctness of the
design The correctness of the fabricated device is determined through testing Thus in
design and test data are necessary order to pro duce a correctly working device both
In any IC manufacturing pro cess physical defects are almost invariably intro duced
No manufacturing pro cess can guarantee yield and therefore some circuits are
bound to have defects Typical defects include shorts b etween lines breaks in conducting
paths missing devices pinholes in the oxide layer threshold voltage shift due to ionic
contamination or improp er doping surface defects due to dust particles etc The typ es
and quantity of defects dep end on the variability of pro cess parameters In general the
chip area the greater is the chance of having a defect larger the circuit is in terms of
It is necessary to separate the bad circuits from the good ones during pro duction as
well as during op eration From an economic viewp oint the cost of identifying a faulty
comp onent during its life cycle is lowest b efore it is packaged This cost increases rapidly
as the comp onent becomes a part of larger and larger systems Therefore testing is a
very imp ortant asp ect of any VLSI manufacturing system
The testing pro cess involves the application of a sequence of input stimuli known as
Chapter Intro duction
test vectors to the circuit and a comparison of the circuit resp onse with a pre computed
exp ected resp onse Test vectors are applied to the circuit using an automatic test equip
ment ATE Any discrepancy in the output resp onse indicates the presence of a fault
The faults in digital circuits can be classi ed as logic or parametric faults A logic fault
is one which causes the logic function of the circuit on an output signal to b e changed to
some incorrect function Parametric faults alter the magnitude of the circuit parameters
causing changes in sp eed of op eration or the levels of currents and voltages In this thesis
we fo cus only on one typ e of parametric faults particularly delay faults which can cause
failures in a circuit timing related
Test Generation for a VLSI device involves the generation of test vectors to detect
failures An imp ortant issue is the fault model used in test generation Physical defects
are often mo deled as logic faults This makes the problem of fault analysis indep endentof
the technology In addition tests derived for logic faults may b e useful for manyphysical
faults whose e ect on the circuit b ehavior is not well understo o d or is to o complex to b e
analyzed The main requirement for the fault mo del is that the mo del should capture
the change in functionality caused by most of the commonly o ccurring physical defects in
the circuit Also the complexity of test generation dep ends on the fault mo del and the
west level for a VLSI device is the layout Test generation circuit representation The lo
complexity for faults in the geometrical structure at this level is very high However it is
p ossible to consider actual defects like shorts and bridging between conductors On the
other hand the test generation complexityisreducedifwe mo del faults at the logic gate
or even higher Bo olean function levels The fault mo del at these levels may not always
be a true representation of the physical defects Realistic and higher level fault mo dels
are imp ortant areas of research Some popular fault mo dels targeted by automatic test
ation ATPG are the stuck at fault mo del the bridging fault mo del the pattern gener
CMOS stuck open fault mo del and various delay fault mo dels It is p ossible that more
than one fault o ccur in a circuit However the single fault assumption is p opular as the
total number of multiple faults in a circuit is to o large to be considered explicitly and
tests generated for single faults frequently detect a large numbers of multiple faults As
Chapter Intro duction
di erent fault mo dels represent di erentphysical defects it may b e necessary to p erform
test generation for various fault mo dels and derive tests in order to maximize the pro duct
reliability
A normal requirement for test vectors is that they detect avery high fraction of the
mo deled faults The detected fraction of the faults is called the fault coverage and it
is determined by the pro cess of fault simulation Fault simulation involves nding the
fault free output resp onse and the set of mo deled faults that pro duce a resp onse di erent
from the fault free resp onse Fault simulation is widely employed to grade the quality
up ATPG by avoiding test generation for of a given set of tests and is useful to sp eed
those faults already detected by a generated test Fault simulation is also useful for the
construction of fault dictionaries which help in fault diagnosis A variety of techniques
for fault simulation have been develop ed
Delay Fault Testing
Ascertaining correct op eration of digital logic circuits requires veri cation of functional
behavior as well as correct op eration at the rated clo ck sp eed Research on metho ds to
mo del failures that a ect functional b ehavior and metho ds to detect these mo deled faults
wever it is equally imp ortant to insure that the has been extensively rep orted Ho
manufactured circuits meet their timing sp eci cations The maximum allowable clo ck
rate in a digital circuit is determined by the propagation delays of the combinational
logic network between the latches If the delay of the manufactured network exceeds
sp eci cations unstabilized and p ossibly incorrect logic values may b e latched in ip ops
or pro duced at outputs Failures causing logic circuits to malfunction at desired clo ck
h rates or not meet timing sp eci cations are currently receiving much attention Suc
failures are mo deled as delay faults The ob jective of delay testing is to guarantee that
the circuit op erates without any malfunction at the sp eci ed clo ckrate The use of delay
fault mo dels in VLSI test generation is currently gaining acceptance in the industry
Recent studies at IBM have shown that the application of a delay fault tests can raise the
Chapter Intro duction
SPQL Shipped Parts Quality Level by an order of magnitude
Why Delay Fault Testing
Digital system designers have traditionally maximized the frequency of system clo cks in
order to obtain the highest p erformance from a hardware unit The maximum allowable
clo ck rates are determined by the propagation delays of the combinational logic network
between latches A change in the logic value at any network primary input PI may
through the network to the primary output PO propagate along one or more paths
Consider the circuit under test shown in Figure Let DP be the propagation delay
i
asso ciated with any path i in the logic network
1 0
OUTPUT 0 1 INPUT LATCH LATCH 1 1
0 0
V2 V1 COMBINATIONAL LOGIC BLOCK C1 C2
Clock C1 Tt
Clock C2
t Tc t t 0 1 2
V1 is Loaded V2 is loaded Output is sampled
Figure Hardware mo del and clo ck timings
Chapter Intro duction
In practice logic designers must calculate the maximum path delay DP in order
max
to sp ecify a clo cking rate In Figure during the normal op eration of the circuit
the input clo ck C is the same as the output clo ck C and the p erio d T of C and
c
C corresp onds to the system clo ck This period should be greater than the maximum
y propagation delay of any path DP in the circuit However during testing for dela
max
faults we use two separate test clo cks C and C running at the same frequency but
at a sp eed slower than the normal system clo ck Thus the period of test clo cks T is
t
longer than T The two test clo cks are skewed by the amount T The activation of
c c
the output clo ck C must follow the activation of the input clo ck C by at least DP
max
time units i e T t t DP If the output clo ck is activated so oner then
c max
unstabilized and possibly incorrect logic values may be latched at the output latches
When the logic network is manufactured the actual gate delays may not conform to
manufacturing sp eci cations Due to delay faults the actual DP of a manufactured
max
network can exceed the DP predicted by the logic designer As the clo cking rate is
max
the faultynetwork may not op erate correctly Since delay based on the predicted DP
max
faults do not alter the logic function realized by a circuit and since the tests for stuck at
faults are normally applied at a slow clo ck rate they are inadequate for detecting delay
faults Sp ecial two pattern test vectors are required for detecting delay faults
The hardware mo del used in delay fault testing has been shown in Figure Here
the vector pair V V constitutes a delay test and signals C and C are used to
hes resp ectively At time t an initializing input vector clo ck the input and output latc
V is applied and the circuit is allowed to stabilize under input V At time t the
propagation vector V is applied and the outputs are sampled at time t where t t
is the intended time interval b etween the input and output clo cks called the clo ck p erio d
or clo ck interval T
c
For verifying that the circuit meets timing requirements we must exhaustively test
under the ab ove condition for all pattern pairs i e apply all pairs of inputs V V
and verify that the exp ected values under V are always obtained at the output latches
at time t However for the circuits having n inputs the total number of pattern pairs
Chapter Intro duction
n n n
required will be which is of the order This will be an astronomical
number even for mo derately large values of n inputs Thus exhaustive testing is quite
impractical for delay faults Hence one has to derive suitable and reasonable delay fault
mo dels and devise algorithms that can generate tests for mo deled faults Various fault
mo dels used in delay fault testing and a survey of existing algorithms for test generation
and fault simulation are presented in Chapter
Contribution of the Thesis
new and e cient metho ds for delay test generation and fault simulation of
We prop ose
path delay faults in combinational logic circuits The ma jor contributions of this thesis
are
A new rule based path delay fault simulation algorithm for combinational circuits
employing two valued logic simulation
An e cient test generation algorithm for path delay faults incorp orating multiple
backtrace and several novel features
A new coverage metric for path delay fault testing that alleviates the problems of
verage and an astronomically large numb er of paths
generally low path delay fault co
A two pass test generation approach achieves high fault e ciency
Wehavedevelop ed a novel path delay fault simulator for combinational logic circuits
which is capable of detecting b oth robustly and nonrobustly tested paths simultaneously
Simple binary logic is used in place of the more complex multiple valued logic as used in
most of the fault simulators presented in the literature This contributes to the reduction
of the overall complexity of the algorithm The two valued algebra prop osed in this thesis
is simpler though not necessarily faster than the multi valued algebras A rule based
approach has b een develop ed whichidenti es all robust and nonrobust paths tested by a
two pattern test while backtracing from primary outputs to primary inputs in a depth
manner Additional rules are develop ed to nd probable glitches and to determine rst
Chapter Intro duction
how they propagate through the circuit which enables the identi cation of nonrobust
paths Exp erimental results for several ISCAS and scan hold versions of ISCAS
benchmark circuits are given
Wehavedevelop ed a versatile and e cient automatic test pattern generation system
for path delay faults in combinational logic circuits To facilitate a simultaneous con
sideration of robust and nonrobust tests we have devised a new value logic system
Once a robust test is found for some path with a given transition our algorithm derives
minimal extra e ort The derived test in most cases is either a robust another test with
or nonrobust test for the same path with the opp osite transition We employ a multiple
backtrace pro cedure for satisfying the test generation ob jectives We also use a path
selection metho d which covers all lines in the logic circuit by the longest and shortest
possible paths through them We have integrated our fault simulator with this test
generator to determine all robustly and nonrobustly detected faults from the targeted
well as from all p ossible path faults in the circuit Exp erimental results path faults as
on several ISCAS and scan hold versions of ISCAS b enchmark circuits substantiate
the e ciency of our algorithm in comparison to other published results
We prop ose a practical coverage metric called line delay fault coverage and a two
pass test generation metho d for path delay faults in combinational logic circuits The
coverage is measured for each line with a rising and a falling transition The new test
called a line delay test is a robust path delay test for the longest sensitizable path
pro ducing a given transition on the target line One ma jor advantage is that the maximum
b er of lines Since the fault is tested numb er of tests and faults is limited to twice the num
along the longest propagation path the system timing failures caused by the smallest
lo calized delay defects sp ot defects or the accumulation of distributed delay defects can
be detected Our mo del thus retains many advantages of the transition and gate delay
fault mo dels while alleviating the ma jor drawback of the path delay mo del viz to o
many paths to be tested and the low fault coverage For test generation in the rst
pass we begin with a minimal set of longest paths covering all lines and generate tests
simulation is used to determine the line delay coverage For uncovered for them Fault
Chapter Intro duction
lines in the second pass several paths of successively decreasing length are targeted We
giveatheorem stating that a redundant stuck fault on alinemakes all path delay faults
corresp onding to paths passing through that line untestable for a particular transition
The use of this theorem reduces the e ort of delay test generation An implementation of
our algorithm achieved very high line delay coverage e ciency for most of the
ISCAS and scan hold versions of ISCAS b enchmark circuits
Organization of the Thesis
In Chapter we survey delay fault mo dels and prior work on test generation and fault
binational and sequential logic circuits In Chapter simulation of path delay faults in com
we present our path delay fault simulator which uses binary logic Delay fault simu
lation results for ISCAS and scan hold versions of ISCAS b enchmark circuits are
presented In Chapter we describ e an e cient automatic test generation system for
path delay faultsincombinational logic circuits A new value logic system is illustrated
for the simultaneous generation of robust and nonrobust tests Test generation results are
presented for b oth ISCAS and scan hold versions of ISCAS b enchmark circuits In
Chapter we present the new coverage metric called line delay fault coverage and a
two pass test generation metho d for path delay faults in combinational logic circuits We
e employed the information on redundantstuck at faults in the circuit obtained from hav
a stuck at fault test generator to avoid test generation for a large number of untestable
path delay faults and thus haveachieved signi cantsavings in computational time bythis
novel approach Results are presented for ISCAS and scan hold versions of ISCAS
benchmark circuits Finally in Chapter we present a critical review of our work and
suggestions for further research
Chapter
Prior Work
This chapter provides the necessary background for the work rep orted in this thesis We
rst discuss various fault mo dels used in delay testing along with their advantages and
limitations A brief survey of the existing techniques for delay fault simulation and test
generation is also presented
Delay Fault Mo dels
When a logic circuit is found to b e free from DC stuck at faults it do es not imply that the
circuit will op erate correctly under actual op erating conditions The op eration of digital
circuits is often controlled by p erio dic clo ck signals Correct op eration requires that
blo ck must be completed within
the propagation of signals in the combinational logic
a clo ck period Delay fault testing is used to ascertain that the manufactured digital
circuits meet their timing sp eci cations and op erate correctly at desired clo ck rates A
delay fault causes logic values to change slower than the normal rate which leads to the
malfunctioning of the logic network at the rated sp eed Unlike a stuck at fault a delay
fault do es not a ect the steady state logical op eration of a system but a ects the timing
behavior of the system and degrades the overall system p erformance In the recent past
e b een prop osed for delay testing These are describ ed b elow three fault mo dels hav
Chapter Prior Work
Transition Fault Mo del
The transition fault mo del is considered as a logical
mo del for a defect that delays rising or falling transitions at inputs and outputs of logic
gates There are two kinds of transition faults i e slow to rise and slow to fal l The
slow to rise transition fault temp orarily b ehaves like a DC stuck at fault Likewise the
slow to fall transition fault corresp onds to aDCstuck at fault
A test for a transition fault is a pair of input patterns one initialization pattern
state of a transition and another propagation pattern to cause to set up the initial
the appropriate transition and observe its e ects at a primary output The propagation
pattern is identical to the pattern that detects the corresp onding DC stuck at fault
The transition fault mo del has another application indep endent of its use as an
idealized mo del of delay faults It is well known that stuck op en transistors can induce
sequential b ehavior in CMOS logic circuits and testing for such defects can b e done only
by applying pairs of patterns For dynamic CMOS circuits op en transistors that cause
sequential b ehavior corresp ond to certain transition faults in Bo olean circuits
coverage is a measure of the e ectiveness of the delay test in The transition fault
detecting large delay variations Transition faults are a sp ecial case of gate delay faults
b ecause the delaydue to the defect is large enough to cause a logical failure when propa
gated along any path through the site of the fault The main drawback of this mo del is
the assumption of large gate delay faults Also it is di cult to tell how small a delay
fault can b e b efore it is not detectable In practice delayvariations tend to b e distributed
over many circuit elements Thus many small gate delay faults each undetectable as a
transition fault can give rise to a large path delay fault
y Fault Mo del
Gate Dela
A quantitative mo del for delay faults de ned as the gate delayfault was rst intro duced
by Carter et al In this mo del it is assumed that delays through the logic gates
are known with some precision The characteristics of likely delay faults size lo cation
Chapter Prior Work
are also known The delays through a gate are represented by intervals in this mo del A
fault is an added delay of certain size say in the rising or falling transition at a gate
input or output The set of faults considered includes numerical delay information An
excessive delay of nanoseconds at a pointisnot the same fault as an excessive delayof
nanoseconds at the same p oint Both the path delay fault mo del discussed in the next
section and the transition fault mo del share the characteristic that precise gate delay
information is not integrated into these mo dels and some p otential tests for the particular
under test are excluded The gate delay fault mo del overcomes this drawback as circuit
illustrated b elow
Consider the circuit given in Figure where the fault b eing considered is a slow to
rise delay fault on line B To excite this fault we need to apply a transition on B
The initial and nal values required at the latch with output B are indicated The arrows
between the latches indicate the correlation in the scan chain when the nal pattern is
derived by a one bit shift of the initial pattern For example sp ecifying a initial value
F puts the of for B forces the same nal value for C To propagate the fault to
requirement of for the nal value of A To further propagate the fault to the output H
requires a steady without anyglitch on G Since B already has a transition
most test generation schemes will attempt to justify a steady on G by setting a steady
on E However a steady on E results in a con ict with the values chosen so far as
it requires steady on both inputs to E Without any knowledge of the circuit delays
one would have to give up at this point However the set of latch values indicated is a
G has a steady because E do es test if the AND gate E delay is large enough that
not fall until after B has risen
Given the size of a gate delay fault most of the recent research in this area has
concentrated on the determination of such fault sizes detected byagiven test
Given a particular fault of a xed known size Carter et al provide a metho d to
determine whether a test T detects that fault This is clearly a painstaking and ine cient
metho d and it would be more desirable to nd a certain minimum fault size at a fault
is guaranteed to detect site such that given atest T for a fault at the ab ove fault site T
Chapter Prior Work
A 1 1 11 F B1 0 1 1 0 B 0 1 H B2 1 0 1 0 C 10 1 1 1 0 G E D 11
1 1
Figure Example of a fault that requires knowledge of circuit delays
any fault at that site with a magnitude greater than the determined minimum size
Path Delay Fault Mo del
The path delay fault mo del was rst prop osed by Smith This mo del has received
greater attention than the gate delay and transition fault mo dels and has been quite
extensively studied
on various asp ects of test
A considerable amount of research has already been rep orted
generation and fault simulation of path delay faults Our research work mainly considers
e cient metho ds for test generation and fault simulation of path delay faults and we
prop ose anew coverage metric for path delay fault testing in Chapter
In path delay fault mo del any path with a total delay exceeding the system clo ck
interval is said to have a path delay fault This is a distributed fault mo del because
primary it is asso ciated with an entire path For each physical path P connecting a
input to the primary output of the circuit there are two corresp onding delay paths The
rising path falling path is the path traversed by a transition which is initiated as a
rising falling transition at the input of path P and changes the direction of transition
whenever it passes through an inverting gate For convenience we shall refer to a delay
path simply as a path and denote it as P when the direction of the transition is x
Chapter Prior Work
immaterial A path P is said to have a path delay fault if the propagation delay of the
x
path is larger than the clo ckinterval T as describ ed in the previous chapter We present
c
the following de nition from
De nition Let G be agate on path P in alogiccircuit and let r be an input
to gate G r is called an o path sensitizing input if r is not on path P
Robust Tests
fault
The class of robust tests for path delay faults is a very imp ortant class of delay
detecting tests We present the following de nitions and results for combinational
circuits
De nition A two pattern test V V is called a robust test for a delay
fault on path P if the vector detects that fault indep endently of all other delays in the
circuit
It has b een shown that a two pattern test V V represents a robust test
for path fault on P i
of the path
it provokes a transition on the primary input at the source
it guarantees that all signals on the structural path corresp onding to P cannot attain
their nal values according to V until the provoked transition reaches them
Nonrobust Tests
De nition A two pattern test V V is called a nonrobust test for a delay
fault on path P if it detects the fault under the assumption that no other path in the
circuit involving the o path inputs to P has a delay fault
A satisfactory de nition for nonrobust test has not b een given in the literature The
al of de nition given by Schulz et al and several others is based on the early arriv
the o path signals It is p ossible to nd an example where a nonrobust test will fail to
detect the fault even if their condition is satis ed Therefore we have chosen the ab ove
de nition which matches that of Gharayb eh et al
Chapter Prior Work
It has been shown that a two pattern test V V represents a nonrobust
test for a fault on path P i
it provokes a transition on the primary input at the source of the path
V causes all o path sensitizing inputs along the structural path corresp onding to P
to assume those non controlling values that allowthe propagation of the transition
from the primary input PI to primary output PO
Examples for robust and nonrobust tests are given below
Consider the circuit given in Figure The two pattern test vector consists of the
and the propagation vector V According to initialization vector V
De nition this is a robust test for the structural path P C E I J L N Q shown
in b old lines since all signals on the corresp onding path cannot attain their nal values
unless the provoked transition at input C arrives The same test b ecomes a nonrobust
test for the structural path P C E I J L M P b ecause an excessive delay in the rising
transition on line H may cause the primary output line P tohave its exp ected true nal
logic value at the sampling time regardless of the delayonpathP Thus it can lead
to the conclusion that the circuit is fault free although there are delay faults on line H
But if there is no delay fault on line H and when P has a delay fault we and path P
will get the faulty logic value on the primary output P at the sampling time provided
that the delay fault on P is not due to a lump ed delay defect on the output gate P
Thus the ab ove test ful lls the conditions for a nonrobust test for path P as stated in
De nition The usefulness of a nonrobust test is limited since it do es not guarantee
circuit the detection of a path delayfaultindep endent of other path delays in the
The gate delay and transition fault mo dels describ ed earlier have some inherent draw
backs They do not mo del the cumulative e ect of distributed gate delays along a path
from primary inputs to primary outputs The path delay fault mo del alleviates this de
ciency In this mo del the delay fault is asso ciated with a physical path and the path is
declared to b e free of delay faults only if the transition provoked at the input of the path
propagates to the output through the sp eci ed path in less time than the op erational
Chapter Prior Work
A 1 1 H D 0 1 P B M 1 1 1 1 L J C E 1 0 1 0 I F 1 1 0 1 N K Q O 0 1 G
0 0 1 1
Figure Example of robust and nonrobust tests
system clo ckinterval Thus the path delay fault mo del provides the capability of mo del
ing the distributed failures which are mainly caused by statistical pro cess variations and
physical defects during the VLSI manufacturing pro cess
The ma jor b ottleneck in the path delay fault mo del is the selection of paths for which
test generation and fault simulation are to b e carried out since as the circuit size grows
the number of paths grow exp onentially with circuit depth and the number of fanouts
Hence prior to the test generation and fault simulation pro cess it may be necessary
to fo cus on a subset of all p ossible paths in the logic circuit There are several metho ds
ailable in literature suchasworst case path selection threshold basedpath selection av
or a p olynomial time algorithm to nd a minimum cardinality path set We have
employed a path selection metho d similar to Li et al where we consider the longest
and shortest p ossible paths through each line in the logic circuit
Prior Work on Path Delay Fault Simulation
We present a brief survey of various path delay fault simulation techniques describ ed in
work is limited to test generation and fault simulation of path the literature Since our
delay faults in combinational circuits we have concentrated only on the path delay fault
Chapter Prior Work
mo del
Path Delay Fault Simulation by Logic Value Propagation
Smith rst prop osed a pro cedure that identi es paths which are tested for path delay
faults by a given set of patterns He used a six valued logic to describ e the state of a signal
in two consecutive patterns Each value consisted of the ordered pairs s s p p
and The rst element of each ordered pair was a Bo olean or which represented the
nal logic value of the signal The second value was s steady p path or neither
s nor p A value s indicated that a gate necessarily held a steady value during the
of the two patterns This must be true no matter what delays are assumed for the gates
network The value s s indicated that the initial and nal logic values of the signal
were and there were no transients hazards between the two consecutive patterns
A value p indicated that there was at least one path of gates with a value p from the
network input to this gate and that the gate output did not change b efore transitions
network input to have propagated through each path of gates with a value p from the
this gate A value p p denoted a falling rising transition of the signal during the
two consecutive patterns There may be momentary transitions between the initial and
nal patterns A value indicated that it did not meet the criteria for values s or p
A gate with a value may have none one or many transitions Its nal value may or
maynot b e the same as its initial value The value represented a logic value
and an unknown X logic value in the initial pattern in the nal pattern of the signal
There maybe several transitions b etween the two consecutive patterns
The following pro cedure describ es how to identify the set of paths that are robustly
tested for path delay faults indep endent of other delays by a set of patterns
Pro cedure
Generate the next set of initial and nal values Assign corresp onding values s s
p or p to each input of the network
Chapter Prior Work
Propagate values as p er the propagation tables which can b e easily derived for each
gate typ e
Trace each path in the list of untested paths Any path with the correct transition
direction and with the value p on every gate of the path is agged as tested It is
then removed from the path list
The main advantage of this metho d is that a path is tested for path faults indep endent
of gate delays and the size of any individual gate delay has no e ect on the delay testing
of the path Whether or not the delay values of individual gates exceed sp eci cations is
irrelevant to this criterion This fault mo del is capable of mo deling all delayfaultsofany
function of the number of size The execution time is roughly prop ortional to a linear
gates and the number of paths
Parallel Pattern Fault Simulation of Path Delay Faults
Schulz et al prop osed an accelerated fault simulation for path delay faults which
applies parallel pro cessing of patterns A large number of paths cannot be tested under
the restrictive condition of robustness Using Smith s six valued algebra they devised a
four valued algebra to enable simulation of robust and nonrobust path delay faults
umber of paths in circuits they
In order to e ectively cop e with the typically huge n
have employed a highly economical data structure called the path tree Its basic idea
consists in storing parts of paths which are common to many paths from a distinct PI
to POs only once rather than explicitly carrying them along for each path separately
Performance results for robust and nonrobust path delay fault simulation of random
pattern pairs for the ISCAS benchmark circuits have been rep orted However even
with an e cient data structure explicit representation of all physical paths can be very
e for example it takes more than MB to store the path tree for circuit c exp ensiv
Chapter Prior Work
Non Enumerative Estimation of Path Delay Fault Cover
age
Pomeranz and Reddy prop ose a metho d to estimate the number of path delay
faults detected by a given test without enumerating paths The time complexity of the
algorithm is p olynomial in the size of the circuit The computed estimate is p essimistic
i e the true fault coverage is greater than the estimated one As the degree of complexity
of the p olynomial is increased b etter estimates are obtained If the degree of p olynomial
is allowed to b e of the order of number of lines in the circuit instead of b eing a constant
faults detected the complexity b ecomes exp onential and the exact number of path delay
is obtained Three prop erties are used to allowthe fault coverage of path delay faults to
be estimated without enumerating paths
The total number of physical paths in the circuit can be computed in time that is
linear in the number of lines in the circuit by making one backward pass over the
circuit
Considering a single test pattern one pass of fault free logic simulation is required to
determine which lines in the circuit b elong to paths whose delay faults are covered
of lines
by the test In this metho d the number of paths de ned by this subset
can b e determined in linear time without enumerating paths The number of paths
computed equals the number of path delay faults covered by the test
Considering an arbitrary test pattern in a given test set some of the faults detected
by the test are also detected by the preceding tests Only new faults detected for
the rst time by the test pattern considered should be counted for the purp ose of
computing the fault coverage Circuit lines that are not included in path delay
faults detected by earlier tests are determined These lines are called new lines
by the test pattern considered can
The number of new path delay faults detected
be p essimistically estimated by counting the number of path delay faults detected
by the test which include at least one new line The estimated number of faults
Chapter Prior Work
can then b e added to the numb er of faults detected earlier to obtain an estimate of
the fault coverage
An approximation is required to estimate the fault coverage of a test set comprising
more than than one test Several levels of approximation with increasing accuracy and
increasing complexity have been prop osed In all cases the metho d remains p olynomial
in the numb er of lines in the circuit and thus allows even circuits with exorbitantnumber
of paths to b e considered under the path delay fault mo del However using the zero order
approximation metho d the coverages tend to be very p essimistic and have a signi cant
Also the metho d do es not give any information error as rep orted by Heragu et al
ab out the detectability of individual faults which can b e used for fault dropping Heragu
et al have prop osed further improvements to this metho d to reduce the estimation
error in fault coverage
Fault Coverage Estimation by Test Vector Sampling
Heragu et al prop osed another approximate technique of estimating fault coverage
in combinational circuits by fault free simulation of a random sample of the test vector
set Unlike fault sampling where exact fault simulation is required for the sampled faults
over the entire vector set in this case they only determine detection probabilities of all
randomly sampled subset of vectors faults from fault free simulation of a
The prop osed vector sampling metho d is applicable to b oth stuck at faults and delay
faults They use a fault sampling technique to determine path delay fault coverages
with resp ect to all paths where only a xed number of sampled paths is considered for
fault coverage computation Following fault free simulation of a random sample from the
vector set they statistically compute controllabilities and observabilities of all faults in
the circuit which are used to predict fault detection probabilities on a randomly selected
vector pair The detection probabilities for the entire length of the vector set is then
computed and are used to predict the fault coverage
F faults V vectors and N lines in a circuit the complexity of their metho d is
For
Chapter Prior Work
O N as opp osed to O N F V for a fault simulator and O N V for a random
sampling estimator The reduction in complexity of fault coverage estimation becomes
very signi cantinapplications like built in self test BIST where the number of vectors
is typically very large
Delay Fault Coverage Estimation by Selective Path Search
hronous
Bose et al prop osed fault simulation algorithms for path delay faults in sync
sequential circuits A dynamic path search of only the active paths is devised to
avoid explicit simulation of all path faults The fault simulator provides b oth robust and
nonrobust fault coverage For robust coverage a new up date rule Optimistic Up date
Theorem for state variables is used in which latches are up dated with their correct values
provided they are destinations of at least one robustly activated path delay fault This
rule provides a less p essimistic coverage than the earlier metho d of Chakrab orty et al
in which all latches with transition were assumed to have unknown values
Among the numerous p ossible paths in a circuit only a few propagate transitions
paths dep ends on the previous and current during any given vector The number of such
vectors and is a dynamic prop erty of b oth the circuit and input vectors After simulation
of a new vector the algorithm evaluates the highest ranked sensitized path in the subtree
ro oted at each no de This information is maintained at each no de with the help of a
one bit propagation ag called p ag and an integer identi er referred to as maxpath
If p ag is false then no sensitized path to any output of the combinational logic exists
in the subtree and the value of maxpath is irrelevant So p ag is true if a sensitized
ath uses the values of path from that no de to an output exists The evaluation of maxp
pathcount at each no de of the graph The computation is done with a depth rst search
The complexity of the algorithm is O n F where n is the numb er of lines the circuit
and F is the number of faults considered However if for every vector pair a signi cant
n
number of paths is sensitized then the complexity of this algorithm can b e O n in
the worst case due to the p ossibilityof an exp onential number of paths in large circuits
Chapter Prior Work
Hence the metho d may not work well for estimating path delay fault coverage for large
circuits
Exact Path Delay Fault Coverage Estimation
In recent pap ers Gharayb eh et al have presented an e cient fault simulator for
path delay faults that do es not involve enumeration of paths Their metho d calculates
the exact fault coverage and identi es all tested faults even in circuits with a very large
They have presented a new data structure called Path Status Graph number of paths
PSG to e ciently hold the status of each path delay fault in the circuit The key to this
e ciency is in breaking the information into pieces and distributing over the data structure
and in retaining all or part of the reconverging fanout structure of the circuit in the PSG
Thus an exp onential number of path delay faults can share the same piece of information
In their implementation they have used the sixteen valued algebra which is e cient
for simulating single input change SIC pattern pairs They have concentrated on non
robust detection which identi es singly testable ST path delay faults
Kap o or has presented an e cient algorithm to compute exact path delay fault
faults has coverage In his implementation a set of consecutively numbered path delay
b een represented as a closed interval over a pair of integers He has describ ed a mo di ed
tree data structure to store and manipulate these intervals to keep track of tested faults
In addition to estimating exact path delay fault coverage this technique also provides the
abilityto e ciently nd out whether agiven path delay fault has b een tested
SPADES A Path Delay Fault Simulator for Sequential
Circuits
Pomeranz et al prop osed a fault simulator for path delay faults in synchronous
sequential circuits where a test sequence is considered under di erent combinations of
the fault simulator slow and fast clo ck cycles clocking schemes The main features of
are as follows A sp ecial path representation scheme is used which facilitates the step
Chapter Prior Work
where a detected path fault is compared to the previously detected path faults to nd
whether the fault has already b een detected by a previous test or the fault coverage has
to be increased For a given input sequence V and a clo cking scheme C containing
a single fast clo ck cycle it determines the path delay faults detected by robust and
nonrobust tests Given an input sequence V it simulates in paral lel all cases of a
ector applied with a fast clo ck The full fault coverage of a test sequence di erentsinglev
of length k when used with any set of clo cking schemes can b e determined by considering
anumber of clocking schemes which is linear in the length of the test sequence instead of
k
considering all p ossible clo cking schemes Given an input sequence it determines
a minimal number of clo cking schemes each using multiple fast clo ck cycles to achieve
the maximum fault coverage These features maximize the numb er of faults detected bya
given sequence and minimize the number of clocking schemes with whichatestsequence
is applied
The ma jor drawback of the prop osed metho d is that it assigns unknown values to
signals at their inputs in the previous vector Such o path latches that have non steady
pro cedures are p essimistic and predict low fault coverages They also have an adverse
e ect on the execution time of fault simulation esp ecially if the circuit has a large number
of active paths because a separate analysis of fault e ect propagation may be necessary
for every active path fault The situation can be remedied by the optimistic up date
theorem of Bose et al as mentioned in Section
Prior Work on Test Generation for Path Delay
Faults
Wenowgive a brief survey of various test generation techniques whichhave b een develop ed
We also discuss for path delay faults in combinational as well as sequential logic circuits
the advantages and limitations of the di erent approaches
Chapter Prior Work
Test Generation for Path Delay Faults Using PODEM
Lin and Reddy rst prop osed a PODEM based test generation technique for path
delay faults in combinational circuits The delay fault test generation algorithm with a
PODEM typ e mechanization with several heuristics to aid backtracing has been imple
mented and describ ed byPatil and Reddy They prop ose a ve valued logic system
to facilitate the derivation of robust tests for path delay faults and give necessary and
for a given path su cient conditions for a two pattern test to b e a robust test
The ma jor advantage of this approach is that the prop osed logic system allows sp ec
i cation of minimal signal conditions to propagate required transitions along the path
under test The reduced numb er of logic symb ols leads to more e cient implementations
in terms of computation time and memory requirements
DYNAMITE
Fuchs et al prop osed a test generation system for path delay faults in combinational
or scan based circuits named Delay Fault Oriented Automatic Test Generation System
DYNAMITE Their metho d exploits the b ene cial techniques applied in the automatic
test generation ATG system SOCRATES Based up on a valued logic for robust
tests and a three valued logic for nonrobust tests DYNAMITE is capable of generating
antage of tests for path delay faults Moreover in order to overcome the main disadv
the path delay fault mo del they intro duce a new path sensitization pro cedure which is
capable of e ciently identifying large number of path faults as redundant with a single
ATG attempt If the given subset of paths is not highly testable due to the presence
of many redundant paths DYNAMITE dynamically switches to another subset of paths
and mayeventually succeed in generating a test set for all testable path delay faults The
path tree structure describ ed in Section is used for e cient storage of paths
All selected paths are stored in the path tree A stepwise path sensitization pro cedure
enumerating them This metho d is identi es sets of redundant path delay faults without
very e ective in p o orly testable circuits but many faults have to b e treated separately in
Chapter Prior Work
those circuits that are highly testable A limitation of this approach is that the storage of
the path tree is impractical for large circuits Because of limited memory resources the
set of all path delay faults must usually b e partitioned into many subsets
Delay Fault Testing Using Bo olean Expressions
Bhattacharya et al present a new test generation technique for path delay faults in
scan hold typ e circuits They use reduced ordered binary decision diagrams ROBDDs
to represent Bo olean functions implemented by the sub circuits in a circuit as wellasto
represent the constraints to b e satis ed by the delay fault test Two faults are considered
for each path in the circuit under test and a pair of constraint functions corresp onding to
transition is evaluated for each fault These con the two time frames that constitute a
straint functions are manipulated to obtain robust tests if they exist otherwise nonrobust
tests are obtained For circuits amenable to analysis using BDDs the Bo olean algebraic
technique is much faster than existing branch and b ound algorithms This approach how
ever requires p ost pro cessing steps to check for robustness Since an exhaustive check
may b e prohibitively CPU intensive the metho d only provides a conservative estimate of
the robust path delay fault coverage
Chakradhar et al have employed a four valued logic in a similar approachwhen
the constraint function is solved using a transitive closure metho d
NEST Non Enumerative Test Generation Metho d for Path
Delay Faults
Pomeranz et al present a test generation metho d that is based on the pro cedures
intro duced in their fault coverage estimator describ ed in Section and is ca
pable of generating tests for a large number of path delay faults without enumerating
paths The basic idea behind the metho d is to replace the practically infeasible pro cess
of considering an exp onential number of paths with a pro cess that considers single lines
The authors show that it is p ossible to detect a large number of path delay faults by
Chapter Prior Work
propagating transitions robustly through parts of the circuit without having to enumer
ate the complete paths through which these transitions are propagated To make the
metho d e ective sub circuits with a large number of paths which can be simultaneously
tested are identi ed This is done by using a lab eling technique that considers only lines
and not paths For every selected sub circuit test generation ob jectives are determined
Once the ob jectives are satis ed a test is obtained that often detects a large number of
path delay faults A fault simulation metho d is then used to estimate how many
faults are actually detected
tage of this approach is that in contrast to conventional test genera
The ma jor advan
tion approaches where sp eci c faults are targeted this metho d allows circuits with a large
number of detectable path delay faults to be handled It thus removes the most serious
restriction of the path delay fault mo del The drawback of this metho d however is that
though it is e ective in highly testable circuits it may fail in those with p o or testability
NEST also provides only a conservative estimate of the robust path delay fault coverage
Compact Delay Tests by Multiple Path Activation
Bose et al present a test generation algorithm for multiple path tests The ob jective
is to generate a compact set of tests that will robustly test all testable path delay faults
many path faults as p ossible Other
Each test is successively augmented to detect as
features of the test generator are a PODEM like branch and b ound search for test and an
algorithmic selection of secondary target faults for augmenting the tests to cover multiple
faults The new ideas incorp orated in the algorithm are
A value logic system that represents the signal state in two consecutive vectors
It has b een shown that such a value logic system is ideal This logic system
is complete and puts minimum restrictions on signals for satisfying path activation
requirements
An e cient path numb ering scheme previously develop ed for path delay fault sim
ulation is employed to avoid storing the details of paths which may
Chapter Prior Work
require enormous memory
A test generation pro cedure that arbitrarily selects the rst path and uses the
value logic to obtain a test with a minimal set of essential signal assignments The
logic is further used to nd the candidate paths that may b e testable by augmenting
the present test
The drawback in this approach is that the fault selection algorithm is heuristic and
do es not guarantee that a test will indeed b e found by input assignment mo di cation for all
secondary target faults No consideration is given to the circuit connectivity However the
metho d works well for smaller circuits whereas for some circuits the numb er of secondary
backtracks is very large as rep orted in the results
e presented an e cient metho d
In a recent pap er Pramanick and Reddy hav
for multiple path propagation compact tests for delay faults where each test covers many
single path faults
RESIST Recursive Test Generation for Path Delay Faults
Fuchs et al present RESIST a recursive test pattern generation algorithm for path
delay fault testing of combinational and scan based sequential circuits Five di erenttest
classes are intro duced and their prop erties are discussed They derive a logic system for
test pattern generation that results in an early recognition of con icting value assignments
RESIST uses the derived logic system for each test class for an optimal search strategy
fact that many paths in a circuit
In contrast to earlier approaches RESIST exploits the
have common subpaths and sensitizes these subpaths only once thus reducing the number
of value assignments during path sensitization signi cantly In addition the pro cedure
identi es large sets of untestable path delay faults without enumerating them
Rep orted results show that RESIST is capable of p erforming test pattern generation
for al l path delay faults in ISCAS and ISCAS benchmark circuits A comparison
with other test pattern generation systems shows that RESIST is signi cantly faster than
all previous published metho ds
Chapter Prior Work
Test Generation for Path Delay Faults in Non Scan Se
quential Circuits
Agrawal et al develop ed a new metho d for generating tests for path delay faults
in synchronous sequential circuits using the sequential circuit test generation program
STEED To generate a test sequence forapathdelay fault they augment the netlist
mo del of the circuit under test with a sequential logic blo cksuch that the test for a single
stuck typ e fault in this blo ck is also a test for the path delay fault in the original circuit
The added logic consists of a pair of ip ops and a few logic gates that are driven bythe
signals feeding the gates on the paths A stuck at fault in this logic is activated and its
e ect is latched into the destination ip op of the path only when all signals on the path
are set in the states required for the delay test The fault e ect is then propagated to a
primary output The test sequence for the stuck fault thus p erforms all three functions
namely initialization path activation and fault propagation for the delay fault
Given a path and a transition a mo di ed circuit is created in which a test for a
sp eci ed single stuck fault will detect the delay fault This stuck fault is de ned as
follows
vectors have The stuck fault must be activated only when the two path activation
been applied to the combinational logic Since the circuit is sequential any initial
ization vectors also precede path activation vectors
D is injected into the destination Once the stuck fault is activated its e ect D or
ip ops of the path This happ ens at the second path activation vector Prior to
its activation the stuck fault must not interfere with the normal op eration of the
circuit
After the fault e ect is stored in the destination ip op the stuck fault must allow
the fault free function of the circuit during the propagation phase
Notice that the initialization and propagation phases assume slow clo ck op eration The
main disadvantage in this approach is that the complexity is rather high which makes it
Chapter Prior Work
impractical for very large sequential circuits
Chakrab orty et al prop ose another metho d for test generation of path delay
faults in random logic sequential circuits A new thirteen valued algebra is employed to
represent logic values in two consecutive time frames and the hazard b etween them This
algebra helps in detecting robust and nonrobust tests and hence is useful for path based
delay fault simulation Three fault mo dels are prop osed based on sp eci c assumptions
ab out the initial states of ip ops for the vector sequence that propagates the captured
h the clo ck is logic value to a primary output This metho d of path delay testing in whic
run at rated sp eed only during the path activation phase simpli es test generation
One disadvantage of this approach is that no sp eci c criterion is used to select a
combinational path between the source and destination Hence this metho d may not b e
feasible for large circuits The exp erience in their approach indicates that circuits with
p o or testability with resp ect to stuck at faults may in fact also have many untestable
paths The consequences arising from low path delay fault coverage however require
detailed investigation
The pro cess of test generation under rated clo ck test application in sequential circuits
is more complex Recent results have been given by Bose and Agrawal However
b ecause of the complexity of the problem they were able to give results only for some
smaller b enchmark circuits
Multi valued algebras are basic to delay testing These algebras should be minimal
use the smallest number of values and complete provide all information necessary for
the sp eci c problem Derivation of such algebras is discussed by Bose et al
Conclusion
e brie y discussed the three imp ortant delay fault mo dels namely the
In this chapter w
transition fault mo del the gate delay fault mo del and the path delay fault mo del The
advantages and limitations of these fault mo dels were also discussed Our presentwork is
con ned to the path delay fault mo del which has the advantageous capability of mo deling
Chapter Prior Work
the distributed failures along an entire path We have also presented a brief survey of
various techniques used for test generation and fault simulation of path delay faults in
combinational as well as sequential circuits In the following chapters we will describ e
the main contributions of our work i e the development of e cient test generation and
fault simulation algorithms for path delay faults in combinational circuits and also a new
line delay fault coverage metric for path delay faults
Chapter
Path Delay Fault Simulation Using
Binary Logic
In this chapter we present anovel path delay fault simulator for combinational logic cir
cuits The simulator is capable of detecting both robustly and nonrobustly tested paths
simultaneously We use binary logic instead of the multiple valued logic as is used in ex
isting simulators The simpler logic contributes to the reduction of the overall complexity
of the algorithm A rule based approach has been develop ed which identi es all robust
and nonrobust paths tested by a two pattern test using backtracing from POs to PIs in
given to nd probable glitches and to determine a depth rst manner Rules are also
how they propagate through the circuit thus identifying nonrobust paths Exp erimental
results on several ISCAS and the scan hold versions of ISCAS benchmark circuits
demonstrate the e ciency of the algorithm
Intro duction
There has always been an increasing demand for faster digital systems The maximum
allowable clo ck frequency in a synchronous system is determined by the propagation delay
of signals in the combinational network between latches Due to some physical defects
ufactured net statistical pro cess variations or stray capacitances if the delay of the man
Chapter Path DelayFault Simulation Using Binary Logic
work exceeds sp eci cations there is a chance of unstabilized and p ossibly incorrect logic
values b eing latched Delay fault testing can b e used to ascertain that manufactured dig
ital circuits meet their timing sp eci cations and op erate correctly at desired clo ck rates
Thus delay fault testing has achieved theoretical and practical imp ortance in the design
of high sp eed logic circuits In this chapter we have presented a novel path delay fault
simulator for combinational circuits which detects the faulty paths under the application
of two pattern tests
and limitations in the
We describ ed several delay fault mo dels and their advantages
previous chapter The path delay fault mo del is considered for delay fault simulation
and test generation in our present work In this mo del the delay fault is asso ciated with
a physical path in the circuit and the path is declared to be free of delay faults if the
transition provoked at the input propagates to the output through a sp eci ed path in less
time than the op erational system clo ck interval
There is a ma jor b ottleneck in selecting paths for which the test generation and fault
simulation are to be carried out since as the circuit size grows the number of paths can
grow exp onentially with circuit depth and the number of fanouts Hence prior to the
test generation and fault simulation pro cess it may be necessary to fo cus on a subset
of all p ossible paths in the logic network There are several metho ds available in the
literature such as the worst case path selection threshold based path selection and
a p olynomial time algorithm to nd a minimum cardinality path set
Multi valued logic systems are commonly used for test generation and fault simulation
of path delay faults Smith has prop osed a six valued logic which identi es the
paths tested for delay faults indep endent of the delays of any individual gate in the
et al have used Smith s six valued logic and a mo di ed four valued network Schulz
logic for robust and nonrobust detection of path delay faults with parallel pro cessing of
patterns Bose et al have used Smith s six valued algebra for delay fault simulation
of synchronous sequential circuits Similarly multiple valued logic has been used for
the test generation pro cess of the delay faults e g eleven valued logic ten valued
logic and ve valued logic The numb er of logic states used is a factor
Chapter Path Delay Fault Simulation Using Binary Logic
that determines the time and memory complexity of the algorithms based on them fewer
logic symbols lead to less complex implementations Hence we have employed the
simple two valued logic for path delay fault simulation
The broad outline of our fault simulation approachisasfollows During event driven
logic simulation with resp ect to the rst vector initialization vector of the two pattern
test V V we classify all gate inputs as either control ling CO or noncontrol ling
NC based on their logic values After evaluating the true logic values with resp ect to the
propagation vector using the same event driven approach the p ossibility second vector
of a glitch event at the output of a gate is determined taking b oth the initialization and
propagation vectors into account An event queue is also maintained for the propagation
of the glitchevents from PIs to POs in order to determine the robustness nonrobustness
of a path Finally we backtrace from POs to PIs in a depth rst manner based on some
sp eci ed rules to trace the faulty paths Thus our algorithm detects b oth robust and
nonrobust paths during the simulation pro cedure All paths are counted initially but no
fault is detected by a vector pair it is added target path list is generated Once a path
to the global list of detected faults to keep track ofthefaultcoverage Thus all paths in
the circuit are implicitly considered by the fault simulator The algorithm can be easily
mo di ed to simulate faults for any given list of paths
Theoretical Background and Basic De nitions
Hardware Mo del and Clo ck Timings
Unlike a single pattern test as used for testing a stuck at fault delay fault testing re
quires a two pattern test The main ob jective of delay fault testing is to ensure that the
terval maximum propagation delay of paths in the circuit is less than the system clo ckin
The hardware mo del and clo ck timings for delay fault testing have already b een given in
Chapter
Chapter Path DelayFault Simulation Using Binary Logic
Robust and Nonrobust Paths
For clarity of presentation we de ne twotyp es of paths robust and nonrobust employing
the de nitions of robust and nonrobust tests given in the previous chapter
Robust Path A structural path P in the logic network is termed a robust path
with resp ect to a two pattern test V V i
a transition provoked at the input to the path propagates to the output through
the structural path P
that all signals on the structural path P cannot attain their nal
it is guaranteed
values with resp ect to the propagation vector V of the two pattern test V V
until the provoked transition reaches them
A delay fault in the robust path will cause a faulty logic value at the output of the
path indep endent of other path delays in the network The corresp onding vector pair
which detects the faulty robust path is de ned as a robust test
termed a nonrobust Nonrobust Path A structural path P in the logic network is
path with resp ect toatwo pattern test V V i
a transition is provoked at the input of path P by the test V V
the excessive delay on path P can be detected by the two pattern test V V
under the assumption that there do es not exist any other faulty path in the network
In other words the propagation vector V causes all o path sensitizing inputs
along the structural path P to assume their noncontrolling values to propagate the
provoked transition
o pattern test V V consisting of the initialization
Figure illustrates a tw
vector V and the propagation vector V The primary inputs are
assumed to be glitch free The structural path P C E I J L N Q is referred as a
robust path shown in bold lines with resp ect to the test V V since all lines in
path P cannot attain their nal values unless the transition provoked at input C arrives
Chapter Path Delay Fault Simulation Using Binary Logic
at them The structural path P C E I J L M P is referred as a nonrobust path
with resp ect to the test V V b ecause an excessive delay in the rising transition
on line H may cause the PO line P to have its exp ected true nal logic value at the
sampling time t as shown in Figure b regardless the delayonpathP We assume
that the delay fault on path P is not entirely caused by a sp ot delay defect on the output
gate P Thus it leads to the conclusion that the circuit is fault free although there are
But if there is no delay fault on line H as shown delay faults on line H as well as path P
in Figure c we will get the faulty logic value at the PO line P at the sampling
time t Thus path P canbedetected as a nonrobust path with resp ect to the test pair
V V i there is no delay on line H
A 1 1 H D 0 1 P B M 1 1 1 1 L J C E 1 0 1 0 I F 1 1 0 1 N K Q O 0 1 G 0 0 1 1 [a]
H H
L, M L, M
P P tc tc t1 t2 t1 t2
[b] [c]
Figure Examples of robust and nonrobust paths
Chapter Path DelayFault Simulation Using Binary Logic
Sensitivity and Gate Evaluation
During event driven logic simulation with resp ect to the initialization vector V of the
two pattern test V V we classify each gate as follows
Globally Sensitive GS A logic gate with all inputs at noncontrolling NC
values is classi ed as a GS gate Noncontrolling values are for AND NAND
OR NOR gates
Potentially Sensitive PS A logic gate with at least one input at a controlling
is classi ed as a PS gate Controlling values are for AND NAND
CO value
OR NOR gates
Odd Parity Sensitive OPS A logic gate whose output is complemented when
an o dd numb er of inputs haveevents is classi ed as an OPS gate e g XOR XNOR
gates We have restricted the OPS gates to two input gates throughout our dis
cussion as any gate with or more inputs can be mo deled as a cascade of input
gates
Input Sensitive IS A logic gate with single input is classi ed as IS gate since
are IS
the output is complemented by complementing the input Inverters bu ers
gates
Path Delay Fault Simulation Using Binary Logic
In order to perform the path delay fault simulation with resp ect to a given two pattern
test vector we followthe pro cedures given b elow
While doing event driven logic simulation with resp ect to the initialization vector
V of the two pattern test V V the gate sensitivity i e GS PS OPS IS
the gates are
as well as the controlling CO and noncontrolling NC inputs of
determined based on the classi cation given in the previous section An example is
given in Figure where we have taken the test pair V V as
Chapter Path Delay Fault Simulation Using Binary Logic
Gate inputs having a star are the CO inputs with resp ect to the initialization
vector V
A 1 1 H D GS * 0 1 P B M PS 1 1 1 1 L J PS C E * 1 0 1 0 I F GS 1 1 0 1 N K Q * GS O 0 1 G PS
0 0 * 1 1
Figure Evaluation of gate sensitivity CO and NC inputs
Event driven logic simulation is then p erformed for the propagation vector V and
the true nal logic values are evaluated Along with the logic simulation we ad
ditionally check for the p ossibility of a glitch event at gate outputs An example
showing the generation of a glitch at the gate output is shown in Figure There
are both rising and falling transitions at the inputs of the AND gate According
do not have a logic event on the
to the rules of event driven logic simulation we
output of the AND gate However this condition can cause a glitch event at the
gate output if the falling transition at the NC input is delayed with resp ect to the
rising transition at the CO input We have develop ed a set of rules to accurately
mo del the generation and propagation of glitches as explained in the next section
After evaluating the true logic values pro duced by V we p erform glitch propagation
for those glitchevents whichwere scheduled in the previous step in an event driven
manner toward primary outputs
Chapter Path DelayFault Simulation Using Binary Logic
10 00 PS
01 *
Figure Glitch generation
Finally we backtrace from POs to PIs in a depth rst manner to determine the
tested paths b oth robust and nonrobust based on the rules explained in Section
Glitch Generation and Propagation
In order to determine the robustness nonrobustness of a path we need to check for the
p ossibility of a glitch event at the gate output A robust test may get invalidated due
the to the presence of a glitch static hazard caused by another delay fault present in
circuit The concept of hazards static and dynamic and metho ds for their detection and
elimination have been addressed by earlier researchers A simple theorem
for identifying probable glitches based on the structure of reconvergent paths in a circuit
was presented by Shaik et al A glitch is p ossible at a gate output only if two
opp osite transitions arrive at gate inputs and one gets delayed with resp ect to another
Thus only gates whose output do es not have a logic event need be considered for glitch
generation We also need to determine whether or not a glitchevent can propagate to the
hmay propagate through a gate causing a glitch at the output or primary output Aglitc
a glitch and a transition may simultaneously propagate through a gate causing a dynamic
hazard at the gate output However we do not consider the propagation of dynamic
hazards through the circuit This is b ecause if a transition propagates through a gate
any dynamic hazard glitch asso ciated with the transition can also propagate through the
gate Since during backtrace we consider the invalidation of a robust test due to p ossible
dynamic hazards we need not explicitly consider the propagation of dynamic hazards
Chapter Path Delay Fault Simulation Using Binary Logic
We have develop ed a set of simple rules that govern the generation and propagation of
the glitchevent as discussed next
Glitch Generation
Rule If the gate is PS all CO inputs have events and exactly one NC input
has an event so then the output can have a glitchas shown in Figure a
Rule If the gate is OPS and b oth inputs have events then output can have a
wn in Figures b and c
glitchas sho
The ab ove rules are based on the observation that a glitch is p ossible only if transitions
in opp osite directions arrive at the inputs of a gate The situation can not o ccur for GS IS
gates A glitch can occur even when more than one NC input have events provided that
all events at the NC inputs are delayed with resp ect to the event at CO input However
this implies that at least two paths in the circuit have delay faults and thus it leads to
a multiple delay fault assumption Since the criterion for a nonrobust test requires that
path all other paths are assumed to be there is a delay fault asso ciated with only one
fault free we do not consider such cases
10 0 0 10 11 11 PS OPS 01 * 01
[a] [b]
01 00 OPS 01
[c]
Figure Examples of glitch generation
Chapter Path DelayFault Simulation Using Binary Logic
Glitch Propagation
Rule If the gate is GS or OPS a glitch on any input will propagate to the
output as shown in Figures a and b
Rule If the gate is PS exactly one CO input has a glitch all other CO inputs
if more than one CO input are present haveeventsandnoNCinputhasanevent
then the glitch on the CO input will propagate to the gate output as shown in Figure
c We do not restrict the presence of glitches on NC inputs
Rule If the gate is IS the glitch on the single input will propagate to the
output as shown in Figures d and e
1 1 0 0 0 0 * 1 1 1 1 GS OPS 1 1 PS 1 1 1 1 0 1 *
[a] [b] [c]
IS IS
[d] [e]
Figure Glitch propagation
Illustration Figure shows the generation of glitch events at lines I and J
according to Rules and resp ectively The glitchevents are then propagated toward
a primary output based on Rules and mentioned ab ove Finally the path E
G M P can be tested as a nonrobust path based on the rules describ ed in the next
section under the test
Chapter Path Delay Fault Simulation Using Binary Logic
A 0 1 I B PS 1 0 * 1 1 N C GS 1 1 0 0 O K PS D * 1 1 1 0 J E F OPS L 0 1 1 1 GS 1 0 P G M H GS
0 0 1 0
Figure Example illustrating glitch generation and propagation
Backtracing for Robust and Nonrobust Paths
Our strategy in identifying robust and nonrobust paths detected by a vector pair is to
backtrace from POs to PIs in a depth rst manner and mark each input of gates along
the path as robust or nonrobust based on a set of simple rules Once we reach a PI we
have identi ed a path and it is classi ed as a robust or nonrobust path dep ending on the
status of the lines along the path The backtrace employs a recursive pro cedure To start
aPOhaving an event is marked as robust and a PO with a glitchismarked as nonrobust
if its output is robust nonrobust The following
A gate is declared robust nonrobust
rules are then applied to compute the robust nonrobust status of the inputs of a gate
Rules for Evaluating the Inputs of a Robust Gate
The following rules are used to evaluate the robust nonrobust status of the inputs of a
gate that has already b een marked as robust since it has a logic event with or without a
dynamic hazard at its output
Rule If the gate is PS all CO inputs are marked as robust and all NC inputs
with glitches are marked as nonrobust
Chapter Path DelayFault Simulation Using Binary Logic
Rule If the gate is GS exactly one input say input j has an event and no
other input has a glitch then input j is marked as robust If at least one input
except j has a glitch then input j will b e marked as nonrobust
Rule If the gate is OPS the input with an event is marked as robust if there
is no glitchonthe other input else b oth inputs are marked as nonrobust
logic underlying Rules through for Example Figure illustrates the
determining the robust and nonrobust inputs of a robust gate In Figure a the
output D of the AND gate typ e PS has an event and has been marked as robust The
controlling inputs A and B with rising transitions will b e marked as robust since
the path delay fault on these inputs can robustly propagate to output D The delayfault
on input C i e glitch can be propagated to output D if there is no delay
on inputs A and B Thus input C is marked as nonrobust and Rule is justi ed
Example In Figure b the output D of the OR gate of typ e GS has an
event and has b een marked as robust The input B having a rising transition will
be marked as robust since the delay fault on this input can be robustly propagated to
output D But the same input B will b e marked as nonrobust as shown in Figure c
when there is a glitch on input A The glitch on A may cause a true nal
logic value on output D at the sampling time and the delay fault on B could remain
undetected The delay fault on B can propagate to the output provided that there is
no delay on input A and thus B is marked as nonrobust satisfying Rule Again if
there are more than one inputs of the GS gate having events then none of the inputs
will be marked as robust b ecause the delay fault on one input will be masked by the
transition on the other input causing the gate output to have its true nal logic value at
the sampling time
delay fault on input A of the XOR gate of Example In Figure d the
typ e OPS can robustly propagate to output C and thus it is marked as robust In Figure
e the delay fault on A can b e masked by the delay fault on B i e glitch
and vice versa As a result the output can have its true nal logic value at the sampling
Chapter Path Delay Fault Simulation Using Binary Logic
time though there are delay faults on both inputs The delay fault on one input will
propagate to the output provided there is no delay on the other input and thus both
inputs A and B are marked as nonrobust satisfying Rule
A A A 0 1 * 0 0 0 0 B 0 1 D B 0 1 B 0 1 0 1 * PS 0 1 GS 0 1 GS C C D C D 1 1 0 0 0 0
[a] D is robust [b] D is robust [c] D is robust and => A, B are robust and => B is robust A has a glitch C is nonrobust => B is nonrobust
A A 1 0 0 1 1 0 0 1 B OPS C B OPS 1 1 1 1 C
[d] C is robust [e] C is robust and B has a glitch
=> A is robust => A, B are nonrobust
Figure Robust and nonrobust inputs of a robust gate
Rules for Evaluating the Inputs of a Nonrobust Gate
Rule If the gate is PS and the output has a glitch but none of the inputs has
a glitch then the single NC input having an event is marked as nonrobust If the
output has a glitch and exactly one input has a glitch then the input with a glitch
is marked as nonrobust If the output has an event all CO inputs with events as
well as all NC inputs with glitches are marked as nonrobust
Rule If the gate is GS and the output has a glitch all inputs with glitches are
marked as nonrobust If the gate is GS and the output has an event and exactly one
Chapter Path DelayFault Simulation Using Binary Logic
input say input j hasanevent then input j is marked as nonrobust indep endent
of the presence of glitches on other inputs
Rule If the gate is OPS and the output has an event or a glitch then any
input with an event or glitchismarked as nonrobust
A A A 0 1 * 0 0 * 0 1 * B 0 0 B 0 0 B 0 1 D 0 1 * PS 0 1 * PS 0 1 * PS C D CDC 1 0 1 1 1 1
[a] D is nonrobust [b] D is nonrobust and [c] D is nonrobust but => C is nonrobust A has a glitch having an event => A is nonrobust => A, B, C are nonrobust A A 0 0 0 1 0 0 0 1 GS GS B C BC 0 0 0 0
[d] C is nonrobust and [e] C is nonrobust but A has a glitch having an event => A is nonrobust => A is nonrobust
A A A 1 0 1 1 1 1 1 1 1 0 0 1 B OPS B OPS B OPS 0 1 C 0 0 C 1 1 C
[f] C is nonrobust [g] C is nonrobust and [h] C is nonrobust but => A, B are nonrobust B has a glitch having an event
=> B is nonrobust => A is nonrobust
Figure Nonrobust inputs of a nonrobust gate
Example Figure illustrates the logic b ehind Rules through for
determining the nonrobust inputs of a nonrobust gate It must be noted that the inputs
Chapter Path Delay Fault Simulation Using Binary Logic
of a robust gate can be marked either as robust or as nonrobust whereas the inputs of
a nonrobust gate will be only nonrobust This is b ecause if an event at a gate output
cannot robustly propagate to a PO then no event at the inputs to that gate can propagate
robustly to a PO In Figure a the output D of the AND gate of typ e PS has a
glitchand has b een marked as nonrobust The delay fault on the single NC input C can
is no delay fault on any propagate to the output if all CO inputs have events and there
one of the CO inputs Thus input C is marked as nonrobust In Figure b the glitch
on the CO input A can propagate to output D if there are no events on
other NC inputs and thus input A is marked as nonrobust In Figure c the output
D has been marked as nonrobust although it has an event This p ossibility has been
explained in the previous example used for illustrating Rules through Referring
to Figure c the delay faults on inputs A and B can robustly propagate to output D
ed as nonrobust since output D is nonrobust Again input but these inputs will b e mark
C having a glitch will b e marked as nonrobust as the asso ciated delay fault
can be detected provided that there is no delay fault on inputs A and B
Example Consider the case when the output of the GS gate has a glitch and
has b een marked as nonrobust The delay fault i e glitch on any input will propagate
to the output An example is given in Figure d in which input A has a glitch and is
gate has an event thus marked as nonrobust In Figure e the output C of the GS
and has been marked as nonrobust The delay fault on input A having an event will
propagate to the output C provided that there is no delay fault on input B and thus A
will b e marked nonrobust as the output C is nonrobust satisfying Rule
Example Consider the case when the output of an OPS gate has a glitch and
has been marked as nonrobust The delay fault on any input having a logic event or a
ent can propagate to the output Thus inputs A and B having logic events will glitch ev
b e marked nonrobust as shown in Figure f and input B having a glitcheventwillbe
marked nonrobust as shown in Figure g If the output of the OPS gate has an event
and has been marked nonrobust then the delay fault on the input having a logic event
will propagate to the output In Figure h the input A having a logic event will be
Chapter Path DelayFault Simulation Using Binary Logic
marked nonrobust since the delay fault can propagate through the gate and the output
has been marked nonrobust
Rule for Evaluating the Input of an IS Gate
Rule If the gate is IS its input is marked as robust nonrobust provided that the
output is robust nonrobust
Rule is obvious since any transition or glitch at the input of an IS gate will
always propagate through the gate Similarly when we backtrace from a fanout branch
and reach a stem line the stem will b e assigned the same robust nonrobust status as the
branch
where we have applied Rules
Illustration Figure shows an example circuit
to while backtracing from POs to PIs and determined the status of each line Each
line in the circuit will have two asso ciated ags r and nr The r ag is set if the line is
robust and nr is set if it is nonrobust during backtrace For lines that are common to two
or more paths both ags may be set during backtrace and such lines will be indicated
as rnr Wehave applied the two pattern test at the inputs of the logic circuit
events as well as the glitch events through the circuit Finally and propagated the logic
the output P will have a logic event whereas the output Q will have a glitch
event Hence the output P will b e marked as robust r ag set and Q as
nonrobust nr ag set First we backtrace from the robust output P toward primary
of typ e PS will inputs in a depth rst manner The inputs G and M of the AND gate
be marked as robust based on Rule Backtracing along the line G the stem line F
will be marked as robust since its fanout branch G is robust The input C of the XOR
gate of typ e OPS will b e marked robust based on Rule and thus primary input B
which is a stem line for C will also be marked as robust After reaching at the primary
robust since all lines along input B we can enumerate the path B C F G P which is
the path have been marked as robust Next backtracing along line M the stem line L
will be marked as robust The inputs H and J of the XOR gate of typ e OPS will be
Chapter Path Delay Fault Simulation Using Binary Logic
marked as nonrobust based on Rule Backtracing along the line H the stem line F
which has already b een marked as robust will also b e marked as nonrobust nr ag also
set The input C of the XOR gate will b e marked as nonrobust based on Rule and
thus the primary input B will also be marked as nonrobust Hence we can enumerate
another path B C F H L M P which is nonrobust since some of the lines along this path
have b een marked as only nonrobust e g line H Next backtracing along line J the
D of the AND gate of typ e PS stem line I will be marked as nonrobust The input
will be marked as nonrobust based on Rule and thus the primary input B will also
be marked as nonrobust Hence we can enumerate another path B D I J L M P as
nonrobust After enumerating all paths whose output converge on P we backtrace from
the nonrobust output Q The input K of the NAND gate of typ e PS will b e marked as
nonrobust based on Rule and thus the stem line I will also b e marked as nonrobust
to Rule and Backtracing again the input D will be marked as nonrobust according
the stem line B will also be marked as nonrobust Thus we enumerate another path
B D I K Q as nonrobust and now all robust and nonrobust paths tested by the vector
pair have been enumerated
G A * r P 1 1 F r M PS C OPS 0 1 * 0 1 rnr rnr H r L r B J nr OPS 1 0 rnr 01 D nr nr nr 0 0 N E PS * Q 0 1 * I K PS nr nr * 1 1
[a] Path B-C-F-G-P is robust [b] Paths B-C-F-H-L-M-P, B-D-I-J-L-M-P
and B-D-I-K-Q are nonrobust
Figure Example of robustly and nonrobustly tested paths
As shown in Figure we have used the following notation to mark the status of a
Chapter Path DelayFault Simulation Using Binary Logic
line e g a line is denoted as r which is only robust nr which is only nonrobust and rnr
which is b oth robust as well as nonrobust Thus we observe that
A line can be robust as well as nonrobust with resp ect to di erent paths
A functional path will be robust i all lines of the path have their r ag set even
if some lines have both r and nr ags set
A functional path will b e nonrobust i at least one of the lines on the path has only
the nr ag set
Simulation Results
delay fault simulation algorithm in the C lan
We have implemented the prop osed path
guage ab out lines of co de on an IBM RS computer system running UNIX
Table shows the numb er of primary inputs primary outputs numb er of logic levels in
the circuit and total number of physical paths for the ISCAS combinational b enchmark
circuits The CPU times for counting the number of paths have b een included in Table
We have not enumerated the path lists Path counting was carried out as describ ed
by Pomeranz and Reddy The number of logical path delay faults mo deled is twice
the number of physical paths present in a circuit since b oth the rising and falling transi
at the source of each path The number of logical path faults varies tions are considered
from for circuit c to for circuit c
In order to derive a set of deterministic delay fault test vectors for use in simulation
we have employed Patil and Reddy s test generator In Table the total number
of paths generated bytheworst case path selection pro cedure is given in the column
Examined The number of path faults tested is given in the column Tested The column
Dropped denotes the numb er of path faults dropp ed due to the backtrack limit of The
numb er of path faults proved undetectable is given in the column Notest The number of
generated is given in the column Vectors two pattern test vector pairs
Chapter Path Delay Fault Simulation Using Binary Logic
Table Number of p ossible physical paths PIs POs and levels
Circuit PI PO Levels Physical Time
paths secs
c
c
c
c
c
c
c
c
c
c
Table Test generation results
Circuit Examined Tested Dropp ed Notest Vectors Time secs
c
c
c
c
c
c
c
c
c
c
Chapter Path DelayFault Simulation Using Binary Logic
Table shows the delay fault simulation results obtained by our fault simulator
implementation We have simulated three sets of vector pairs to detect b oth robust and
nonrobust paths for all circuits The rst rowofeach circuit shows the simulation results
of the deterministic test pattern pairs for path delay faults denoted as dp d shown in
Table In our simulation pro cedure we use the second pattern propagation vector of
the present simulation as the rst pattern initialization vector for the next simulation
n vector pairs where n is the number of deterministic vector pairs Hence we get
generated which are given in Table The second row in Table for each circuit
shows the simulation results employing the deterministic test patterns obtained for stuck
at faults and these are denoted as dsa These deterministic test patterns for single stuck
faults were obtained using COMPACTEST and had a complete coverage of all non
redundant stuck faults The third row for each circuit shows the simulation results for
random test patterns denoted as r
fault is detected by a test vector pair the path In our implementation once a path
is added to the global path list of detected paths provided that path do es not already
exist in the global list of tested paths The circuit c was not simulated for nonrobust
paths since the number of nonrobust paths detected was extremely large and simulation
did not complete within reasonable CPU time Hence the CPU time mentioned for this
circuit is the time taken only for detecting the robust paths We have not imp osed any
restriction on path lengths All paths tested by the test patterns are added to the global
path list
erall statistics The simulation results of circuit c havenot Table shows the ov
b een considered for the statistics in Table since wehave not considered the nonrobust
paths for this circuit It is to b e noted that the numb er of robust paths tested p er vector
pair by dp d patterns is greater than that of random patterns For example dp d test
patterns test robust paths whereas random patterns test only robust paths
for circuit c Similarly dp d test patterns cover robust paths whereas
random patterns cover only robust paths for circuit c as given in Table On
average the number of nonrobust paths tested per vector pair by dsa patterns is greater
Chapter Path Delay Fault Simulation Using Binary Logic
Table Path delay fault simulation results
Circuit Vector Robust Nonrobust Time
pairs paths paths secs
c dp d
dsa
r
c dp d
dsa
r
c dp d
dsa
r
c dp d
dsa
r
c dp d
dsa
r
c dp d
dsa
r
c dp d
dsa
r
c dp d
dsa
r
c dp d NA
dsa NA
r NA
c dp d
dsa
r
dp d deterministic test patterns for delay faults
dsa deterministic test patterns for stuck at faults r random test patterns
Chapter Path DelayFault Simulation Using Binary Logic
Table Overall statistics
Typ e of Vector Robust Nonrobust Faults det Vector pair
vectors pairs paths paths Robust Nonrobust
dp d
dsa
random
than that of dp d patterns since dp d patterns were obtained using the deterministic robust
test generator As shown in Table the p er vector coverage of nonrobust paths by dsa
patterns is whereas that of dp d patterns is For example dsa patterns
cover nonrobust paths whereas dp d patterns cover only nonrobust paths for
circuit c Similarly dsa patterns cover nonrobust paths whereas dp d
patterns cover only nonrobust paths for circuit c as shown in Table On
the whole the p er vector coverage by dsa patterns is b etter than that of dp d and random
shown in Table This indicates that patterns for b oth robust and nonrobust paths as
vector sets generated by test generators targeting single stuck faults can b e e ectively used
in delay fault testing Simulation with these vectors can cover a signi cant number of
path delay faults so that the delay fault test generator needs to target only the uncovered
paths in the target path list
Table shows the delay fault simulation results for some of the scan hold versions
of the ISCAS benchmark circuits We have simulated random test patterns for
these circuits
Conclusion
In this chapter we have describ ed a novel path delay fault simulator that is capable of
erage of b oth robust and norobust paths We b elieve that our path delay
nding the cov
fault simulator that uses the simple two valued algebra will b e simpler though not neces
sarily faster than the multi valued algebras Although it is not necessary to have a lo ok up
Chapter Path Delay Fault Simulation Using Binary Logic
Table Path delayfaultsimulation results for ISCAS circuits
Circuit Vector Robust Nonrobust Time
pairs paths paths secs
s
s
s
s
s
s
s
s
s
s
s
s
s n
s
s
s
s
s
s
s
s
s
s
s
s
s
Chapter Path DelayFault Simulation Using Binary Logic
table as required in the multiple valued logic evaluation wehave to p erform logic simula
tion b oth for the rst and second vector of eachvector pair Our exp erimental results on
the ISCAS and the scan hold versions of ISCAS benchmark circuits indicate that
even mo derately large circuits can be handled by our simulator within reasonable CPU
time
In the next chapter we will discuss an e cient automatic test pattern generation
system for path delay faults for combinational logic circuits
Chapter
An E cient Automatic Test
Generation System for Path Delay
Faults in Combinational Circuits
In this chapter we describ e an e cient automatic test pattern generation algorithm and
its implementation for path delay faults in combinational logic circuits To facilitate
simultaneous consideration of robust and nonrobust tests we have develop ed a value
logic system Once a robust test is found for a path with a given transition our algorithm
derives another test with minimal extra e ort The derived test in most cases is either
An e cient
a robust or nonrobust test for the same path with the opp osite transition
multiple backtrace pro cedure is employed for satisfying the test generation ob jectives A
path selection metho d covers all lines in the logic circuit by the longest and the shortest
p ossible paths through them Wehaveintegrated a fault simulator with the test generator
which can cover robust and nonrobust path faults either from a targeted path list or from
all p ossible path faults in the circuit Exp erimental results on several ISCAS and
the scan hold versions of ISCAS b enchmark circuits are presented to substantiate the
e ciency of our algorithm in comparison to other published results
Chapter Test Generation for Path Delay Faults
Intro duction
The path delay fault mo del is extensively used since it represents the in uence of
distributed delays on the op eration of clo cked systems The complexity of test generation
for delay faults is rather high due to factors such as the large number of p ossible paths
large numb er of tests and the exp onential search space for test generation In this chapter
we present a novel test generation algorithm which is capable of e ciently generating
have robust and nonrobust tests for path delay faults in combinational circuits We
employed an e cient path selection pro cedure that targets a suitable subset of paths
from the enormously large number of p ossible paths in the circuit
Most of the delay fault testing metho ds rep orted hitherto arebasedonthe
relatively simple concept of the PODEM algorithm Schulz et al have demonstrated
an extended multiple backtrace pro cedure and the concept of static and dynamic learning
for path delay fault testing Park and Mercer have implemented a delaytest
generation algorithm based on the D algorithm for generating robust and nonrobust tests
Their algorithms use a valued hazard free logic system to prevent the invalidation of
a test due to hazard phenomena and to reduce the potential search space for delay test
ting for any generation Several non enumerative metho ds i e without explicitly accoun
sp eci c paths for test generation and fault simulation of path delay faults have recently
app eared in the literature
Our metho d uses a multiple backtrace pro cedure similar to that of Schulz et al
for satisfying the test generation ob jectives The new ideas incorp orated in our algorithm
are as follows
A new value logic system to derive robust and nonrobust tests for path delay
faults Section
Amultiple backtrace pro cedure to nd and resolvecon ictsatinternal no des rather
than at PIs This is illustrated by Example
Direct derivation of a test for the opp osite transition once a test for a path for a
Chapter Test Generation for Path DelayFaults
given transition is found This is illustrated by Examples and
Tests are generated for all paths or esp ecially in the case of to o many paths for
one longest and one shortest path p er line Section
A Value Logic System
Multi valued logic has been used by practically all researchers for test generation and
fault simulation of path delay faults In a recent pap er Bose et al have used a
ultiple paths Fuchs et al have
valued logic system for the test generation for m
intro duced valued logic for robust automatic test generation ATG and three valued
logic for nonrobust ATG Park and Mercer have used valued logic for robust test
generation The number of logic states used is a key factor that determines the
time and memory complexities of the algorithm fewer logic symb ols generally lead to less
complex implementations
We have used a value logic system i e S X FT S X RT XX G G for
alues are simply the generation of robust and nonrobust tests The initial seven logic v
a more explicit representation of Lin and Reddy s ve value system whereas signals
G and G are newly intro duced in our prop osed logic system Signal values S and S
sp ecify steady values and resp ectively forbothvectors without a static hazard glitch
in the signal Signals X and X represent the nal logic values and resp ectively
whereas the initial value is X don t care Signals RT and FT sp ecify rising and falling
transitions without a dynamic hazards The concepts of static and dynamic hazards are
in XX means don t care for both vectors G and G represent given
static hazards i e glitches and resp ectively
Derivation of Value Logic
Our goal is to derive an optimal logic system that will allowsimultaneous consideration of
robust and nonrobust tests In earlier literature a multi valued logic system
Chapter Test Generation for Path Delay Faults
has b een derived by manipulating three logic and X states whicharesimultaneously
considered in two consecutive time frames initial nal of the clo ck p erio d Similarly we
manipulate three logic and X states for three initial intermediate and nal sub
intervals within two clo ckperiodsin order to determine the presence of hazards between
two successive clo cks Thus we get p ossible transition states whicharegiven in
Table These states eventually collapse to a value logic system
In Table the transition states and in which the logic values are fully
are represented by unique values i e S G FT and S G RT resp ec sp eci ed
tively The comp osite states transition states and are absorb ed together and
are represented by X and X resp ectively since the nal value is known and the initial
or intermediate values are not fully sp eci ed The last states are collapsed to
a single logic value XX since the nal logic value is X don t care Signal values G
and G represent static hazards i e glitches and and are explicitly used for
generation of nonrobust tests
XX
X0 X1
00 10 010 01 11 101
S0 FT G0 RT S1 G1
Figure Prop osed value logic
Figure shows the pictorial representation of our prop osed value logic system in
which X covers S FT G X covers S RT G and XX covers both X and X
Following Agrawal et al in Table we have given the signal value representation
Chapter Test Generation for Path DelayFaults
Table Enumeration of logic states
State Possible Fully Comp osite
id states sp eci ed states
fS g
fG g
fFTg
fFTg
X fS G g
X fS FTg
XX fS G FTg
X fFT FTg
X fG FTg
fS g
fG g
fRTg
fRTg
X fRT RTg
X fS G g
X fRT G g
XX fS G RTg
X fRT S g
X
X
X X
X X
X X
X X
X
X
XXX
Chapter Test Generation for Path Delay Faults
Table Signal value representation
Name of Initial Final Hazard
signal value value value conditions
S no static hazard
X X hazard possible
FT no dynamic hazard
S no static hazard
X X hazard possible
RT no dynamic hazard
XX X X hazard possible
G static hazard
G static hazard
and their corresp onding logic values in b oth vectors
Hazards static or dynamic are timing anomalies in digital circuits and are caused by
inherent delays of the circuit elements A hazard mayinvalidate a delay test by declaring
a faulty circuit to be good Thus hazards play an imp ortant role in two pattern test
generation for delay faults For example a two input AND gate having one rising and
one falling transition at the inputs will give rise to a static hazard i e glitch if
the falling transition is delayed with resp ect to the rising transition Examples are given
in Figure showing the glitch generation
0 1 1 0 1 0 0 0 1 1 0 1
G0 G1
1 1 0 1 0 0
Figure Examples of glitch generation
Signal values G and G are explicitly used for the generation of nonrobust tests
Chapter Test Generation for Path DelayFaults
Consider the circuit of Figure Supp ose wehave to nd a test for the rising transition
on path AE shown in bold lines For propagating the transition through the OR gate
we need to justify a S on the o path sensitizing input D These conditions for robust
propagation are the same as given by Lin and Reddy Assume that the two pattern
test vector applied is V and V After simulation we will get a static hazard
G at D if the falling transition at C is delayed with resp ect to the rising transition at B
E provided that there is an The static hazard at D can app ear as a dynamic hazard at
excessive delay on path AE If the hazard at E coincides with the clo ck the correct logic
value will be latched and thus the test will be invalidated If there is no propagation
delayonC then the delay fault rising transition on path AE can b e detected and thus
V V will be a nonrobust test For generating a robust test we need to justify a S
signal at D and this can be obtained by assigning S to either input B or C
A E
B 01 D S0 C 10
G0
Figure Glitch causing a nonrobust test
Path Selection
There is a ma jor b ottleneck in selecting all p ossible paths for test generation and fault
simulation since as the circuit size increases the numb er of p ossible paths grows exp onen
tially with the numb er of lines In most practical cases the large numb er of paths makes
it imp ossible to consider all paths for the purp ose of delay fault testing Hence it maybe
necessary to fo cus on a subset of all p ossible paths There are several metho ds presented
in the literature like worst case path selection and threshold based path selection Li
et al have presented a p olynomial time algorithm to nd a minimum cardinality path
Chapter Test Generation for Path Delay Faults
set In their approach a set of paths is selected such that each line L is included in
at least one selected path P and the mo deled signal propagation delay along the path P
is maximum among all paths that contain L In recent pap ers it has b een shown
that the determination of an optimal clo cking period highly dep ends on the accuracies
of the estimated longest path delay and the shortest path delay in the circuit e g in
the case of wave pip elined combinational circuits Furthermore in a synchronous design
um delay of a path may be important For example there are instances where the minim
if the skew between the clo cks of two ip ops is larger than the combinational path
delay between them then incorrect data can be latched in the destination ip op In
general the delay of paths should be greater than a lower b ound that is determined by
the p ermissible skew of the clo ck signal Hence in this work wehaveintro duced a metho d
for selecting a subset of paths that covers all lines in the logic circuit at least once and
L as well as the shortest S p ossible path through each line includes the longest
The pro cedure for longest path selection is describ ed below for clarity
Consider the circuit given in Figure Each line is lab eled with two lab els The
two lab els namely level and depth of the line are its maximum distances in terms of
the number of logic levels from aPI and aPO resp ectively The lab els for level of each
line are computed in a breadth rst forward trace of the circuit during netlist reading
h line rst we lab el all primary outputs i e lines For computing the depth of eac
with the depth All inputs of a gate are lab eled by the depth of the output of the gate
plus Thus we assign lines and depth lines and depth lines and
depth and so on When a fanout stem is encountered it is lab eled bythemaximum
depth of its fanout branches plus Thus we assign depth to the fanout stem depth
to the fanout stem and so on Wethus continue the breadth rst backward trace of
the circuit till we reach primary inputs
First we b egin a depth rst trace for longest path selection from all PIs and mark
those lines as covered for which the enumerated path is the longest structural path Next
we enumerate the longest paths through intermediate lines which are not covered in the
mark all PIs as covered already enumerated paths During this path enumeration we
Chapter Test Generation for Path DelayFaults
1 [1,4]
2 [1,6] 16 [6,3] 17 [7,1] 20 [8,0] 13 [5,4]
12 [4,5] 18 [7,2] 3 [1,8] 14 [5,3] 21 [8,1] 6 [2,7] 7 [3,6] 19 [6,2] 22 [9,0]
4 [1,8] 8 [3,4] 15 [4,3]
5 [1,6] 9 [2,5] 10 [3,4]
11 [3,1]
Figure Example of path selection
In Figure starting from PI when we reach the fanout stem we cho ose the
fanout branch for depth rst enumeration since it has the maximum depth Continuing
the trace along line wereach a PO line through line Thus the path P
is found as the longest structural path through line We have employed the
following rule to mark whether or not a line on the path is covered by a longest path
the sum Rule In a circuit a line L wil l be markedas coveredthrough path P if
of level and depth of line L is equal to the number of logic levels in path P
Example Consider the path P given ab ove which is the
longest path through line The numb er of logic levels numb er of lines in path P is
The sum of the level i e and depth i e of line is whereas the sum of level
and depth for other lines is greater than Hence only line is covered by the longest
path P
Next the longest path through PI i e P is enumerated
andline is marked as covered Then the longest path through PI isenumerated i e
P In this case all lines of the path P are marked as covered
since they satisfy Rule Thus the longest path through each PI is enumerated and
corresp onding lines are marked as covered based on Rule These paths are shown in
Chapter Test Generation for Path Delay Faults
Table Longest path selection
Path Longest Lines
no path covered
the upp er half of Table Next weenumerate the longest path through the lines which
are not yet covered To nd the longest structural path through an internal line wemake
abackward trace toward PIs in a depth rst manner along the lines having maximum level
and a forward trace toward POs in depth rst manner along the lines having maximum
depth For example line is not covered by the longest paths enumerated from PIs For
cho osing the longest path through line we makeabackward trace and reach the PI
through lines and Making a forward trace along the maximum depth lines from
lines and Thus path P in a depth rst manner we reach the PO through
is enumerated and lines and are marked as covered following
Rule
All the chosen structural paths through each signal line are listed in Table Longest
path represents the longest enumerated path Lines covered denotes the lines for which
the enumerated path is the longest structural path The number of path delay faults is
twice the number of enumerated structural paths since for every path we consider b oth
rising and falling transitions at the source of the path In general it is not necessary to
eight representing delay for all lines They can be assigned their rise assume a unit w
Chapter Test Generation for Path DelayFaults
and fall delays as weights The ab ove analysis will then be rep eated twice once for rise
delay and then for the fall delay
In a similar manner for selecting the shortest paths through each line we trace the
circuit in both directions i e from PIs to POs and vice versa for assigning two lab els
depth depth to each line L which represent the minimum length in terms of logic
pi po
to any PI and PO Wecontinue the backward and forward traces along the levels from L
minimum depth lines for selecting the shortest paths
Test Generation
Given a target path and a transition at the input of the path we must sensitize the
path to propagate the transition In order to satisfy the primary ob jectives i e o path
sensitizing input values backtracing is carried out and PIs are assigned for obtaining a
two pattern test vector Our test generation metho d uses a multiple backtrace pro cedure
similar to that of Schulz et al Along with the multiple backtrace pro cedure we
hniques for detecting and resolving have used some novel and e cient backtracking tec
con icts on internal lines We do not target the generation of nonrobust tests explicitly
Once a robust test is generated for a path with a given transition wederive another test
for the opp osite transition by mo difying the robust test obtained In most cases the
derived test becomes a robust or nonrobust test for the opp osite transition on the same
path Details of the test generation algorithm and examples are given below
Pro cedure for Test Generation
The salientfeatures of the test generation pro cedure are as follows
The implication op eration is done with resp ect to the transition rising or falling at
the input of the path with all other inputs unsp eci ed XX The main ob jectiveof
this implication pro cedure is to determine whether or not the transition can robustly
propagate along the target path
Chapter Test Generation for Path Delay Faults
The o path inputs of the gates along the target path are then set to suitable
logic values in order to propagate the transition The rule used to set the o path
sensitizing inputs is as follows If the transition at a gate input along the path
is in the direction of the controlling value of the gate all side inputs of this gate
must have steady non controlling logic values if the transition is toward the non
ve transitions toward the non controlling controlling value all side inputs can also ha
value During this propagation phase if any one of the o path sensitizing inputs
has already been implied during the previous step and there is a con ict between
the implied logic value and the required sensitizing logic value then we immediately
conclude that no robust test is p ossible for this path delay fault If no con ict is
found the o path inputs with the assigned sensitizing logic values b ecome the
primary ob jectives Also we mark all fanout branches of a stem as assigned if the
stem is a part of the target path
It is b est to nd out any inconsistency in the primary ob jectives as early as p ossible
may so happ en that two or more primary ob jectives have con icting
Sometimes it
logic values and they are the fanout branches of the same stem In that case it is not
p ossible to generate a test and hence we eliminate such paths without attempting
test generation
Wehave not used controllability measures for cho osing the inputs as used in FAN
and PODEM Instead for the sake of simplicity we have used a heuristic
concept of fanin sorting i e we put all fanins of a gate g in an ascending order
attached to the gate g the lowest with resp ect to the level number in a linked list
level input at the head and the highest level input at the tail Hence when a choice
exists we rst select the input with the lowest level number
In order to satisfy the primary ob jectives webacktrace from primary outputs toward
primary inputs in a breadth rst manner This multiple backtrace pro cedure is the
most imp ortant asp ect of our algorithm The highest level ob jective generates the
previous level ob jectives and so on For example if we are required to satisfy a S
Chapter Test Generation for Path DelayFaults
logic value at the output of an AND gate then wecho ose the input having the lowest
level number in other words easiest to control and put that input and ob jective
in the level of the chosen line The other inputs are then put on the primary stack
along with the logic value to be satis ed This helps in backtracking to the last
choice if we fail to generate a test in the rst multiple backtrace pro cess Again for
example if we need to satisfy a S logic value at the output of an OR gate then we
put all inputs with logic value S in their corresp onding level ob jectives
During the backtrace op eration if we create a new ob jective on an input of a gate G
e immediately create another
and this input happ ens to b e a fanout branch then w
ob jective with the same logic value on the fanout stem After doing an implication
op eration we mark all fanout branches as tried Hence before setting an ob jective
on anyfanoutbranch during backtrace we rstcheck whether or not it has already
b een tried by previous ob jectives If so weintersect the already assigned logic value
on the stem with the required logic value on the fanout branches If con ict o ccurs
in the intersection then the fanout branch with the required logic value is pushed
to the secondary stack
As an example consider the circuit shown in Figure We need to satisfy the
brackets n n n etc
ob jectives F S and G X The value mentioned in
refers to the level number Supp ose that the ob jective F S is to b e satis ed rst
Wecho ose the input C as it has a lower level numb er assign C S and put the other
input A S in the primary stack which is used to store the untried alternatives
Since C is a fanout branch immediately it creates the previous level ob jective on
the stem B S After implication the fanout branches C and D will be marked
the input as tried When the next ob jective G X is considered we rst cho ose
D which has already been tried as the level number of D is lower than E After
intersection it leads to a con ict at the stem S X NULL Hence input D
with logic value X is pushed to the secondary stack and next input E is considered
Thus we create the new ob jective E X and the backtrace pro cedure will continue
Chapter Test Generation for Path Delay Faults
further toward primary inputs If all choices in the primary stack fail to generate
a test the ob jectives in the secondary stack are tried allowing the test generation
pro cess to consider all p ossible choices
A[n-1] F[n] C[n-2] S1 B[n-3] S1 X0 D[n-2] G[n] X0
E[n-1]
Figure Example of con ict at a stem
The complexity of the test generation algorithm dep ends on the number of back
tracks required in generating a test However the e ciency of test generation is
strongly in uenced by the order in which the signals in the target list are consid
ered for justi cation According to the existing literature a single stack has
been used for the backtrack op eration by all researchers In this work we use two
hoices for selecting inputs stacks primary and secondary which store alternativec
The primary stack contains line numbers with non con icting logic values and the
secondary stack contains line numbers with con icting logic values During the
backtrack rst we cho ose the last choice from the primary stack and after comple
tion of all choices we consider the secondary stack Through exp eriments we have
found that this metho d has a greater advantage over the use of single stack and it
drastically reduces the number of backtracks for generating a test
pseudo co de for the test generation algorithm is given in Figure The pro cedure The
for test generation is illustrated by the following example
Chapter Test Generation for Path DelayFaults
Testgen Path Transition
Imply w r t transition and other unspecified inputs
Propagate Transition propagate the transition along the target path
If there is conflict between implied logic value and the
transition on line k on target path then
Transition can not propagate along the path
No test possible Exit
Set primary objectives Find all primary objectives to be justified
If there is conflict between two or more primary objectives on the
then
fanout branches of the same stem
No test possible Exit
Fanin sorting puts the fanins of a gate in an ascending order
w r t the level number
Multiple backtrace backtrace from POs to PIs in a breadth first manner
for satisfying test generation objectives
Imply Implication w r t the PI assignments
If all primary objectives are satisfied
then test is found
else continue backtrace from the last choice assigned
Substitute primary objectives X X by S S and vice versa
Modified test vector replace X X by S S and reverse the
of the path
transition at source
Imply Implication w r t the new derived test vector
If all primary objectives are satisfied
then a test is found for the opposite transition
Figure Pseudo co de for the test generation algorithm
Chapter Test Generation for Path Delay Faults
Example Consider the circuit given in Figure where a test is to be generated
for the falling transition on path shown by the bold lines
During the implication op eration with resp ect to the falling transition at input the
fanouts and are marked as assigned and the implication evaluates the output of the
NAND gate as X Next the propagation phase generates a primary ob jective i e
OR gate For line X in order to robustly propagate the transition through the
robustly propagating the transition through the NAND gate the o path input
must be set to S But input has already been set to the logic value X during the
previous implication pro cedure Intersection of these two logic values S X S
do es not create any con ict and hence the primary ob jective S is obtained Thus
the transition is propagated along the target path and the primary ob jectives obtained
are X S S X All lines of the path and the fanout branches of stems
as assigned in order to avoid any further assignment of logic along the path are marked
values on them during backtrace Then we check for the existence of primary ob jectives
that are fanout branches and have con icting logic values to be justi ed In this case
and are fanout branches but b elong to di erent stems Hence we immediately assign the
corresp onding logic values to the fanout stems and create the new ob jectives X and
S whichhappen to b e primary inputs We do an implication on the stems and mark
the fanout branches and as tried Next webacktrace from the highest level ob jective
the lowest level X The input of NAND gate is considered rst since it has
number Since it has already been tried by another ob jective we compare its required
logic value X with the already assigned logic value S of the stem After intersection
S X S we assign S to the stem The next ob jective S can b e satis ed
by setting S but input has already b een marked as tried by the previous ob jective
X Thus after intersection we assign logic value S to the stem in the same manner
as describ ed ab ove After the backtrace completes we assign S S FT and
XX and do an implication with resp ect to the test vector Wehave a robust test since
all ob jectives are justi ed
Chapter Test Generation for Path DelayFaults
1 2 19 16 X1 4 5 23 11 3 8 21 S0 S1 20 6 15 17 13 X0 12 22 7 9 24 14 18
10
Figure Test generation Example
Robust Nonrobust Test for Opp osite Transition
Once we nd a robust test for a transition say rising on a target path instead of trying
to generate another test for the opp osite transition i e falling we derive another test
by substituting the X values X X in the rst test with steady values S S and
reversing the transition at the input of the target path The underlying principle is that
the second vector propagation vector of the two pattern test is a test for the stuck
stuck fault at the at fault on the primary input at the source of the transition The
PI is sensitized along the target path If the sensitizing condition remains unchanged
i e all PIs have values as in V except the PI at the source of the path the opp osite
transition will always reach the primary output along the target path Hence we replace
the non steady X values X X by the steady values S S in the generated test vector
to derive a new test vector for the opp osite transition on the target path In most cases
this mo di ed vector pair will b e a valid robust nonrobust test for the opp osite transition
In a few cases the derived test vector pair will not be either a robust or a nonrobust
of redundant stuck at faults on any one of the signal lines along test due to the presence
Chapter Test Generation for Path Delay Faults
the target path The following example illustrates the derivation of robust test for the
opp osite transition
Example Consider the circuit shown in Figure in whichwe rst generate a
test for the rising transition on the target path The primary ob jectives
to be justi ed for this path delay fault are X S and X The highest level
ob jective X will be justi ed by setting X Since the other two ob jectives are
already PI ob jectives we obtain the robust test XX X RT X S
ed by substituting S FT
The test for the opp osite transition falling can b e deriv
and S in the ab ove test Since the transition has b een reversed the primary ob jectives
along the path will also change The new set of the primary ob jectives will be S
X and S Then we do an implication with resp ect to the derived test XX
S FT S S and nd that all primary ob jectives are justi ed Hence
we obtain another test without explicitly executing the test generation pro cedure On
average we found that of the generated robust tests actual ly produce either a robust
osite transition for the ISCAS benchmark circuits or a nonrobust test for the opp
1 XX 8 4 16 2 13 X0 12 10 3 5 9 6 X1 X1 14 11 17 15 7
S1
Figure Derivation of test for opp osite transition Example
During the implication op eration we compare the primary ob jective logic values with
the implied logic values in order to determine the robustness nonrobustness of a test If
the implied logic values either are a subset S and G X S and G X of the
Chapter Test Generation for Path DelayFaults
primary ob jective logic values or are the same then the derived test will be a robust
test If at least one of the primary ob jective logic values is S S and the implied logic
value b ecomes G G then the derived test will be a nonrobust test for the opp osite
transition The following example illustrates the derivation of a nonrobust test for the
opp osite transition by mo difying the robust test
Example In Figure we rst generate a test for the rising transition on path
The primary ob jectives are X S and X After backtrace
obtain a robust test i e S RT The new set of primary ob jectives for the we
opp osite transition will be S X and S The derived test will be S
FT After implication we nd that the implied logic value of line is G i e static
hazard whereas its primary ob jective logic value is S Hence the derived test
will be a nonrobust test for the falling transition Thus once a robust test is derived
for a path with a given transition we are able to save a considerable amount of e ort
opp osite transition on the target by directly generating a robust nonrobust test for the
path
2 S1 10 8
1 3 X1 7 12 4 5 9 X1 11
6
Figure Nonrobust test derived from robust test Example
Exp erimental Benchmark Results
Wehave implemented the prop osed path delay test generation algorithm in the C language
ab out lines of co de on an IBM RS workstation In order to benchmark
Chapter Test Generation for Path Delay Faults
and demonstrate the e ciency of our test generator we have p erformed ATG for ro
bust and nonrobust tests on the ISCAS and the scan hold versions of the ISCAS
benchmark circuits
Table gives the results for ISCAS benchmarks Path faults is the number of
logical paths considered for test generation This is twice the number of the physical
or the purp ose paths selected to cover each line via the longest L path through it F
of comparison we have also given the test generation results when the path selection
pro cedure is mo di ed to cho ose the shortest S path through each line As exp ected in
general the coverage is higher for shorter paths Wehaveintegrated a fault simulator
in the system Once a robust or nonrobust test is generated immediately we do fault
simulation with resp ect to the test vector Both robust and nonrobust detection of path
delay faults are rep orted Robustly detected paths are then marked in the targeted path
list and hence not considered for further test generation The third and forth columns of
ber of robust and nonrobust tests generated by the test generator Table givethe num
within the backtrack limit of The fth and sixth columns give the number of path
faults which are robustly and nonrobustly tested from the targeted fault list while columns
seven and eight are for the non targeted faults The CPU time in seconds is given for the
complete ATPG pro cess For circuit c the numb er of nonrobustly detected paths was
extremely large even for a small numb er of tests and requires a large amount of CPU time
and memory for a successful completion Hence we have not considered the nonrobust
detection of paths during simulation
Our results in Table may be compared to two earlier works on test
included in Table We have generation for ISCAS benchmarks Their results are
given our results only for longest paths However since the numb er of mo deled path faults
and the machines used are di erent a direct comparison can not be made It may be
noticed that the fraction of mo deled path faults that are robustly tested by our metho d is
signi cantly higher than that rep orted in b oth previous pap ers For example
in our metho d the fraction of targeted path faults that are robustly tested ranges from
to with the average b eing The results rep orted by Schulz et al are
Chapter Test Generation for Path DelayFaults
Table Delay test results for ISCAS benchmarks
Tests Paths detected Paths detected
Circuit Path generated Targeted Non targeted
faults Rob Nrob Rob Nrob Rob Nrob CPU s
c L
S
c L
S
c L
S
c L
S
c L
S
c L
S
c L NA NA
S NA NA
c L
S
IBM RS
Table Comparison with other results
Our ATPG NEST Schulz et al
Circuit Target Tested CPU s Target Tested CPU sy Target Tested CPU sz
paths paths paths
c L
c L
c L
c L
c L
c L
c L
c L
IBM RS y SUN SPARC z Micro VAX
Chapter Test Generation for Path Delay Faults
also for the longest paths and the fraction of targeted path faults that are robustly tested
ranges from to whereas the average is only In Pomeranz et al the
p ercentage coverage will b e extremely low since it implicitly considers all p ossible paths
Our results show that the test generation for path delay faults can b e e ectively done for
both longest as well as shortest paths by the prop osed algorithms
Table presents the results of our algorithm for scan hold versions of ISCAS
benchmark circuits Path faults is the number of both rising and falling transitions on
ber of robust al l p ossible physical paths Under Our ATPG Rob nrob tests is the num
and nonrobust tests generated within the backtrack limit of Rob det is the number
of path faults which are robustly tested Nrob det is the number of path faults that
are nonrobustly tested by the fault simulator The CPU time in seconds given for the
IBM RS workstation includes the time for test generation and fault simulation
For the last eight b enchmarks shown in Table wehave considered only a subset of all
p ossible path faults since the total numb er of paths in these circuits was very large These
paths were obtained by the path selection algorithm given in Section and include one
shortest path p er line
For comparison we include the results of three other pap ers in Table
verages of robustly tested paths and CPU times All p ossible
which rep ort the co
path faults are mo deled in Bhattacharya et al and Bose et al Fuchs et al
have presented a highly e cientATPG algorithm called RESIST which considers all path
delay faults in the ISCAS b enchmark circuits Their metho d presents the b est available
results on path delay faults and the CPU time is given for SUN SPARCIPX For a direct
comparison CPU times must b e normalized for the corresp onding machine sp eeds Such
normalization has not b een done in Table However our ATPG algorithm app ears to
b e more e cient than the technique of Bose et al and the fault coverage is comparable
The CPU times rep orted in Bhattacharya et al and Fuchs et al are b etter than
our results
In RESIST an e cient sensitization technique has b een prop osed that sensitizes
common subpaths only once The metho d resulted in a substantial decrease in the number
Chapter Test Generation for Path DelayFaults
Table Test results for scan hold versions of ISCAS b enchmarks
Our ATPG
Circuit Path Rob nrob Rob Nrob CPU Paths CPU Paths CPU Paths CPU
faults tests det det sy det s det sz det sx
s
s
s
s
s
s
s
s
s
s
s
s
s n
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
Partial set of path faults y IBM RS DECstation z SUN SPARC
x SUN SPARCIPX
Chapter Test Generation for Path Delay Faults
of subpath sensitization steps The sensitization pro cedure has b een shown to give a
sp eed up factor that grows linearly with the circuit depth Compared to conventional
approaches RESIST is capable of detecting a signi cantly larger number of path delay
faults in less time The technique of sensitizing common subpaths only once may be
readily applied in our algorithm as well to obtain substantial sp eed up
In the BDD approach a combination of the conventional fully transitional path
ation and the single input transition SIT metho d provides FTP approach to path activ
a high coverage of robustly detectable path delay faults Every ma jor step in the test
generation pro cess consists of manipulation of Bo olean functions and do es not require
enumeration of input patterns or covers and hence the algebraic approach can be faster
than existing metho ds However it must be remembered that the time and memory
complexities of the BDD approach can b e impractical for some circuits This metho d
has b een applied to synchronous circuits also However results only for smaller ISCAS
benchmarks are rep orted
The novel ideas develop ed byussuch as the value logic system the e cientmultiple
ation of tests for the opp osite transition from a given backtrace technique and direct deriv
test can b e used to further enhance the p erformance of anydelay test generation package
Conclusion
In this chapter we have presented a novel path delay test generation algorithm which
incorp orates an e cient multiple backtrace pro cedure for signal value justi cation The
value logic system provides an e cientway of deriving b oth robust and nonrobust tests
Once we nd a robust test for a path delay fault we mo dify it to derive another test for
the opp osite transition In most cases the derived test is either a robust or a nonrobust
e are able to considerably test for the same path with the opp osite transition Thus w
reduce the test generation time A subset of paths is selected for test generation covering
all lines in the logic circuit at least once This subset includes the longest and shortest
paths through each line We use a fault simulator for robust and nonrobust detection of
Chapter Test Generation for Path DelayFaults
path faults
In the next chapter we will discuss a new coverage metric and a two pass test gen
eration metho d for path delay faults through the longest robustly testable path to cover
each signal line of the combinational logic circuits
Chapter
Line Delay Fault Mo del and Its
Coverage
In this chapter we prop ose a coverage metric and a two pass test generation metho d for
path delay faults in combinational logic circuits The coverage is measured for each line
with a rising and a falling transition However the test criterion is di erentfromthatof
the slow to rise and slow to fall transition faults The new test called the line delay test
is a robust path delay test for the longest sensitizable path pro ducing a given transition
twice the on the target line The maximum number of tests and faults is limited to
number of lines However the line delay test criterion resembles the path delay test and
not the gate or transition delaytest Using a two pass test generation pro cedure we b egin
with a minimal set of longest paths covering all lines and generate tests for them Fault
simulation is used to determine the coverage metric For uncovered lines in the second
pass several paths of decreasing length are targeted We present a theorem stating that
a redundantstuck at fault makes all path delay faults involving the faultylineuntestable
for either a rising or falling transition dep ending on the typ e of the stuck at fault The use
considerably reduces the e ort of delay test generation We give results of this theorem
on several benchmark circuits
Chapter Line Delay Fault Mo del
Intro duction
In this chapter wecombine relevant features of transition and path delay fault
mo dels and de ne line delay tests A rising line delay test will test the longest sensitizable
path passing through the target line pro ducing a rising transition on it Similarly a
falling line delay test is de ned The de nition of longest can be appropriately chosen
For example in the simplest case it can be the path with the largest number of gates
Alternatively gates can be weighted by their nominal delays However once the path is
y test selected the test generation is indep endent of the gate delays The criterion of dela
through the longest path has been used for diagnosis
The coverage is measured for all lines with two p ossible transitions Thus the max
imum number of faults or tests is twice the number of lines For example in c
we will consider only line delay faults whereas the total number of p ossible path
faults is Yet the test criterion is similar to the path delay fault and not
like the gate or transition delay fault In general a test will cover several lines This cov
applied to the rep orted metho ds that extract sensitizable erage metho dology can also b e
paths
Conventional path delay test generators attempt to derive robust tests for a subset
of paths in the circuit based on some path selection criterion suchastheworst case path
selection or threshold based path selection However a large numb er of these paths
may not be robustly testable and hence the test coverage of the targeted paths can be
very low e g only ab out paths in c are rep orted as robustly testable The
new coverage metric seeks to remove this de ciency by attempting to derive a pair of line
the delay tests for each line in the circuit A coverage of line delay faults gives
user the con dence that the longest sensitizable paths through each line in the circuit are
covered by the vectors The two pass test generation metho d prop osed here can achieve
this goal given su cient computational resources
The basic idea of an iterative approach for generating a robust test was rst prop osed
by Park and Mercer They have followed an approximate method where the search
Chapter Line DelayFault Mo del
space of the test generation pro cess is biased to nd a test along a path whose propagation
delay is greater than or equal to a prede ned threshold value Our metho d on the other
hand uses an exact method for generating a robust test for the longest testable path
through each line To facilitate the simultaneous consideration of robust and nonrobust
tests we have used the value logic system describ ed in Chapter
A ma jor improvement in the p erformance of a delay fault test generation algorithm
can be obtained by avoiding test generation for those path delay faults which are guar
veemployed the information on redundant stuck at faults anteed to b e untestable Weha
in the circuit provided by a stuck at fault test generator to avoid test generation for
a large number of untestable path delay faults We have achieved signi cant savings in
computational time by this novel approach
Line Delay Tests and Coverage Metric
A line delay test is de ned as a robust test for the longest sensitizable path passing
consider line through the target line pro ducing a given transition on the line One may
delay tests with resp ect to the rising as well as falling transitions on the target line The
motivation of de ning the line delay test is to determine the smallest incremental delay
asso ciated with a rising or falling transition at any line that can be robustly detected by
a test vector Let be the incremental delay of a rising or falling transition through
L
line L Then for detection of this delay fault
T T T T
L P C L C P
path P through which where T system clo ck period and T nominal delay of the
C P
L is tested From the ab ove relation we determine that the smallest incremental
delay fault on L can b e detected via the path through L having the longest nominal delay
T i e
P max
T T
L min C P max
Chapter Line Delay Fault Mo del
By sensitizing the longest path through L we are able to detect the delay fault of the
smallest size However simultaneous delay variations are p ossible for other gates on P
due to correlation with L Supp ose that the delays of other gates increase Then the
line delay test for L will detect a delay fault of even smaller size If the delays of other
gates reduce while that of L increases the sensitivity of the tests reduces Considering
correlation of delays this later case is less probable The basic assumption asso ciated
with the line delay fault mo del is that the delays of all gates are not reduced b elow their
nominal values
The ma jor advantage of this fault mo del is that the numb er of faults is limited to twice
the number of lines in the circuit Since the fault is tested along the longest propagation
path the system timing failures caused by the smallest lo calized delay defects or the
accumulation of distributed delay defects can be detected In the transition fault mo del
adelay test is obtained along any arbitrary path b ecause the size of delay fault is assumed
to b e large enough to b e tested via any path through the fault site In the gate delay fault
mo del one has to sp ecify the exact sizes of the delay defects and accurate information may
not b e always available Both transition and gate delay faults do not mo del the distributed
delay defects along a target path Our mo del on the other hand retains many advantages
of the transition and gate delay fault mo dels while alleviating the ma jor drawbackofthe
many paths to b e tested and the low fault coverage path delay mo del viz to o
Two Pass Test Generation
Finding the longest sensitizable and robustly testable path through a given delay fault
site is an NP hard problem We rst attempt to nd a robust test for the longest
structural path through a line If the path is not sensitizable then we try to nd a robust
test for successively shorter structural paths until a test for the longest sensitizable path
is found Given enough resources CPU time and memory this metho d guarantees to
nd atest for the longest sensitizable path through the line if such atest exists
same as
The rst pass of our two pass test generation strategy is essentially the
Chapter Line DelayFault Mo del
rep orted in Chapter Initially a simple path selection metho d is employed to obtain
a list of paths that cover all signal lines by their resp ective longest structural paths
This metho d of path selection has been explained in Chapter The multiple backtrace
pro cedure employing a value logic system is used to derive robust tests for these
targeted path faults Once a robust test is generated fault simulation is carried out to
obtain information on the robust detection of other path faults Whenever the simulator
the generated test vector pair each nds that a path in the circuit is robustly tested by
line on this path is examined to see if the vector pair satis es the criterion of b eing a line
delay test for any other line on that path If the robustly tested path happ ens to be the
longest structural path in the circuit through any line then that line can be marked as
covered since a line delay test has b een obtained for the line with resp ect to a rising falling
transition The fault coverage includes lines and transitions for which line delaytestswere
obtained
The line delay fault coverage at the end of the rst pass is generally low since many
structural paths are not robustly testable For each line that is not covered by the line
the rst pass we attempt to derive a robust test for the second longest delay tests in
structural path If a robust test exists for this path we mark the corresp onding line as
covered If a test is not p ossible for the second longest structural path then we go for the
third fourth etc successively shorter paths until we get a robust test Once a line delay
test is obtained for a line L through the Nth longest path P we mark line L as covered
L
The simulator then determines the other lines in the circuit for which the generated test
satis es the criterion for a line delay test The successive line segments following L along
e the tested path P will be marked as covered if the level numbers of these successiv
L
line segments di er only by This strategy usually obtains signi cantly improved line
delay fault coverage after the second pass The pro cedure for two pass test generation is
illustrated by the following example
Example Consider the circuit given in Figure Lines are numb ered through
The lab el of line l is l m n where m and n are level and depth resp ectively These
are the maximum distances in terms of the number of logic levels from primary inputs
Chapter Line Delay Fault Mo del
and primary outputs In the rst phase of the two pass test generation pro cedure we
select a list of paths that cover all signal lines through the longest propagation delay path
using the algorithm discussed in Section We assume that a unit delay is asso ciated
with each signal line There are a total of signal lines and hence wehave line delay
faults to be tested The list of longest paths selected in the rst pass is given below
1 [1,4] S1 2 [1,6] X0 16 [6,3] 17 [7,1] 20 [8,0] 13 [5,4]
12 [4,5] 18 [7,2] 3 [1,8] 14 [5,3] 21 [8,1] 6 [2,7] 7 [3,6] 19 [6,2] 22 [9,0] S1 X1 4 [1,8] 8 [3,4] S0 15 [4,3]
5 [1,6] 9 [2,5] 10 [3,4] XX
11 [3,1]
Figure Test generation for longest path through line
Chapter Line DelayFault Mo del
We try to derive robust tests for the ab ove selected paths and it is found that only
robust tests vector pairs are generated for the targeted path faults After fault
simulation with these robust tests we nd that line delay faults are covered These
are lines and whicharecovered for b oth rising and falling transitions
on them Hence the line delaycoverage at the end of the rst pass is only or
Consider line which has not been covered in the rst pass since the longest path
through line i e is not robustly testable with resp ect to b oth
of successively shorter paths rising and falling transitions We then enumerate the list
through line as listed below
longest path
We now derive a robust test for the falling transition on the path
which is one of the second longest paths through line as shown in Figure We
get a robust test as S X S FT and XX for this path using our test
generator and hence this test will b e a line delay test for the falling transition on line
Now the simulator is invoked and it is found that all which is now marked as covered
other line segments of the tested path will also b e marked as covered
since successive line segments di er in their levels only by Once a test is obtained for a
path with a given transition another test for the same path with the opp osite transition
is immediately derived with a small extra e ort Thus we get another test for the rising
transition on the same path by suitable substitution on the already derived test vector
i e S S S RT and XX which is a rising line delay test for line
been discussed The details of derivation of the test for the opp osite transition have
in Chapter At the end of the second pass our algorithm succeeds in obtaining
coverage of all line delay faults in the circuit by a total of derived tests vector
pairs The six line delay faults on lines and are found to b e untestable through
Chapter Line Delay Fault Mo del
any path for b oth rising and falling transitions giving a fault e ciency of
It may so happ en that there is no test for the second longest path through a given
line In that case we try to generate a test for the next longest or successively shorter
paths until we obtain a test for the longest robustly testable path Our main ob jectiveis
to cover all or most signal lines for delay defects through the longest sensitizable paths
In most other metho ds if it is not p ossible to derive a test for a target path then the
longest robustly next targeted path is tried However this do es not guarantee that the
testable path through each line in the circuit will b e tested
1 S1
2 X0 17 20 13 16
7 18 12 3 S1 14 21 6 4 19 22 8 10 15 5 XX 9
11
Figure Test generation for second longest path through line
N Longest Path Selection
Yen et al have presented an algorithm to nd the K longest paths of a directed acyclic
graph DAG Ju and Saleh presented an incremental algorithm for enumeration of
paths which is log linear in complexity Kundu has given a linear time complexity
algorithm that nds the next k longest or shortest paths of a directed acyclic graph
on demand without recomputing all previous paths However for simplicity of
path selection algorithm that is enumerative We enumerate implementation we use a
Chapter Line DelayFault Mo del
all possible paths through the target line L order the paths according to decreasing
length and retain only the N longest paths at anygiven time This brute force approach
is used only to demonstrate the e ectiveness of the new fault mo del In a pro duction
implementation any of the cited approaches can be used for e cient path selection
We rst trace backward in a breadth rst manner from line L toward PIs and mark
all signal lines from which there is a path to L We then trace forward from line L in a
manner toward POs and mark all signal lines that can be reached from L breadth rst
For each PI that has b een marked in the backward trace from L weenumerate all paths
starting at the PI and passing through L by traversing depth rst along only the marked
lines As each path is enumerated we store it in alinked list in decreasing order of path
lengths If the total number of p ossible paths through line L is greater than N then we
insert the N th path into the ordered list at the appropriate p osition and remove the
however is not last path from the list to retain only the N longest paths Our approach
suitable for handling circuits which have extremely large number of paths e g c
However one can implement Kundu s algorithm to overcome this problem
Elimination of Untestable Path Faults
In this section we present the integration of a stuck at fault test generator COM
PACTEST inourATPG system for the elimination of untestable path delay faults
The main ob jective of this approachistosave the unnecessary computational time sp ent
in generating tests for some of the untestable path delayfaults COMPACTEST though
based on PODEM is not primarily intended as a redundancy identi er It fails to identify
TPG some redundant faults Wehave employed COMPACTEST since this was the only A
to ol available to us Better results can b e obtained with more e cient programs for redun
dancy identi cation The following theorem relates to the identi cation
of untestable path delay faults
Theorem Consider an untestable redundant stuck at stuck at fault on
line k in a logic circuit Then all path delay faults for paths through line k and hence
Chapter Line Delay Fault Mo del
the line delay fault on line k for which a rising falling transition reaches line k will b e
untestable
Pro of We consider an untestable stuck at fault on line k The pro of for the
opp osite case is analogous Since the stuck at fault on line k is untestable the logic
function realized by the circuit is unaltered when we replace the logic value on line k with
a constant Replacing the logic value to a constant can also be viewed as a rising
delayed line k never attains the transition due to arrive at line k which is in nitely
value and hence is stuck at logic Thus if the stuck at on line k do es not alter
the go o d circuit b ehavior do es not cause an incorrect logic value at the output then an
in nitely delayed rising transition on line k also cannot cause an incorrect logic value at
the circuit output Hence all path delay faults through line k for which a rising transition
arrives on line k will b e untestable in the circuit
In a prepro cessing phase we run COMPACTEST for determining the redundant
stuck at faults and keep this information in a separate le After reading the circuit
e read the redundant faults from the le and mark the corresp onding lines netlist w
Before invoking test generation for a path delay fault we rst examine whether or not
any line along this path is redundant for stuck at faults Thus wesave a large amountof
computation time by avoiding test generation for untestable path faults This pro cedure
is explained in the following example
Example Consider the circuit given in Figure This is a highly redundant
contrived circuit for stuck at faults The faults notation for line stuck at
redundant by COMPACTEST and are proved to be
Considering for example the fault line stuck at we conclude that no test
can be obtained for the falling transition on any path passing through line However
a test may be p ossible for the rising transition on any path passing through this line
Hence we run the test generator to obtain a test for the rising transition on path
and nd X RT S and S to be a robust test If both stuck
on any line L then we conclude that all paths at and stuck at faults are redundant
passing through L are untestable for both rising and falling transitions In this way we
Chapter Line DelayFault Mo del
1 2 X0 12 10
4 9 5 11 S0 13 15 67 S0
8 14
3
Figure Elimination of untestable path delay faults
avoid some of the untestable path delay faults and make the ATPG pro cess faster For
example there are redundant stuck at faults in c circuit By employing this
information for eliminating untestable path delay faults we completed the two pass test
generation in seconds CPU time on IBM RS workstation as given in
Table whereas it to ok seconds when the redundancy information was not used
COMPACTEST to ok only seconds for identifying all redundancies in circuit c
Exp erimental Results
Wehave implemented the prop osed two pass test generation algorithm in the C language
of co de on an IBM RS workstation In order to benchmark
ab out lines
and demonstrate the e ciency of our algorithm we p erformed an exp erimental study of
the ISCAS and scan hold versions of ISCAS b enchmark circuits
Table gives the results for the ISCAS b enchmarks Total LDF denotes the total
number of line delay faults which is twice the number of lines in the circuit Red Flts
gives the number of redundant stuck at faults obtained by COMPACTEST which are
Chapter Line Delay Fault Mo del
Table Two pass test generation results for ISCAS benchmark circuits
Total Red Pass I Pass I I Final Total
Circuit LDF Flts Target Vec Paths LDF CPU Vec Paths LDF LDF CPU
Paths Tested Cov s Tested Cov Cov s
c
c
c
c
c
c
c y y y y y
c
s
s
s
s
s
s
s
s
s
s
s
s
s n
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
IBM RS COMPACTEST did not identify any redundant faults
y Pass I I incomplete
Chapter Line DelayFault Mo del
used to avoid test generation for untestable path delay faults The fourth column Target
Paths gives the number of logical paths considered for test generation in the rst pass
This is twice the number of the physical paths selected to cover each line via the longest
path The fth column Vec gives the number of robust tests vector pairs generated
in the rst pass within a backtrack limit of We have a fault simulator in the test
generation system Robustly detected paths are immediately marked in the targeted path
list and hence not considered for further test generation The sixth column Paths Tested
gives the total number of path faults detected robustly from the Target Paths as well
as from all other path faults as rep orted by the fault simulator LDF Cov seventh
column gives the numb er of line delay faults LDF detected in the rst pass The CPU
time in seconds is given for the rst pass in the eighth column The ninth column Vec
gives the number of additional robust test vectors generated in the second pass of test
generation For the second pass we have enumerated up to longest paths through
h line although more paths may exist for some lines Paths Tested gives the number of eac
additional paths tested robustly at the end of the second pass The eleventh column LDF
Cov gives the number of new line delay faults detected in the second pass The twelfth
column Final LDF Cov gives the total p ercentage line delay fault coverage obtained at
the end of two pass test generation The CPU time in seconds in the last column is for
the complete ATPG pro cess including b oth passes
For example wehave initially targeted longest paths Target Paths for circuit
of lines in c There is a total of line delay faults which is twice the number
the circuit In the rst pass of the test generation pro cess robust test vectors are
generated After simulation with these vectors we found that path delay faults in the
circuit are detected robustly and line delay faults LDF are detected in the rst pass
of the ATPG pro cess corresp onding to a line delay fault LDF coverage of After
the two pass test generation pro cess we obtain another extra robust tests which in
turn detect an additional path faults robustly and new line delay faults giving
a total coverage of The total time taken for the complete test generation pro cess
is seconds The line delay fault coverage is less than in many circuits primarily
Chapter Line Delay Fault Mo del
due to the backtrack limit employed by us in the test generation pro cess to keep the time
complexity manageable In other cases it is due to the path limit of used in pass II
The details are presented in Table Furthermore many circuits have a large number
of untestable line delay faults
COMPACTEST did not identify redundant stuck faults in some circuits although
these circuits are known to have several redundant faults Suchcasesareshown with
in Tables and The ATPG timings could improve considerably if all redundant
stuck faults are identi ed for these circuits Since our N longest path algorithm cannot
handle circuit c pass II remained incomplete for that circuit
We have given the statistics for line delay coverage e ciency in Table for the
ISCAS benchmark circuits Total LDF is the total number of line delay faults and is
twice the number of lines in the circuit Tested LDF gives the total number of line delay
faults tested after the two pass test generation pro cess The fourth column Untestable
due to Red stuck fault gives the numb er of redundant stuck at faults All paths untestable
ber of line delay faults which are proved to be untestable after trying to gives the num
generate a test for all p ossible paths through a given line Under the column Aborted due
to Backtrack limit we give the number of line delay faults dropp ed due to a backtrack
limit of and Path limit gives the number of line delay faults dropp ed due to the path
limit of For the faults ab orted due to the path limit wehave tried only the rst
longest paths and all of these were found untestable although more than paths can
be enumerated through these lines Fault e ciency gives the line delaycoverage e ciency
in p ercentage and is computed by dividing the sum of tested faults and proved untestable
total LDF faults with the
Limitations of the Fault Mo del
The strengths of the line delay fault mo del were discussed in Section and nowwewill
discuss some of its limitations In order to derive a line delay test for a given line we
need to target the longest structural path If that path is not robustly testable then wego
Chapter Line DelayFault Mo del
Table Statistics for line delay fault e ciency
Total Tested Untestable due to Ab orted due to Fault
Circuit LDF LDF Red stuck All paths Backtrack Path E ciency
fault untestable limit limit in
c
c
c
c
c
c
c
c
s
s
s
s
s
s
s
s
s
s
s
s
s n
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
COMPACTEST did not identify any redundant faults
Chapter Line Delay Fault Mo del
for the next longest path and so on until we nd a test for the longest robustly testable
path The limitation in this approach is that in addition to the longest robustly testable
path there could exist a nonrobust test for some longer path In such a case the robust
test would miss a line delay fault that only causes the longer nonrobustly testable path
to fail To overcome this limitation we may include any p ossible nonrobust tests for all
paths that are longer than the longest robustly testable path
our approach is that in case of distributed delay defects The second limitation of
our derived test set will fail to detect some of the delay faults which are not targeted
We consider only one path through any given line for determining a line delay test
However there may be some other paths of the same length or shorter through the
target line which have distributed delay defects exceeding the p ermissible propagation
paths and delay Consider the paths shown in Figure Let us assume that
are the longest structural paths through lines A and B resp ectively Let us further
assume that the smallest incremental delay fault that is detectable for each pathis i e
T T where T is the nominal delay of each of the paths If the incremental
C P P
delays of no des A and B are where is small then paths and will pass the
test However path has a fault which is not detected by our test vectors although it is
a detectable delay fault As stated earlier in Section the basic assumption asso ciated
all gates are not reduced b elow their with the line delay fault mo del is that the delays of
nominal values More than one faulty gate is due to correlation between delays of gates
In that case many gates in paths and will have increased delays and it is more likely
that the tests for these faults will show failures
There can b e several ways of dealing with the situation depicted in Figure When
there are several longest paths of equal length through a target line we can mo dify the
test generator to consider all such paths for increasing the con dence level in the tests
a potentially large number of paths to be tested in obtained However this can lead to
some circuits
There are two extreme cases of delay defect distributions One extreme is the com
pletely correlated case where all delays tend to increase prop ortionately Here the longest
Chapter Line DelayFault Mo del
3
1
A Δ−ε
2 Δ−ε
B
Figure Limitation of the fault mo del
delay paths fail Since line delay tests include tests for longest paths they are likely to
cover such defects The other extreme case is that of a spot defect where the delay of
one single gate is increased Here to o the line delay test retains its e ectiveness since it
is sp eci cally derived to detect the smallest incremental delay As the example of Figure
shows the e ectiveness of the line delay test can be questioned for certain cases in
wo extremes Alikely case is that of a local ly distributed delay defect If the between the t
correlation area of the delay defect is known then segments of lines spanning the defect
area can b e considered instead of single lines Such a mo del known as the segment delay
fault has b een discussed by Heragu et al The longest path criterion as used for the
line delay test will b e b ene cial for line segments also
Conclusion
We have presented a new coverage metric that requires a pair of robust tests termed as
line delay tests for each line in the circuit one for the rising and the other for the falling
transition on the line The main advantage of our new metric is that the maximum number
faults and tests is limited to twice the total number of lines in the circuit For test of
generation we begin with a minimal set of longest paths covering all lines and generate
robust tests for them Fault simulation is used to determine the line delay fault coverage
Chapter Line Delay Fault Mo del
A second pass of test generation considers those lines for which line delay tests could
not be generated in the rst pass and attempts to generate robust tests for successively
shorter paths through these lines until a test for the longest sensitizable path is found
Wehave presented a theorem stating that a redundantstuck at fault makes all path delay
faults involving that faulty line untestable for either a rising or falling transition dep ending
on the typ e of the stuck at fault The use of this theorem considerably reduces the e ort
of delay test generation An implementation of our algorithm achieved very high
t test generator line delay coverage e ciency for most b enchmark circuits More e cien
can b e implemented by using a dynamic path selection algorithm Several limitations
and p ossible improvements of the new coverage metric are discussed in Section
Chapter
Conclusions
Summary of Work Presented
As advances in technology push the p erformance of VLSI circuits to higher levels delay
fault testing b ecomes increasingly imp ortant for ensuring that the manufactured circuits
meet their timing sp eci cations Delay testing is also the only reliable metho d through
which manufactured pro ducts can be graded according to their p erformance measures
Development of e cient test generation and fault simulation algorithms for delay faults
has been an active area of research esp ecially in the last years A survey of related
ealed that there is considerable scop e for the development of new fault mo dels literature rev
and algorithms for delay fault testing in combinational as well as sequential circuits In
this thesis we have presented novel and e cient algorithms for test generation and fault
simulation of path delay faults in combinational logic circuits We have also presented a
new coverage metric for path delay fault testing that alleviates the problems of generally
lowpath delay fault coverage and the astronomically large number of paths
The advantages and limitations of various delay fault mo dels i e transition gate
The number of transition faults is delay and path delay were discussed in Chapter
limited to twice the total number of lines in the circuit and a test is obtained along any
arbitrary path because the size of the delay fault is assumed to b e arbitrarily large to b e
Chapter Conclusions
tested via any path through the fault site The tests are therefore not as e ective for
small and distributed delay faults In gate delay fault mo del one has to sp ecify the exact
sizes of delay defects Such information may not b e always available Both transition and
gate delayfaultsdo not mo del the cumulativee ect of delays along paths On the other
hand path delay fault mo del alleviates this de ciency However the astronomically large
numb er of p ossible paths in many circuits makes the test generation and fault simulation
pro cedures very complex Also many paths are not robustly testable which leads to
extremely low fault coverage
In Chapter wehave presented a novel path delay fault simulator for combinational
circuits The simulator is capable of simultaneously analyzing b oth robust and nonrobust
path delay faults Simple binary logic is used in place of the more complex tests for
multi valued logic used in most existing simulators This contributes to the reduction
of overall complexity of the algorithm The two valued algebra prop osed in this thesis
is simpler though not necessarily faster than the multi valued algebras A rule based
approach has b een develop ed which identi es all robust and nonrobust paths detected by
atwo pattern test while backtracing from primary outputs to primary inputs in a depth
rst manner Exp erimental results for b enchmark circuits demonstrate the p erformance
of the simulator for deterministic as well as random test vectors All path delay faults are
implicitly considered for determining the fault coverage
edevelop ed an e cient test generation algorithm for path delay faults
In Chapter w
in combinational logic circuits which incorp orates the multiple backtrace pro cedure for
signal value justi cation A new value logic system provides the capability of deriving
b oth robust as well as nonrobust tests Once a robust test is found for some path with
a given transition our algorithm derives another test with minimal extra e ort The
derived test in most cases is either a robust or nonrobust test for the same path with
opp osite transition Thus we are able to considerably reduce the test generation time A
subset of paths is selected for test generation covering each line of the logic circuit at least
longest and shortest paths through each line We have once This subset includes the
integrated our fault simulator with the test generator to determine robust and nonrobust
Chapter Conclusions
detection of path faults from either a given target set or all path faults Exp erimental
results on several benchmark circuits are given Also a comparison to other published
results is provided
In Chapter we prop osed a new coverage metric called line delay fault coverage
and a two pass test generation metho d for path delay faults in combinational circuits The
coverage is measured for each line with rising and falling transitions The new test called
line delay test is a path delay test for the longest robustly testable path pro ducing a
of this line delay fault mo del is given transition on the target line The main advantage
that the maximum number of faults is limited to twice the total number of lines in the
circuit Since the fault is tested along the longest propagation delay path the system
timing failures caused by the smallest lo calized delay defects sp ot defects and most of
the distributed delay defects are detected Our mo del thus retains many advantages of
the transition and gate delay fault mo dels while alleviating the ma jor drawback of the
viz to o many paths to be tested and the low fault coverage In the path delay mo del
rst pass of the ATPG we b egin with a minimal set of longest paths covering all lines
and attempt to generate robust tests for them Fault simulation is used to determine
the line delay fault coverage The second pass considers those lines for which a line
delay test could not b e generated in the rst pass and attempts to generate robust tests
for successively shorter paths through these lines until a test for the longest robustly
ve employed information on redundantstuck faults to avoid testable path is found Weha
test generation for a large number of untestable path faults An implementation of our
algorithm achieved very high line delay coverage e ciency for most benchmark
circuits
Future Work
The rapidly advancing eld of delay testing has b ecome one of the primary areas of interest
in digital circuit testing There are numerous challenging problems to be solved in this
area The following are some p ossible future extensions of this research
Chapter Conclusions
During the last few years a considerable number of test generation and fault simu
lation metho ds for path delay faults have been develop ed for combinational or full scan
versions of sequential circuits Path delay fault testing for non scan and partial scan se
quential circuits is also addressed in several pap ers The
rule based approach whichuses the simple binary logic for fault simulation of path delay
tial circuits Also the novel faults describ ed in Chapter can be extended for sequen
ideas presented in Chapter i e the value logic system to facilitate simultaneous gen
eration of robust and nonrobust tests and a test for the opp osite transition by mo difying
a generated robust test etc can be incorp orated to make an e cient path delay test
generation system for non scan and partial scan sequential circuits
As describ ed in Chapter we target the longest structural path to derive a line delay
test and if it is not robustly testable we then try to cover successively shorter paths until
we nd a test for the longest robustly testable path The longest path may not b e robustly
testable whereas there may exist a nonrobust test for the path delay fault Hence our
algorithm can be mo di ed to also include p ossible nonrobust tests for all paths that are
longer than the robustly testable path
The time and memory complexities of test generation and fault simulation metho ds
y fault testing are larger than those for stuck at fault testing The implementation for dela
of stuck at fault ATPG algorithms in parallel and distributed environments have been
successful However such parallel and distributed algorithms for test
generation and fault simulation of delay faults have not been rep orted This is another
p ossible direction for fruitful future research
We hop e that the novel ideas and algorithms prop osed in this thesis will nd appli
cation in the development of e cient CAD to ols for delay fault testing and simulation of
real life VLSI circuits
Bibliography
M A Abramovici P R Menon and D T Miller Critical Path Tracing An
Alternative to Fault Simulation IEEE Design Test of Computers Vol No
pp February
M A Abramovici M A Breuer and A D Friedman Digital Systems Testing and
Testable Design Computer Science Press New York
P Agrawal V D Agrawal and S C Seth Generating Tests for Delay Faults in
Test of Computers Vol pp March
Non Scan Circuits IEEE Design
P Agrawal V D Agrawal and S C Seth A New Metho d for Generating Tests
for Delay Faults in Non Scan Circuits in Proc of th Int l Conf on VLSI Design
India pp January
V D Agrawal and S C Seth Test Generation for VLSI Chips Los Alamitos CA
IEEE Computer So ciety Press
est Generation on
P Agrawal V D Agrawal and J Villoldo Sequential Circuit T
a Distributed System in Proc th Design Automation Conf pp June
Z Barzilai and B K Rosen Comparison of AC Self Testing Pro cedures in Proc
Int l Test Conf pp Octob er
Bibliography
J Benkoski E V Meersch L J M Claesen and H D Man Timing Veri cation
Using Statically Sensitizable Paths IEEE Trans on CAD Vol No pp
Octob er
D Bhattacharya P Agrawal and V D Agrawal Test Generation for Path Delay
Faults Using Binary Decision Diagrams IEEE Trans on Computers Vol No
pp March
S Bose P Agrawal and V D Agrawal Logic Systems for Path Delay Fault Test
O DAC pp September
Generation in Pro c of EUR
S Bose P Agrawal and V D Agrawal Generation of Compact Delay Tests by
Multiple Path Activation in Pro c IEEE Int l Test Conf pp Octob er
S Bose P Agrawal and V D Agrawal Path DelayFault Simulation of Sequential
Circuits IEEE Trans on VLSI Systems Vol No pp December
S Bose P Agrawal and V D Agrawal DelayFault TestabilityEvaluation Through
Timing Simulation in ThirdGreat Lakes Symposium on VLSI Michigan pp
March
S Bose P Agrawal and V D Agrawal The Optimistic Up date Theorem for Path
Delay Testing in Sequential Circuits Journal of Electronic Testing Theory and
Applications Vol pp August
S Bose and V D Agrawal Sequential Logic Path DelayTest Generation by Sym
b olic Analysis in Proc th Asian Test Symp Bangalore India pp
November
D Brand and V S Iyengar Identi cation of RedundantDelayFaults IEEE Trans
on CAD Vol No pp May
Bibliography
F Brglez A Neural Netlist of Combinational Benchmark Circuits and aTarget
Translator in FORTRAN in Proc of the Int l Symp on Circuits and Systems pp
June
F Brglez D Bryan and K Kozminski Combinational Pro les of Sequential Bench
mark Circuits in Proc of the Int l Symp on Circuits and Systems pp
May
O Bula J Moser J Trinko M Weismann and F Woytowich Gross Delay De
fect Evaluation for a CMOS Logic Design System Pro duct IBM Jour Research
Development Vol pp March
J L Carter V S Iyengar and B K Rosen E cientTest Coverage Determination
for DelayFaults in Proc IEEE Int l Test Conf pp September
T J Chakrab orty V D Agrawal and M L Bushnell Path DelayFault Simulation
Algorithms for Sequential Circuits in Pro c of Asian Test Symp osium pp
T J Chakrab orty V D Agrawal and M L Bushnell DelayFault Mo dels and Test
Generation for Random Logic Sequential Circuits in Proc th Design Automation
Conf pp June
T J Chakrab orty V D Agrawal and M L Bushnell Design for Testability for
aults in Sequential Circuits in Proc th Design Automation Conf
Path Delay F
pp June
S T Chakradhar M A Iyer andV D Agrawal Energy Mo dels for DelayTesting
IEEE Trans on CAD Vol No pp June
S T Chakradhar V D Agrawal and M L Bushnell Toward Massively Parallel
Automatic Test Generation IEEE Trans on CAD Vol No pp
September
Bibliography
S T Chakradhar V D Agrawal and M L Bushnell Neural Models and Algorithms
for Digital Testing Boston Kluwer Academic Publishers
S T Chakradhar V D Agrawal and S G Rothweiler A Transitive Closure
Algorithm for Test Generation IEEE Trans on CAD Vol No pp
July
H Chang and J A Abraham VIPER An E cient Vigourously Sensitizable Path
Extractor Pro c th Design Automation Conf pp June
H C Chen and D Du Path Sensitization in Critical Path Problem IEEE Trans
on CAD Vol No pp February
ransition Fault Simulation for Sequential Circuits in Proc IEEE
K T Cheng T
Int l Test Conf pp Octob er
K T Cheng and V D Agrawal Uni ed Methods for VLSI Simulation and Test
generation Boston Kluwer Academic Publishers
K T Cheng S Devadas and K Keutzer Robust Delay Fault Test Generation and
Synthesis for Testability Under a Standard Scan Design Metho dology in Proc th
Design Auto Conf pp June
K T Cheng S Devadas and K Keutzer A Partial Enhanced Scan Approach
t l Test
to Robust Delay Fault Test Generation for Sequential Circuits in IEEE In
Conf pp Octob er
S W Cheng H Chen D H C Du and A Lim The Role of Long and Short Paths
in Circuit Performance Optimization in Pro c th Design Automation Conf pp
June
S Devadas Delay Test Generation for Synchronous Sequential Circuits in Proc
IEEE Int l Test Conf pp Octob er
Bibliography
S Devadas and K Keutzer Synthesis of Robust Delay Fault Testable Circuits
Theory IEEE Trans on CAD Vol No pp January
S Devadas and K Keutzer Validatable Nonrobust Delay Fault Testable Circuits
Via Logic Synthesis IEEE Trans on CAD Vol No pp Decem
ber
S Devadas and K Keutzer Design of Integrated Circuits Fully Testable for Delay
Faults and Multifaults in Proc IEEE Int l Test Conf pp Octob er
S Devadas and K Keutzer Synthesis and Optimization Pro cedures for Robustly
estable Combinational Logic Circuits in Pro c th Design Autom
Delay Fault T
Conf pp June
D H C Du S H C Yen and S Ghanta On the General False Path Problem in
Timing Analysis in Proc th Design Autom Conf pp June
E B Eichelb erger Hazard Detection in Combinational and Sequential Switching
Circuits IBM Jour Research Development Vol No pp March
F Fink K Fuchs and M H Schulz Robust and Nonrobust Path Delay Fault
Vol
Simulation byParallel Pro cessing of Patterns IEEE Trans on Computers
pp December
K Fuchs F Fink and M H Schulz DYNAMITE An E cient Automatic Test
Pattern Generation System for Path Delay Faults IEEE Trans on CAD Vol
No pp Octob er
K Fuchs M Pabst and T Rossel RESIST A Recursive Test Pattern Generation
Algorithm for Path DelayFaults Considering Various Test Classes IEEE Trans on
CAD Vol No pp December
H Fujiwara and T Shimono On the Acceleration of Test Generation Algorithms
IEEE Trans on Computers Vol C No pp December
Bibliography
H Fujiwara Logic Testing and Design for Testability MIT Press Cambridge MA
H Fujiwara and T Inoue Optimal GranularityofTest Generation in a Distributed
System IEEE Trans on CAD Vol No pp August
M A Gharayb eh M L Bushnell and V D Agrawal Classi cation and Test
Generation for Path Delay Faults Using Single Stuck Fault Tests in Pro c IEEE
Int l Test Conf pp Octob er
wal Parallel Concurrent Path
M A Gharayb eh M L Bushnell and V D Agra
DelayFault Simulation Using Single Input Change Patterns in Proc th Int l Conf
on VLSI Design Bangalore India pp January
M A Gharayb eh M L Bushnell and V D Agrawal An Exact Non Enumerative
Fault Simulator for Path Delay Faults in Proc IEEE Int l Test Conf Octob er
Also in Proc TECHCON September
A Ghosh S Devadas and A R Newton Test Generation and Veri cation for
Highly Sequential Circuits IEEE Trans on CAD Vol No pp May
est Pattern
J Giraldi and M L Bushnell EST The New Frontier in Automatic T
Generation in Proc th Design Automation Conf pp June
P Girard C Landrault S Pravossoudovitch Delay Fault Diagnosis by Critical
Path Tracing IEEE Design Test of Computers Vol No pp December
P Girard C Landrault S Pravossoudovitch An Advanced Diagnostic Metho d for
DelayFaults in Combinational Faulty Circuit Jour Electronic Testing Theory and
Applic Vol No pp June
Bibliography
C T Glover and M R Mercer A Metho d of DelayFault Test Generation in Pro c
th Design Automation Conf pp June
C T Glover and M R Mercer A Deterministic Approach to Adjacency Testing
for DelayFaults in Proc th Design Automation Conf pp June
P Go el An Implicit Enumeration Algorithm to Generate Tests for Combinational
Logic Circuits IEEE Trans on Computers Vol C No pp March
L H Goldstein Controllability and Observability Analysis of Digital Circuits
Circuits and Systems Vol CAS No pp September
IEEE Trans on
C T Gray W Liu and R K Cavin Timing Constraints for Wave Pip elined
Systems IEEE Trans on CAD Vol No pp August
T Hayashi K Hatayama K Sato and T Natab e A Delay Test Generator for
Logic LSI in Proc IEEE Int l Symp on Fault Tolerant Computing pp
June
Fault Cov
K Heragu Approximate and Statistical Metho ds to Compute Delay
erage Master s Thesis Dept of ECE Rutgers University New Brunswick New
Jersey
K Heragu M L Bushnell and V D Agrawal An E cient Path Delay Fault
Coverage Estimator in Proc st Design Automation Conf pp June
K Heragu V D Agrawal and M L Bushnell Fault Coverage Estimation byTest
Vector Sampling IEEE Trans on CAD Vol No pp May
Bibliography
K Heragu J H Patel and V D Agrawal Improving Accuracy in Path Delay
Fault Coverage Estimation in Proc th Int l Conf on VLSI Design Bangalore
India pp January
K Heragu J H Patel and V D Agrawal Segment Delay Faults A New Fault
Mo del in Proc th IEEE VLSI Test Symposium pp April
M Henftling H C Wittman and K J Antreich Path Hashing to Accelerate Delay
Fault Simulation in Pro c st Design Autom Conf pp June
Hsieh R A Rasmussen L J Vidunas and W T Davis Delay Test Gener
E P
ation in Proc th Design Automation Conf pp June
V S Iyengar B K Rosen and I Spillinger Delay Test Generation Concepts
and Coverage Metrics in Proc IEEE Int l Test Conf pp Septemb er
V S Iyengar B K Rosen and I Spillinger Delay Test Generation Concepts
and Coverage Metrics in Proc IEEE Int l Test Conf pp Septemb er
N K Jha et al Synthesis of Multi level Combinational Circuits for Complete Ro
y Fault Testability in Pro c Int l Symp on Fault Tolerant Comp
bust Path Dela
July
Y Ju and R Saleh Incremental Techniques for Identi cation of Statically Sensi
tizable Critical Paths in Pro c th Design Automation Conf pp June
B Kap o or An E cient Metho d for Computing Exact Path DelayFault Coverage
in Proc European Design Automation Conf pp March
K Keutzer S Malik and A Saldanha Is Redundancy Necessary to Reduce De
No pp April
lay IEEE Trans on CAD Vol
T Kirkland and M R Mercer A Top ological Search Algorithm for ATPG in
Proc th Design Automation Conf pp June
Bibliography
K Kishida F Shirotori Y Ikemoto S Ishiyama and T Hayashi A Delay Test
System for High Sp eed Logic LSI s in Proc rd Design Automation Conf pp
July
S Ko epp e Mo deling and Simulation of Delay Faults in CMOS Logic Circuits in
Proc IEEE Int l Test Conf pp Octob er
Z Kohavi Switching and Finite Automata Theory McGraw Hill New York
rontier for LSSD Test Systems in
B Konemann et al Delay Test The Next F
Pro c IEEE Int l Test Conf pp Octob er
B Konemann J Mucha and G Zwieho Built in Test for Complex Digital Inte
grated Circuits IEEE Jour of Solid state Circuits Vol SC No pp
June
S Kundu S M Reddy On the Design of Robust Testable CMOS Combinational
Logic Circuits in Pro c Int l Symp on Fault Tolerant Comp pp July
S Kundu S M Reddy and N K Jha On the Design of Robust Multiple Fault
CMOS Combinational Logic Circuits in Pro c of ICCAD pp
Testable
November
S Kundu S M Reddy and N K Jha Design of Robustly Testable Combinational
Logic Circuits IEEE Trans on CAD Vol No pp August
S Kundu An Incremental Algorithm for Identi cation of Longest Shortest Paths
Integration The VLSI Journal Vol pp
W K Lam A Saldanha R K Brayton and A L Sangiovanni Vincentelli Delay
Fault Coverage and Performance Tradeo s in Proc th Design Automation Conf
pp June
Bibliography
J D Lesser and J J Shedletsky An Exp erimental Delay Test Generator for LSI
Logic IEEE Trans on Computers Vol C No pp March
Y Levendel and P R Menon Transition Faults in Combinational Circuits Input
Transition Test Generation and Fault Simulation in Pro c th Int l Symp on Fault
Tolerant Comp pp July
W N Li S M Reddy and S K Sahni On Path Selection in Combinational Logic
Circuit IEEE Trans on CAD Vol No pp January
Delay Faults Using
C C Liaw S Y Su and Y K Malaiya Test Generation for
Stuck at Fault Test Set in Proc IEEE Int l Test Conf pp November
C J Lin and S M Reddy On DelayFault Testing in Logic Circuits IEEE Trans
on CAD Vol CAD No pp September
L R Liu H C Chen and D H C Du The Calculation of Signal Stable Ranges
in Combinational Circuits IEEE Trans on CAD Vol No pp
August
U Mahlstedt J Alt and I Hollenbeck Deterministic Test Generation for Non
Classical Faults on the Gate Level in Proc th Asian Test Symp Bangalore India
pp November
Jacob and L M Patnaik A Novel Path Delay Fault Simulator
A K Ma jhi J
using Binary Logic VLSI Design An Int l Jour Custom Chip Design Simulation
and Testing Vol No pp
A K Ma jhi J Jacob L M Patnaik and V D Agrawal An E cient Automatic
Test Generation System for Path DelayFaults in Combinational Circuits in Pro c
th Int l Conf on VLSI Design New Delhi India pp January
Bibliography
A K Ma jhi J Jacob L M Patnaik and V D Agrawal On Test Coverage of
Path Delay Faults in Pro c th Int l Conf on VLSI Design Bangalore India pp
January
A K Ma jhi V D Agrawal J Jacob and L M Patnaik Line Coverage of Path
DelayFaults submitted to IEEE Trans on VLSI Systems under review
Y K Malaiyaand R Narayanaswamy Mo deling and Testing for Timing Faults in
IEEE Design Test of Computers Vol No
Synchronous Sequential Circuits
pp November
W Mao and M D Ciletti A Variable Observation Time Metho d for Testing Delay
Faults in Pro c th Design Automation Conf pp June
W Mao and M D Ciletti A Quantitative Measure of Robustness for Delay Fault
Testing in Pro c of ICCAD pp November
E J McCluskey Introduction to Theory of Switching Circuits McGraw Hill
P C McGeer et al Timing Analysis and Delay Fault Test Generation Using
Pro c of ICCAD pp November
Path Recursive Functions in
P C McGeer and R K Brayton E cient Algorithms for Computing the Longest
Viable Path in a Combinational Network in Pro c th Design Autom Conf pp
June
A Miczo Digital Logic Testing and Simulation NewYork Harp er and Row
E S Park and M R Mercer An E cient Delay Test Generation System for
Combinational Logic Circuits IEEE Trans on CAD Vol No pp
July
E S Park and M R Mercer Robust and Nonrobust Tests for Path DelayFaults in
aCombinational Circuit in Pro c IEEE Int l Test Conf pp September
Bibliography
E S Park M R Mercer and T W Williams The Total DelayFault Mo del and
Statistical Delay Fault Coverage IEEE Trans on Computers Vol No pp
June
S Patil An Automatic Test Pattern Generator for DelayFaults in Logic Circuits
Master s Thesis Dept of Elect and Comp Engg University of Iowa May
S Patil and S M Reddy A Test Generation System for Path Delay Faults in
Pro c Int l Conf on Computer Design pp Octob er
S Patil and P Banerjee A Parallel Branch and Bound Algorithm for Test Gener
on CAD Vol No pp March
ation IEEE Trans
S Perremans L Claesen and H D Man Static Timing Analysis of Dynamically
Sensitizable Paths in Proc th Design Autom Conf pp June
I Pomeranz L N Reddy and S M Reddy COMPACTEST A Metho d to Gen
erate Compact Test Sets for Combinational Circuits IEEE Trans on CAD Vol
No pp July
I Pomeranz and S M Reddy An E cient Non Enumerative Metho d to Estimate
Path Delay Fault Coverage in Pro c Int l Conf on CAD pp November
umerative Test
I Pomeranz S M Reddy and P Uppaluri NEST A Non En
Generation Metho d for Path DelayFaults in Combinational Circuits in Pro c th
Design Autom Conf pp June
I Pomeranz L N Reddy and S M Reddy SPADES A Simulator for Path
Delay Faults in Sequential Circuits in Proc of European Design Automat Conf
pp September
Bibliography
I Pomeranz and S M Reddy On Achieving a Complete Fault Coverage for Se
quential Machines Using the Transition Fault Mo del in Proc th Design Automa
tion Conf pp June
A K Pramanick Delay Testing and Design for Testability for Delay Faults in
Combinational Circuits Ph D Thesis Dept of Elect and Comp Engg University
of Iowa May
A K Pramanick and S M Reddy On the Detection of Delay Faults in Pro c
pp Octob er
IEEE Int l Test Conf
A K Pramanick and S M Reddy On the Computation of the Ranges of Detected
DelayFault Sizes in Pro c of ICCAD pp November
A K Pramanick and S M Reddy E cient Multiple Path Propagation Tests for
Delay Faults Jour Electronic Testing Theory and Applic Vol pp
December
L N Reddy Compact Test Sets for Digital Logic Circuits Ph D Thesis Dept
of Elect and Comp Engg University of Iowa August
S M Reddy C J Lin and S Patil An Automatic Test Pattern Generator for the
pp November
Detection of Path DelayFaults in Pro c Int l Conf on CAD
C H Roth Fundamentals of Logic Design th Edition West Publishing Company
K Roy J A Abraham K De and S Lusky Synthesis of Delay Fault Testable
Combinational Logic in Pro c of ICCAD pp November
A Saldanha R K Brayton and A Sangiovanni Vincentelli Equivalence of Ro
bust Delay Fault and Single Fault Test Generation in Pro c th Design Autom
Conf pp June
Bibliography
J Savir and W H McAnney Random Pattern Testability of DelayFaults IEEE
Trans on Computers Vol No pp March
M H Schulz F Fink and K Fuchs Parallel Pattern Fault Simulation of Path
DelayFaults in Pro c th Design Automation Conf pp June
M H Schulz K Fuchs and F Fink Advanced Automatic Test Pattern Techniques
for Path DelayFaults in Pro c Int l Symp on Fault Tolerant Comp Symp pp
July
M H Schulz and F Brglez Accelerated Transition Fault Simulation in Pro c
th Design Automation Conf pp June
M H Schulz E Trischler and T M Sarfert SOCRATES A Highly E cient
Automatic Test Pattern Generation System IEEE Trans on CAD Vol No
pp January
I Shaik and M L Bushnell Circuit Design for Low Overhead Delay Fault BIST
Using Constrained Quadratic Programming in Proc VLSI Test Symposium
pp April
J Sienicki M L Bushnell P Agrawal and V D Agrawal An Asynchronous
est Genaration on a Network of Workstations in
Algorithm for Sequential Circuit T
Proc th Int l Conf on VLSI Design New Delhi India pp January
G L Smith Mo del for Delay Faults Based on Paths in Pro c IEEE Int l Test
Conf pp Octob er
M K Srinivas Functional Test Generation for Synchronous Sequential Circuits
Ph D Thesis Dept of Computer Science and Automation Indian Institute of Science
Bangalore India
T M Storey and J W Barry Delay Test Simulation in Pro c th Design
Autom Conf pp June
Bibliography
P R Sureshkumar J Jacob M K Srinivas and V D Agrawal FASSAD Fault
Simulation with Sensitivities and Depth First Propagation in Proc nd Asian Test
Symp Beijing China pp November
K D Wagner The Error Latency of DelayFaults in Combinational and Sequential
Circuits in Proc IEEE Int l Test Conf pp November
J A Waicukauski E Lindblo om B K Rosen and V S Iyengar Transition Fault
Simulation IEEE Design Test of Computers Vol No pp April
J A Waicukauski P A Shup e D J Giramma and A Matin ATPG for Ultra
Large Structured Designs in Pro c IEEE Int l Test Conf pp Octob er
E cient Algorithms for Extracting the K
S H Yen D H Du and S Ghanta
Most Critical Paths in Timing Analysis in Pro c th Design Automation Conf
pp July
Vita
Ananta Kumar Ma jhi
Ananta was born in Orissa on August He obtained B Sc degree in Electrical
Engineering from College of Engg and Technology O U A T Bhubaneswar Orissa in
During he worked as a Lecturer in Electrical Engg DepartmentatIndira
Gandhi Institute of Technology Sarang Talcher Orissa He obtained M Tech degree
in Electronics Engg from Institute of Technology Banaras Hindu University Varanasi
India in During he pursued his Ph D degree in Electrical Communication
Engg Department at Indian Institute of Science Bangalore India Presently he is
Pro duct Engineering Division of Texas Instruments India Bangalore His working in
researchinterests include the CAD for VLSI Design Simulation Automatic Test Pattern
Generation ATPG and Design for Testability DFT for logic circuits
Email ananta india ti com
Publications
A K Ma jhi J Jacob L M Patnaik and V D Agrawal An E cient Automatic
Test Generation System for Path DelayFaults in Combinational Circuits in Pro c
th Int l Conf on VLSI Design New Delhi India pp January
A K Ma jhi J Jacob L M Patnaik and V D Agrawal On Test Coverage of
Path DelayFaults in Pro c th Int l Conf on VLSI Design Bangalore India pp
January
vel Path Delay Fault Simulator
A K Ma jhi J Jacob and L M Patnaik A No
using Binary Logic VLSI Design An Int l Jour Custom Chip Design Simulation
and Testing Vol No pp
A K Ma jhi V D Agrawal J Jacob and L M Patnaik Line Coverage of Path
Delay Faults submitted to IEEE Trans on VLSI Systems under review
Burn al l attachement in true know ledge
Grind it to ashes and make ink out of it
Make thy clean mind the paper
With love as thy pen and thy heart as the writer
Write the Name and glory of God
Under the inspiration of the Guru
Guru Nanak