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Algorithms for Test Generation and Fault Simulation of Path-Delay

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Algorithms for Test Generation and Fault Simulation of Path-Delay ALGORITHMS FOR TEST GENERATION AND FAULT SIMULATION OF PATH DELAY FAULTS IN LOGIC CIRCUITS A Thesis Submitted For the Degree of Doctor of Philosophy in the Faculty of Engineering by ANANTA KUMAR MAJHI Department of Electrical Communication Engineering INDIAN INSTITUTE OF SCIENCE BANGALORE INDIA NOVEMBER To Bhai Perfection is the goal of human life but human eorts are limited Happiness does not come merely through human endeavour but comes through grace Blessed are those who have the grace of both God and master Swami Rama i Acknowledgments It gives me immense pleasure to sincerely thank every one who help ed me in various ways to complete this dissertation First and foremost I bow b efore the Lord Almighty with a grateful heart for His blessings which have made me what Iam I express my deep sense of gratitude to my research sup ervisor Dr James Jacob of the ECE Department He has b een an excellent teacher counseller and guide to me and has given me continual encouragement and wise guidance throughout the course of my research work I am also indebted to him and his family for their p ersonal care love and understanding during many dicult times heartfelt gratitude to my research cosup ervisor Prof L M I place on record my Patnaik of the CSA Department for his encouragement moral supp ort and valuable suggestions I am obliged to him not only for providing the computing facilities in Micro pro cessor Applications Lab oratory but also for his p ersonal care and fatherly guidance which will always b e rememb ered and treasured by me My heartfelt thanks to Dr Vishwani D Agrawal of the ATT Bell Labs USA for acting as an unocial research cosup ervisor by always being there for me with his and encouragement during the entire course valuable advice suggestions keen interest of this work His comments and suggestions have greatly help ed me in improving my thinking presenting and writing skills I thank him also for providing me the most recent preprints and publications and for having gone through the entire manuscript I would like to thank Prof V U Reddy past Chairman and Prof A Selvara jan present Chairman of the ECE Department and Prof N Balakrishnan the Chairman of SERC for providing the nancial assistance and necessary computing facilities for my edavathy for allowing researchwork Imust also thank Prof A Kumar and Prof T S V me to use their lab oratory facilities during the initial period of my research career and also for their love and concern over the years I have greatly b eneted by the scholarly advice and suggestions from Dr M K Srinivas Rutgers Univ USA Pradip Mandal Jacob Augustine and P R Sureshkumar ii I thank them for their friendship and encouragement during my research work I would also like to thank Dr Srinivas Patil Dr Ankan Pramanick Dr Ira Pramanick and Dr L N Reddy all of IBM USA and Keerthi Heragu of Univ of Illinois USA for providing me copies of their theses and recent publications in the area of my work I ISc has b een a stimulating environment esp ecially b ecause of myloving friends Ani mesh Ratikanta Lo chan Purna Mano j Prasant Saro j Barada Krutibas Himansu Ni ra j Venkatesh Ra jendra Raghu Pradipta Dillip Pratap Chidananda Subhra Radha Gowri Nanda Namita Shorey Prem Sai Mala and others They have truly shared my life enjoyable during my stay on the campus My many a lighter moment and made sp ecial thanks to Animesh for being always with me in pain and pleasure and sharing my feelings at my monotonous moments I am esp ecially grateful to Biswa jit Biswamohan Moharana and family Ra jesh and family Rout and familyfor their love and concern as a younger brother and for making my stay comfortable in Bangalore Uninvited app earances in their houses on various o ccasions will always be remembered by me It is my pleasure to thank Chandramouli Mahadevan Pro ject Manager Pro duct Division Texas Instruments India Bangalore for his kind help and un Engineering derstanding during the nal phase of the work Life is always cheerful in TI I due to friends like Bala jee SriVidhya Debaleena Baskar Swagata Swathi Vinayak Sara ja RSR Palani and Prakash The nancial assistance from Texas Instruments India for printing and xeroxing the nal manuscript is greatly acknowledged Finallywords cannot express my feelings of gratitude to my beloved mother uncle their unwavering encouragement moral supp ort and sac and other family members for rice without which this work would not have been completed Their love and blessings were a p erp etual source of inspiration to me Ananta iii Abstract Ascertaining correct op eration of digital logic circuits requires verication of functional behavior as well as correct op eration at desired clo ckspeed The maximum allowable clo ck rate in a digital circuit is determined by the propagation delays of the combinational logic network b etween latches If the delay of the manufactured network exceeds sp ecications due to some physical defects or pro cess variations unstabilized and p ossibly incorrect logic values maybelatched in memory elements Delay fault testing can b e used to ensure that manufactured digital circuits meet their timing sp ecications In this thesis we present novel and ecient algorithms for test generation and fault simulation of path delay faults in combinational logic circuits We have develop ed a novel delay fault simulator for combinational logic circuits both robust and nonrobust tests for path which is capable of simultaneously analyzing delay faults Only a simple binary logic is used instead of the multivalued algebra as is used in most existing simulators A rule based approach is develop ed to identify all robust and nonrobust paths tested byatwopattern test while backtracing from primary outputs to primary inputs in a depthrst manner Rules identify probable glitches as they propagate through the circuit and thus determine when a test b ecomes nonrobust Exp erimental results for benchmark circuits determine the p erformance of the simulator For coverage all path delay faults are for deterministic as well as random test vectors implicitly considered We have also develop ed an ecient automatic test generation algorithm for path delay faults in combinational circuits To facilitate simultaneous consideration of robust and nonrobust tests we employ a value logic system Once a robust test is found for a path with a given transition our algorithm derives another test for the opp osite transition with minimal extra eort The derived test in most cases is either a robust or ktrace pro cedure is employed nonrobust test for the same path An ecient multiple bac for satisfying the test generation ob jectives A path selection metho d is prop osed which covers all lines in the logic circuit by the longest as well as the shortest p ossible paths iv through them The fault simulator integrated with the test generation system gives information on robust and nonrobust detection of faults either from a given target set or all path faults Exp erimental results on several b enchmark circuits substantiate the eciency of our algorithm A comparison with other published results is given We prop ose a new coverage metric and a twopass test generation metho d for delay faults in combinational circuits The coverage metric termed as line delay fault coverage on paths passing through each line in the circuit one for the considers two delay faults rising transition and the other for the falling transition However the test criterion is dierent from that of the slowtorise and slowtofall transition faults The new test called line delay test is a path delay test for the longest robustly testable path pro ducing a given transition on the target line The maximum numb er of tests and faults is limited to twice the number of lines Using a twopass test generation pro cedure we b egin with a minimal set of longest paths covering all lines and generate tests for them Fault the line delay fault coverage The second pass considers simulation is used to determine those lines for which line delay tests could not b e generated in the rst pass and attempts to generate robust tests for successively shorter paths through these lines until a test for the longest robustly testable path is found We present a theorem stating that a redundant stuckat fault makes all path delay faults involving that faulty line untestable for either a rising or falling transition dep ending on the typ e of the stuckat fault The use of this theorem considerably reduces the eort of delay test generation An implementation of our algorithm achieved very high line delay coverage eciency for most of the benchmark circuits We hop e that the novel ideas and algorithms prop osed in this thesis will nd appli cation in the development of ecient CAD to ols for delay fault testing and simulation of real life VLSI circuits The new delay fault coverage metric has the advantages of reduced complexity and high coverage eciency We discuss its limitations with resp ect to the conventional path delay fault mo del Future exp erimental work should establish the validity of our fault coverage metric Contents Intro duction Design and Test of Integrated Circuits DelayFault Testing Why Delay Fault Testing Contribution of the Thesis Organization of the Thesis Prior Work DelayFault Mo dels Transition Fault Mo del Gate Delay Fault Mo del
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