High Performance, Sub Ghz Radio Transceiver IC ADF7030-1

High Performance, Sub GHz

Radio Transceiver IC Data Sheet ADF7030-1

FEATURES On-chip ARM Cortex-M0 processor for Radio frequency (RF) ranges Radio control and calibration 169.4 MHz to 169.6 MHz Packet management 426 MHz to 470 MHz Clear channel assessment (CCA) 863 MHz to 960 MHz IEEE802.15.4g support Data rates Frame format 2FSK/2GFSK: 0.1 kbps to 300 kbps Data whitening 4FSK/4GFSK: 1 kbps to 360 kbps (transmit only) Dual-sync word detection Dual power amplifiers (PAs) Forward error correction (FEC) and interleaving Programmable receiver channel bandwidth Suitable for systems targeting compliance with from 2.6 kHz to 406 kHz ETSI EN 300 220-1 Receiver (Rx) performance EN 54-25, EN 13757-4 Up to 97 dB blocking at ±20 MHz offset FCC Part 15, Part 22, Part 24, Part 90, and Part 101 Up to 72 dB adjacent channel rejection ARIB STD-T30, STD-T67, STD-T108, STD-T96 −134.3 dBm sensitivity at 0.1 kbps Packages −121.3 dBm sensitivity at 2.4 kbps 6 mm × 6 mm, 40-lead LFCSP Transmitter (Tx) performance 7 mm × 7 mm, 48-lead LQFP −20 dBm to +17 dBm range with 0.1 dB step resolution APPLICATIONS Very low output power variation vs. temperature and supply IEEE 802.15.4g (MR-FSK PHY) Low active current Wireless M-Bus (EN 13757-4) 50 mA Tx current at 17 dBm Smart metering 21.2 mA Rx current at12.5 kbps Security and building automation Ultralow sleep current Active tag asset tracking 10 nA with memory retained Industrial control Host microprocessor interface Wireless sensor networks (WSNs) Easy to use programming serial peripheral interface (SPI) Configurable 8-bit general-purpose input/output (GPIO) bus

FUNCTIONAL BLOCK DIAGRAM CREGx HFXTALN HFXTALP GPIO6 GPIO7 ADF7030-1

TCXO 26MHz 32kHz 26kHz LDOx BUFFER OSC OSC RC OSC INTERRUPT CONTROLLER

ARM® LNAIN1 CORTEX®-M0 LNA RECEIVER SPI LNAIN2 SLAVE SPI DIGITAL BASEBAND

PA SYNTHESIZER CONFIGURABLE GPIOx PAOUT1 GPIOs ROM

TEMPERATURE PA PAOUT2 TRANSMITTER RAM SENSOR

NOTES

1. CREGx, GPIOx, AND SPI CONTAIN MULTIPLE PINS. 14373-001 Figure 1.

Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADF7030-1 Data Sheet

TABLE OF CONTENTS Features ...... 1 460 MHz—Transmit ...... 34 Applications ...... 1 868 MHz—Receive ...... 36 Functional Block Diagram ...... 1 868 MHz—Transmit ...... 38 Revision History ...... 2 915 MHz—Receive ...... 40 General Description ...... 3 915 MHz—Transmit ...... 42 Specifications ...... 4 Theory of Operation ...... 44 Temperature and Voltage ...... 4 State Machine ...... 44 General RF ...... 4 Radio Timing ...... 45 Receive ...... 5 Host Interface...... 46 Transmit ...... 6 Receiver...... 46 Current Consumption ...... 8 Transmitter ...... 48 Band Specific Receive and Transmit ...... 9 Calibration...... 49 External 26 MHz Oscillator ...... 19 Packet Handling ...... 50 Low Frequency Oscillator ...... 19 Applications Information ...... 51 Temperature Sensor ...... 19 Typical Application Circuit ...... 51 Digital Input/Output ...... 20 Silicon Anomaly ...... 52 Digital Timing ...... 20 ADF7030-1 Functionality Issues ...... 52 Absolute Maximum Ratings ...... 22 Functionality Issues ...... 52 ESD Caution ...... 22 Development Support ...... 53 Pin Configurations and Function Descriptions ...... 23 Design Package ...... 53 Typical Performance Characteristics ...... 27 Reference Manuals ...... 53 169 MHz—Receive ...... 27 Evaluation Kits ...... 53 169 MHz—Transmit ...... 28 Evaluation Software ...... 53 433 MHz—Receive ...... 30 Outline Dimensions ...... 54 433 MHz—Transmit ...... 31 Ordering Guide ...... 55 460 MHz—Receive ...... 33

REVISION HISTORY Changes to Figure 34 to Figure 38 ...... 33 3/2020—Rev. 0 to Rev. A Changes to Figure 46 to Figure 51 ...... 36 Changes to Features ...... 1 Changes to Figure 52 to Figure 54 ...... 37 Changes to General Description ...... 3 Changes to Figure 65 to Figure 70 ...... 40 Changes to Wideband Mode Parameter, Table 3 ...... 5 Changes to Figure 71 ...... 41 Changes to Table 6 and Table 7 ...... 9 Deleted Figure 72 and Figure 73, Renumbered Sequentially ... 41 Changes to Table 8 and Table 9 ...... 11 Changes to Table 28 ...... 47 Changes to Table 10 and Table 11 ...... 13 Updated Outline Dimensions ...... 54 Changes to Table 12 and Table 13 ...... 15 Changes to Table 14 and Table 15 ...... 17 6/2016—Revision 0: Initial Version Changes to Figure 7 to Figure 12 ...... 27 Changes to Figure 23 to Figure 26 ...... 30

Rev. A | Page 2 of 55 Data Sheet ADF7030-1

GENERAL DESCRIPTION The ADF7030-1 is a fully integrated, radio transceiver achieving IEEE802.15.4g standard. FEC, as per the IEEE802.15.4g standard, high performance at very low power. The ADF7030-1 is ideally is also supported. suited for applications that require long range, network The ADF7030-1 operates with a power supply range of 2.2 V to robustness, and long battery life. It is suitable for applications 3.6 V and has very low power consumption in both Tx and Rx that operate in the ISM, SRD, and licensed frequency bands at modes, enabling long lifetimes in battery-operated systems. An 169.4 MHz to 169.6 MHz, 426 MHz to 470 MHz, and 863 MHz ultralow power deep sleep mode achieves a typical current of to 960 MHz. It provides extensive support for standards-based 10 nA with the configuration memory retained. protocols like IEEE802.15.4g while also providing flexibility to support a wide range of proprietary protocols. A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a The highly configurable low intermediate frequency (IF) receiver microcontroller). The host processor can configure the ADF7030-1 supports a large range of receiver channel bandwidths from using a simple command-based protocol over a standard 4-wire 2.6 kHz to 406 kHz. This range of receiver channel bandwidths SPI interface. A single-byte command transitions the radio allows the ADF7030-1 to support ultranarrow-band, narrow- between states or performs a radio function. band, and wideband channel spacing. The ADF7030-1 is available in two package types: a 6 mm × The ADF7030-1 features two independent PAs supporting 6 mm, 40-lead LFCSP and a 7 mm × 7 mm, 48-lead LQFP. Both output power ranges of −20 dBm to +13 dBm and −20 dBm to package types use NiPdAu plating to mitigate against silver +17 dBm. The PAs support ultrafine adjustment of the power migration in high humidity applications. The ADF7030-1 with a step resolution of 0.1 dB. The PA output power is operating temperature range is −40°C to +85°C. exceptionally robust over temperature and voltage. The PAs have an automatic power ramp control to limit spectral splatter For Figure 13 to Figure 19, Figure 30, Figure 42, Figure 60, to meet regulatory standards. Figure 61, and Figure 75 in the Typical Performance Characteristics section, PA_COARSE is a programmable value that provides a The ADF7030-1 features an on-chip ARM® Cortex®-M0 coarse adjustment of the PA output power. This value can be processor that performs radio control, radio calibration, and programmed in the range of 1 to 6 for PA1, and from 1 to 10 for packet management. Cortex-M0 eases the processing burden of PA2. PA_FINE is a programmable value that provides a fine adjust- the host processor because the ADF7030-1 integrates the lower ment of the PA output power. This value can be programmed in layers of a typical communication protocol stack. This internal the range of 3 to 127 for both PA1 and PA2. PA_MICRO is a processor also permits the download and execution of Analog programmable value that provides a microadjustment (typically Devices, Inc., provided firmware modules that can extend the <0.1 dB) of the PA output power. This value can be programmed in functionality of the ADF7030-1. the range of 1 to 31 for both PA1 and PA2. PAOLDO_VOUT_ The ADF7030-1 has two packet modes: generic packet mode CON is a programmable value that configures the internal LDO and IEEE802.15.4g mode. In generic packet mode, the packet voltage that provides bias for the PA. For additional information format is highly flexible and fully programmable, thereby on these bit settings, see the ADF7030-1 Software Reference ensuring its compatibility with proprietary packet formats. In Manual, which is the detailed programming guide for the device. IEEE802.15.4g packet mode, the packet format conforms to the

Rev. A | Page 3 of 55 ADF7030-1 Data Sheet

SPECIFICATIONS VDD = VBAT1 = VBAT2 = VBAT3 = VBAT4 = VBAT5 = VBAT6 = 2.2 V to 3.6 V, exposed pad (EPAD) = 0 V (ground), TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, T A = 25°C, unless otherwise noted. All VBATx pins must be tied together. A one-time radio calibration is required, unless otherwise noted. TEMPERATURE AND VOLTAGE

Table 1. Parameter Min Typ Max Unit Test Conditions/Comments

TEMPERATURE RANGE, TA −40 +85 °C VOLTAGE SUPPLY VBATx Pin Voltage 2.2 3.6 V Transmit power ≤ 13 dBm 2.85 3.6 V Transmit power ≥ 17 dBm, PA LDO voltage = 2.65 V PA LDO voltage + 0.2 V 3.6 V Transmit power >13 dBm and < 17 dBm; the PA LDO voltage is configurable

GENERAL RF

Table 2. Parameter Min Typ Max Unit Test Conditions/Comments RF FREQUENCY Frequency Range 169.4 169.6 MHz 426 470 MHz 863 960 MHz Channel Frequency Resolution 1.5 Hz DATA RATE IEEE802.15.4g Packet Mode kbps 2FSK, 2GFSK Modulation 2.4 150 kbps Generic Packet Mode 2FSK, 2GFSK Modulation 0.1 300 kbps 4FSK, 4GFSK Modulation 1 360 kbps Tx only, generic packet mode only On/Off Keying (OOK) Modulation 16.384 kbps Tx only, Manchester encoded, generic packet mode only Resolution 1 bps FREQUENCY DEVIATION Range 2FSK, 2GFSK Modulation 1 250 kHz 4FSK, 4GFSK Modulation 1 250 kHz Tx only, generic packet mode only Resolution 100 Hz GAUSSIAN FILTER BANDWIDTH TIME (BT) PRODUCT 0.3, 0.35, 0.4, 0.5 Programmable

Rev. A | Page 4 of 55 Data Sheet ADF7030-1

RECEIVE

Table 3. Parameter Min Typ Max Unit Test Conditions/Comments MAXIMUM DATA RATE ERROR TOLERANCE ±0.1 % RECEIVER CHANNEL FILTER BANDWIDTH Programmable; see Table 27 and Table 28 for a list of all supported values Narrow-Band Mode Maximum 20.0 kHz Minimum 2.6 kHz Wideband Mode Maximum 406.25 kHz Minimum 77.38 kHz MAXIMUM RF INPUT LEVEL 10 dBm RECEIVER LINEARITY Measured at maximum receiver gain Input Third-Order Intercept (IIP3) −8.5 dBm Receiver channel frequency = 169.43125 MHz, fSOURCE1 = 171.35 MHz, fSOURCE2 = 173.26875 MHz Input Second-Order Intercept (IIP2) 53 dBm Receiver channel frequency = 169.53125 MHz, fSOURCE1 = 171.55 MHz, fSOURCE2 = 171.63125 MHz 1 dB Compression (P1dB) −18.7 dBm Receiver channel frequency = 169.43125 MHz, fSOURCE1 = 171.43125 MHz RECEIVED SIGNAL STRENGTH INDICATOR Refer to the Typical Performance Characteristics section (RSSI) for further detail; sensitivity defined as bit error rate (BER) = 0.1% Resolution 0.25 dB Calibrated Absolute Accuracy ±2 dB −40 dBm to sensitivity + 6 dB; one-point offset calibration DIFFERENTIAL LOW NOISE AMPLIFIER (LNA) INPUT IMPEDANCE, 40-LEAD LFCSP PACKAGE LNA in Rx Mode f = 169 MHz 78 − j20 Ω f = 433 MHz 69 − j25 Ω f = 460 MHz 68 − j25 Ω f = 868 MHz 56 − j29 Ω f = 915 MHz 55 − j30 Ω LNA in Tx Mode Combined match enabled f = 169 MHz 7 + j2 Ω f = 433 MHz 7 + j4 Ω f = 460 MHz 7 + j4 Ω f = 868 MHz 8 + j8 Ω f = 915 MHz 8 + j8 Ω DIFFERENTIAL LNA INPUT IMPEDANCE, 48-LEAD LQFP PACKAGE LNA in Rx Mode f = 169 MHz 78 − j16 Ω f = 433 MHz 71 − j18 Ω f = 460 MHz 73 − j22 Ω f = 868 MHz 58 − j20 Ω f = 915 MHz 57 − j20 Ω LNA in Tx Mode Combined match enabled f = 169 MHz 7 + j3 Ω f = 433 MHz 8 + j9 Ω f = 460 MHz 8 + j9 Ω f = 868 MHz 9 + j18 Ω f = 915 MHz 9 + j19 Ω

Rev. A | Page 5 of 55 ADF7030-1 Data Sheet

TRANSMIT

Table 4. Parameter Min Typ Max Unit Test Conditions/Comments POWER AMPLIFIER (PA) Power Amplifier 1 (PA1) Transmit Power Maximum 13 dBm Transmit Power Minimum −20 dBm Transmit Power Step Resolution 0.1 dB Transmit Power Variation vs. ±0.15 From −40°C to +85°C, transmit power = 13 dBm, RF Temperature frequency = 169 MHz

Transmit Power Variation vs. VDD ±0.1 From VDD = 2.2 V to VDD = 3.6 V, transmit power = 13 dBm, RF frequency = 169 MHz Transmit Power Accuracy ±0.3 transmit power = 13 dBm, RF frequency = 169 MHz Power Amplifier 2 (PA2) Transmit Power Maximum The maximum output power level achievable on PA2 depends on the programmable PA CREG3 LDO voltage setting; refer to the ADF7030-1 Software Reference Manual for further details

17 dBm 2.85 V ≤ VDD ≤ 3.6 V

13 dBm 2.2 V ≤ VDD ≤ 3.6 V Transmit Power Minimum −20 dBm Transmit Power Step Resolution 0.1 dB Transmit Power Variation vs. ±0.1 dB From −40°C to +85°C, transmit power = 17 dBm, Temperature RF frequency = 169 MHz

Transmit Power Variation vs. VDD ±0.1 dB From VDD = 3.0 V to VDD = 3.6 V, transmit power = 17 dBm, RF frequency = 169 MHz Transmit Power Accuracy ±0.25 dB Transmit power = 17 dBm, RF frequency = 169 MHz PA IMPEDANCE, 40-LEAD LFCSP For guidance on impedance matching, refer to the PACKAGE ADF7030-1 Hardware Reference Manual Optimum PA Load While in Transmit PA1 f = 169 MHz 50 + j0 Ω f = 433 MHz, f = 460 MHz 45 + j30 Ω f = 868 MHz, f = 915 MHz 50 + j20 Ω PA2 f = 169 MHz 38 + j0 Ω f = 433 MHz, f = 460 MHz 38 + j25 Ω f = 868 MHz, f = 915 MHz 38 + j18.5 Ω PA Input Impedance While in Rx PA1 f = 169 MHz 7 − j232 Ω f = 433 MHz 5 − j102 Ω f = 460 MHz 5 − j96 Ω f = 868 MHz 4 − j49 Ω f = 915 MHz 4 − j46 Ω PA2 f = 169 MHz 5 − j177 Ω f = 433 MHz 3 − j69 Ω f = 460 MHz 3 − j65 Ω f = 868 MHz 3 − j33 Ω f = 915 MHz 3 − j31 Ω

Rev. A | Page 6 of 55 Data Sheet ADF7030-1

Parameter Min Typ Max Unit Test Conditions/Comments PA IMPEDANCE, 48-LEAD LQFP For guidance on impedance matching, refer to the PACKAGE ADF7030-1 Hardware Reference Manual Optimum PA Load While in Transmit PA1 f = 169 MHz 45 + j 8 Ω f = 433 MHz, f = 460 MHz 40 + j20 Ω f = 868 MHz 40 + j20 Ω f = 915 MHz 40 + j20 Ω PA2 f = 169 MHz 37 + j 9 Ω f = 433 MHz, f = 460 MHz 30 + j25 Ω f = 868 MHz, f = 915 MHz 30 + j15 Ω PA Input Impedance While in Rx PA1 f = 169 MHz 6 − j236 Ω f = 433 MHz, f = 460 MHz 6 − j87 Ω f = 868 MHz 5 − j37 Ω f = 915 MHz 5 − j34 Ω PA2 f = 169 MHz 5 − j169 Ω f = 433 MHz, f = 460 MHz 4 − j58 Ω f = 868 MHz 3 − j22 Ω f = 915 MHz 3 − j19 Ω

Rev. A | Page 7 of 55 ADF7030-1 Data Sheet

CURRENT CONSUMPTION

Table 5. Parameter Min Typ Max Unit Test Conditions/Comments TRANSMIT CURRENT CONSUMPTION In the PHY_TX state transmitting a carrier f = 169.4 MHz Tx Power = 0 dBm, PA1 18 mA Tx Power = 10 dBm, PA1 31 mA Tx Power = 13 dBm, PA1 39 mA Tx Power = 17 dBm, PA2 65 mA f = 433 MHz Tx Power = 0 dBm, PA1 19 mA Tx Power = 10 dBm, PA1 31 mA Tx Power = 13 dBm, PA1 39 mA f = 460 MHz Tx Power = 17 dBm, PA2 50 mA f = 868 MHz, f = 915 MHz Tx Power = 0 dBm, PA1 20 mA Tx Power = 10 dBm, PA1 34 mA Tx Power = 13 dBm, PA1 43 mA Tx Power = 17 dBm, PA2 65 mA RECEIVE CURRENT CONSUMPTION In the PHY_RX state, waiting for preamble f = 169.4 MHz Data Rate = 4.8 kbps 24.8 mA Narrow-band receive path f = 433 MHz, f = 460 MHz Data Rate = 4.8 kbps 24.5 mA Narrow-band receive path Data Rate = 50 kbps 24 mA Wideband receive path f = 868 MHz, f = 915 MHz Data Rate = 5 kbps 23.2 mA Narrow-band receive path Data Rate = 12.5 kbps 21.2 mA Wideband receive path Data Rate = 50 kbps 21.4 mA Wideband receive path Data Rate = 100 kbps 23.7 mA Wideband receive path Data Rate = 150 kbps 24 mA Wideband receive path Data Rate = 300 kbps 25.4 mA Wideband receive path RADIO STATE CURRENT CONSUMPTION PHY_SLEEP State 2 nA Memory not retained, no wakeup oscillator enabled, RTC disabled 10 nA Memory retained, no wakeup oscillator enabled, RTC disabled 1 µA Memory retained, internal 26 kHz RC oscillator enabled, RTC enabled 1 µA Memory retained, external 32 kHz oscillator enabled, RTC enabled PHY_OFF State 1.9 mA First entry to PHY_OFF after wake from PHY_SLEEP or after reset event PHY_OFF State 3.7 mA Second and subsequent entries to PHY_OFF after wake from PHY_SLEEP or after reset event PHY_ON State 3.7 mA

Rev. A | Page 8 of 55 Data Sheet ADF7030-1

BAND SPECIFIC RECEIVE AND TRANSMIT 169.4 MHz to 169.6 MHz Unless otherwise noted, the configurations detailed in Table 6 are used to specify the performance of the ADF7030-1 in Table 7. All measurements are performed on the EV-ADF70301-169BZ evaluation board, unless otherwise noted. The EV-ADF70301-169BZ uses a separate transmit/receive match design and a 26 MHz thermally compensated crystal oscillator (TCXO) reference. N/A means not applicable.

Table 6. Configurations in the 169.4 MHz to 169.6 MHz Frequency Band RF Data Frequency Channel IF Receiver Configuration Frequency Rate Deviation Spacing Frequency Bandwidth Packet Setup for Packet-Based Name (MHz) (kbps) Modulation (kHz) (kHz) (kHz) (kHz) Testing 169.41875 MHz/ 169.41875 0.1 2GFSK 0.5 N/A 81.25 2.6 Preamble = 0xAAAA, sync word = 0.1 kbps 0xF672, payload length = 23 bytes, cyclic redundancy check (CRC) = 2 bytes 169.43125 MHz/ 169.43125 2.4 2GFSK 2.4 12.5 81.25 9.1 Preamble = 0x55555555, sync 2.4 kbps word = 0xF672, payload length = 23 bytes, CRC = 2 bytes 169.41875 MHz/ 169.41875 4.8 2GFSK 2.4 12.5 81.25 11.1 Preamble = 0x55555555, sync 4.8 kbps word = 0xF672, payload length = 23 bytes, CRC = 2 bytes 169.46875 MHz/ 169.46875 6.4 4GFSK 3.2 (outer 12.5 N/A N/A N/A 6.4 kbps deviation) (Tx only) (Tx only)

Table 7. Specifications in the 169.4 MHz to 169.6 MHz Frequency Band Parameter Min Typ Max Unit Test Conditions/Comments SENSITIVITY, PACKET ERROR RATE (PER) Configuration 169.41875 MHz/0.1 kbps −134.3 dBm At PER = 5%, automatic frequency control (AFC) disabled Configuration 169.43125 MHz/2.4 kbps −121.3 dBm At PER = 5%, AFC enabled, RF frequency error range = ±11.5 ppm Configuration 169.41875 MHz/4.8 kbps −120.0 dBm At PER = 5%, AFC enabled, RF frequency error range = ±11.5 ppm CHANNEL SELECTIVITY AND BLOCKING— Desired signal 3 dB above the input sensitivity level (BER BER-BASED TEST METHOD = 0.1%), carrier wave interferer power level increased until BER = 0.1%; AFC disabled, image calibrated Configuration 169.43125 MHz/2.4 kbps Adjacent Channel (±12.5 kHz) 72 dB Alternate Channel (±25 kHz) 72 dB ±2 MHz 93 dB ±10 MHz 92 dB ±20 MHz 97 dB Configuration 169.41875 MHz/4.8 kbps Adjacent Channel (±12.5 kHz) 70 dB Alternate Channel (±25 kHz) 70 dB ±2 MHz 92 dB ±10 MHz 95 dB CHANNEL SELECTIVITY AND BLOCKING— Desired signal 3 dB above the input sensitivity level (PER = PER-BASED TEST METHOD 5%), carrier wave interferer power level increased until PER = 5%, AFC enabled, image calibrated Configuration 169.43125 MHz/2.4 kbps Adjacent Channel (±12.5 kHz) 66 dB Alternate Channel (±25 kHz) 67 dB ±2 MHz 93 dB ±10 MHz 91 dB Configuration 169.41875 MHz/4.8 kbps Adjacent Channel (±12.5 kHz) 53 dB

Rev. A | Page 9 of 55 ADF7030-1 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments Alternate Channel (±25 kHz) 64 dB ±2 MHz 91 dB ±10 MHz 94 dB CHANNEL SELECTIVITY AND BLOCKING— Measured as per EN 300 220-1 V2.4.1, AFC disabled ETSI EN 300 220-1 TEST METHOD Configuration 169.43125 MHz/2.4 kbps Desired signal level = −106.7 dBm (3 dB above the reference sensitivity level) ±2 MHz −15 dBm ±10 MHz −12 dBm Configuration 169.41875 MHz/4.8 kbps Desired signal level = −105.8 dBm (3 dB above the reference sensitivity level) ±2 MHz −16 dBm ±10 MHz −13 dBm COCHANNEL REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), carrier wave interferer power level increased until PER = 5%, AFC enabled Configuration 169.43125 MHz/2.4 kbps −9 dB Configuration 169.41875 MHz/4.8 kbps −11 dB CALIBRATED IMAGE REJECTION dB Desired signal 3 dB above the input sensitivity level (PER = 5%), carrier wave interferer power level increased until PER = 5%, AFC enabled, image calibrated Configuration 169.43125 MHz/2.4 kbps 60 dB Configuration 169.41875 MHz/4.8 kbps 58 dB ADJACENT CHANNEL POWER (ACP) Spectrum analyzer settings: resolution bandwidth = 100 Hz, video bandwidth = 300 Hz Configuration 169.43125 MHz/2.4 kbps PA1, output power = 13 dBm Adjacent Channel −83 dBc Alternate Channel −83 dBc Configuration 169.41875 MHz/4.8 kbps PA2, output power = 17 dBm Adjacent Channel −60 dBc Alternate Channel −84 dBc Configuration 169.46875 MHz/6.4 kbps PA1, output power = 13 dBm Adjacent Channel −68 dBc Alternate Channel −81 dBc OCCUPIED BANDWIDTH Occupied bandwidth is the bandwidth containing 99% of the total integrated power; spectrum analyzer settings: resolution bandwidth = 100 Hz, video bandwidth = 300 Hz Configuration 169.43125 MHz/2.4 kbps 6.3 kHz PA1, output power = 13 dBm Configuration 169.41875 MHz/4.8 kbps 7.8 kHz PA2, output power = 17 dBm Configuration 169.46875 MHz/6.4 kbps 8.2 kHz PA1, output power = 13 dBm SPURIOUS EMISSIONS (EXCLUDING Measured conductively at antenna input; RF frequency = HARMONICS) 169.43125 MHz Receive <1 GHz −74 dBm 1 GHz to 4 GHz −52 dBm Transmit PA2, output power = 17 dBm, transmitting continuous carrier wave <1 GHz −70 dBc 1 GHz to 4 GHz −72 dBc HARMONIC EMISSIONS Measured conductively at antenna input, transmitting continuous carrier wave; RF frequency = 169.43125 MHz 17 dBm Output Power PA2 Second Harmonic −64 dBc Third Harmonic −89 dBc All Other Harmonics <−90 dBc

Rev. A | Page 10 of 55 Data Sheet ADF7030-1

433 MHz Unless otherwise noted, the configuration detailed in Table 8 is used to specify the performance of the ADF7030-1 in Table 9. All measurements are performed on the EV-ADF70301-460BZ evaluation board, unless otherwise noted. The EV-ADF70301-460BZ uses a separate transmit/receive match design and a 26 MHz TCXO reference.

Table 8. 433 MHz Configurations RF Data Frequency Channel IF Receiver Configuration Frequency Rate Deviation Spacing Frequency Bandwidth Packet Setup for Name (MHz) (kbps) Modulation (kHz) (kHz) (kHz) (kHz) Packet Based Testing 433 MHz/50 kbps 433 50 2GFSK 25 200 135.42 101.57 Preamble = 0xAAAAAAAA, sync word = 0xF672, payload length = 16 bytes, CRC = 2 bytes

Table 9. 433 MHz Specifications Parameter Min Typ Max Unit Test Conditions/Comments SENSITIVITY, PER Configuration 433 MHz/50 kbps −108.6 dBm AT PER = 5%, AFC enabled, RF frequency error range = ±25 ppm CHANNEL SELECTIVITY AND BLOCKING— Desired signal 3 dB above the input sensitivity level (BER = BER-BASED TEST METHOD 0.1%), carrier wave interferer power level increased until BER = 0.1%, image calibrated, AFC disabled Configuration 433 MHz/50 kbps Adjacent Channel (±200 kHz) 56 dB Alternate Channel (±400 kHz) 62 dB ±2 MHz 78 dB ±10 MHz 83 dB ±20 MHz 87 dB CHANNEL SELECTIVITY AND BLOCKING— Desired signal 3 dB above the input sensitivity level (PER = PER BASED TEST METHOD 5%), carrier wave interferer power level increased until PER = 5%, image calibrated, AFC enabled Configuration 433 MHz/50 kbps Adjacent Channel (±200 kHz) 51 dB Alternate Channel (±400 kHz) 58 dB ±2 MHz 73 dB ±10 MHz 79 dB COCHANNEL REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), carrier wave interferer power level increased until PER = 5%, AFC enabled Configuration 433 MHz/50 kbps −10 dB CALIBRATED IMAGE REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), carrier wave interferer power level increased until PER = 5%, AFC enabled, image calibrated Configuration 433 MHz/50 kbps 48 dB ACP Spectrum analyzer settings: resolution bandwidth = 100 Hz, video bandwidth = 300 Hz Configuration 433 MHz/50 kbps −60 dBc OCCUPIED BANDWIDTH Occupied bandwidth is the bandwidth containing 99% of the total integrated power; spectrum analyzer settings: resolution bandwidth = 100 Hz, video bandwidth = 300 Hz Configuration 433 MHz/50 kbps 86 kHz

Rev. A | Page 11 of 55 ADF7030-1 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments SPURIOUS EMISSIONS (EXCLUDING Measured conductively at antenna port; RF frequency = HARMONICS) 433 MHz Receive <1 GHz −74 dBm 1 GHz to 4 GHz −51 dBm Transmit PA1, output power = 13 dBm, transmitting continuous carrier wave <1 GHz −46 dBc 1 GHz to 4 GHz −68 dBc HARMONIC EMISSIONS Measured conductively at antenna input, transmitting continuous carrier wave; RF frequency = 433 MHz, PA1, output power = 10 dBm Second Harmonic −64 dBc All Other Harmonics <−90 dBc

Rev. A | Page 12 of 55 Data Sheet ADF7030-1

450 MHz to 470 MHz Unless otherwise noted, the configuration detailed in Table 10 is used to specify the performance of the ADF7030-1 in Table 11. All measurements are performed on the EV-ADF70301-460BZ evaluation board, unless otherwise noted. The EV-ADF70301-460BZ uses a separate transmit/receive match design and a 26 MHz TCXO reference.

Table 10. Configurations in the 450 MHz to 470 MHz Frequency Band RF Data Frequency Channel IF Receiver Configuration Frequency Rate Deviation Spacing Frequency Bandwidth Packet Setup for Packet Name (MHz) (kbps) Modulation (kHz) (kHz) (kHz) (kHz) Based Testing 460 MHz/7.2 kbps 460 7.2 2GFSK 2.0 12.5 81.25 11.7 Preamble = 0xAAAAAAAA, sync word = 0xF672, payload length = 23 bytes, CRC = 2 bytes

Table 11. Specifications in the 450 MHz to 470 MHz Frequency Band Parameter Min Typ Max Unit Test Conditions/Comments SENSITIVITY, PER Configuration 460 MHz/7.2 kbps −115.6 dBm At PER = 5%, AFC enabled, RF frequency error range = ±3.9 ppm CHANNEL SELECTIVITY AND BLOCKING— Desired signal 3 dB above the input sensitivity level (BER = 0.1%), BER-BASED TEST METHOD carrier wave interferer power level increased until BER = 0.1%, image calibrated, AFC disabled Configuration 460 MHz/7.2 kbps Adjacent Channel (±12.5 kHz) 58 dB Alternate Channel (±25 kHz) 60 dB ±2 MHz 81 dB ±10 MHz 87 dB ±20 MHz 89 dB CHANNEL SELECTIVITY AND BLOCKING— Desired signal 3 dB above the input sensitivity level (PER = 5%), PER-BASED TEST METHOD carrier wave interferer power level increased until PER = 5%, image calibrated, AFC enabled Configuration 460 MHz/7.2 kbps Adjacent Channel (±12.5 kHz) 51 dB Alternate Channel (±25 kHz) 58 dB ±2 MHz 80 dB ±10 MHz 87 dB COCHANNEL REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), carrier wave interferer power level increased until PER = 5%, AFC enabled Configuration 460 MHz/7.2 kbps −13 dB CALIBRATED IMAGE REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), carrier wave interferer power level increased until PER = 5%, AFC enabled, image calibrated Configuration 460 MHz/7.2 kbps 54 dB ACP Spectrum analyzer settings: resolution bandwidth = 100 Hz, video bandwidth = 300 Hz Configuration 460 MHz/7.2 kbps −49 dBc OCCUPIED BANDWIDTH Occupied bandwidth is the bandwidth containing 99% of the total integrated power; spectrum analyzer settings: resolution bandwidth = 100 Hz, video bandwidth = 300 Hz Configuration 460 MHz/7.2 kbps 7.7 kHz

Rev. A | Page 13 of 55 ADF7030-1 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments SPURIOUS EMISSIONS (EXCLUDING Measured conductively at antenna port; RF frequency = 460 MHz HARMONICS) Receive <960 MHz −74 dBm 960 MHz to 12.7 GHz −51 dBm Transmit PA2, output power = 17 dBm, transmitting continuous carrier wave <960 MHz −46 dBc 960 MHz to 12.7 GHz −71 dBc HARMONIC EMISSIONS Measured conductively at antenna port, transmitting continuous carrier wave; RF frequency = 460 MHz, output power = 17 dBm, PA2 Second Harmonic −63 dBc All Other Harmonics < −90 dBc

Rev. A | Page 14 of 55 Data Sheet ADF7030-1

863 MHz to 876 MHz Unless otherwise noted, the configurations detailed in Table 12 are used to specify the performance of the ADF7030-1 in Table 13. All measurements are performed on the EV-ADF70301-868BZ evaluation board, unless otherwise noted. The EV-ADF70301-868BZ uses a separate transmit/receive match design and a 26 MHz TCXO reference.

Table 12. Configurations in the 863 MHz to 876 MHz Frequency Band RF Data Frequency Channel IF Receiver Configuration Frequency Rate Deviation Spacing Frequency Bandwidth Packet Setup for Name (MHz) (kbps) Modulation (kHz) (kHz) (kHz) (kHz) Packet Based Testing 868 MHz/4.8 kbps 868 4.8 2GFSK 2.4 12.5 81.25 11.7 Preamble = 0xAAAAAAAA, sync word = 0xF672, payload length = 23 bytes, CRC = 2 bytes 868 MHz/100 kbps 868 100 2FSK 50 500 270.83 203.12 Preamble = 0xAAAAAAAA, sync word = 0x543D54CD, payload length = 20 bytes, CRC = 2 bytes

Table 13. Specifications in the 863 MHz to 876 MHz Frequency Band Parameter Min Typ Max Unit Test Conditions/Comments SENSITIVITY, PER Configuration 868 MHz/4.8 kbps −118.4 dBm At PER = 5%, AFC enabled, RF frequency error range = ±3 ppm Configuration 868 MHz/100 kbps −106.4 dBm At PER = 5%, AFC enabled, RF frequency error range = ±25 ppm, data rate error range = ±100 ppm, frequency deviation error range = ±25% CHANNEL SELECTIVITY AND BLOCKING— Desired signal 3 dB above the input sensitivity level (BER = BER-BASED TEST METHOD 0.1%), carrier wave interferer power level increased until BER = 0.1%, image calibrated, AFC disabled Configuration 868 MHz/4.8 kbps Adjacent Channel (±12.5 kHz) 60 dB Alternate Channel (±25 kHz) 60 dB ±2 MHz 82 dB ±10 MHz 90 dB ±20 MHz 95 dB CHANNEL SELECTIVITY AND BLOCKING— Desired signal 3 dB above the input sensitivity level (PER = PER-BASED TEST METHOD 5%), carrier wave interferer power level increased until PER = 5%, image calibrated, AFC enabled Configuration 868 MHz/4.8 kbps Adjacent Channel (±12.5 kHz) 43 dB Alternate Channel (±25 kHz) 57 dB ±2 MHz 79 dB ±10 MHz 87 dB Configuration 868 MHz/100 kbps Adjacent Channel (500 kHz) 35 dB Adjacent Channel (−500 kHz) 53 dB Alternate Channel (±1000 kHz) 60 dB ±2 MHz 65 dB ±10 MHz 74 dB COCHANNEL REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), carrier wave interferer power level increased until PER = 5%, AFC enabled Configuration 868 MHz/4.8 kbps −11 dB Configuration 868 MHz/100 kbps −11 dB

Rev. A | Page 15 of 55 ADF7030-1 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments UNCALIBRATED IMAGE REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), carrier wave interferer power level increased until PER = 5%, AFC enabled Configuration 868 MHz/4.8 kbps 37 dB Configuration 868 MHz/100 kbps 34 dB ACP Spectrum analyzer settings: resolution bandwidth = 100 Hz, video bandwidth = 300 Hz Configuration 868 MHz/4.8 kbps −66 dBc Configuration 868 MHz/100 kbps −39 dBc OCCUPIED BANDWIDTH Occupied bandwidth is the bandwidth containing 99% of the total integrated power; spectrum analyzer settings: resolution bandwidth = 100 Hz, video bandwidth = 300 Hz Configuration 868 MHz/4.8 kbps 7.8 kHz Configuration 868 MHz/100 kbps 225 kHz SPURIOUS EMISSIONS (EXCLUDING Measured conductively at antenna input; RF frequency = HARMONICS) 868 MHz Receive <1 GHz −77 dBm 1 GHz to 4 GHz −50 dBm Transmit PA2, 17dBm output power, transmitting continuous carrier wave <1 GHz −59 dBc 1 GHz to 4 GHz −66 dBc HARMONIC EMISSIONS Measured conductively at antenna input, transmitting continuous carrier wave; RF frequency = 868 MHz 13 dBm Output Power PA1 Second Harmonic −53 dBc Third Harmonic −78 dBc Seventh Harmonic −95 dBc 17 dBm Output Power PA2 Second Harmonic −51 dBc Third Harmonic −70 dBc All Other Harmonics <−100 dBc

Rev. A | Page 16 of 55 Data Sheet ADF7030-1

902 MHz to 928 MHz Unless otherwise noted, the configurations detailed in Table 14 are used to specify the performance of the ADF7030-1 in Table 15. All measurements are performed on the EV-ADF70301-868BZ evaluation board, unless otherwise noted. The EV-ADF70301-868BZ uses a separate transmit/receive match design and a 26 MHz TCXO reference.

Table 14. Configurations in the 902 MHz to 928 MHz Frequency Band RF Data Frequency Channel IF Receiver Configuration Frequency Rate Deviation Spacing Frequency Bandwidth Packet Setup for Packet Based Name (MHz) (kbps) Modulation (kHz) (kHz) (kHz) (kHz) Testing 915 MHz/ 915 50 2GFSK 25 200 180.55 135.42 Preamble = 0xAAAAAAAA, sync word = 50 kbps 0x904E, payload length = 100 bytes, CRC = 2 bytes 915 MHz/ 915 150 2GFSK 37.5 400 325.0 243.75 Preamble = 150 kbps 0xAAAAAAAAAAAAAAAAAAAAAAAA , sync word = 0xFF7D7F5D, payload length = 100 bytes, CRC = 2 bytes 915 MHz/ 915 300 2GFSK 120 600 406.25 395 Preamble = 0xAAAAAAAA, sync word = 300 kbps 0xF672, payload length = 23 bytes, CRC = 2 bytes

Table 15. 902 MHz to 928 MHz Specifications Parameter Min Typ Max Unit Test Conditions/Comments 2GFSK SENSITIVITY, PER Configuration 915 MHz/50 kbps −109.2 dBm At PER = 5%, FEC disabled, AFC enabled, RF frequency error range = ±40 ppm Configuration 915 MHz/150 kbps −100.7 dBm At PER = 5%, FEC disabled, AFC enabled, RF frequency error range = ±40 ppm Configuration 915 MHz/300 kbps −98.8 dBm At PER = 5%, AFC disabled, RF frequency error range = ±11.5 ppm CHANNEL SELECTIVITY AND BLOCKING— Desired signal 3 dB above the input sensitivity level BER-BASED TEST METHOD (BER = 0.1%), carrier wave interferer power level increased until BER = 0.1%, AFC disabled Configuration 915 MHz/150 kbps Adjacent Channel (±400 kHz) 49 dB Alternate Channel (±800 kHz) 56 dB ±2 MHz 66 dB ±10 MHz 75 dB ±20 MHz 80 dB CHANNEL SELECTIVITY AND BLOCKING— Desired signal 3 dB above the input sensitivity level PER-BASED TEST METHOD (PER = 5%), carrier wave interferer power level increased until PER = 5%, image calibrated Configuration 915 MHz/50 kbps FEC disabled, AFC enabled Adjacent Channel (±200 kHz) 44 dB Alternate Channel (−400 kHz) 36 dB Alternate Channel (400 kHz) 52 ±2 MHz 68 dB ±10 MHz 77 dB Configuration 915 MHz/150 kbps FEC disabled, AFC enabled Adjacent Channel (±400 kHz) 43 dB Alternate Channel (−800 kHz) 48 dB Alternate Channel (800 kHz) 53 ±2 MHz 59 dB ±10 MHz 68 dB Configuration 915 MHz/300 kbps AFC disabled Adjacent Channel (±600 kHz) 36 dB Alternate Channel (±1200 kHz) 53 dB ±2 MHz 57 dB ±10 MHz 67 dB

Rev. A | Page 17 of 55 ADF7030-1 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments COCHANNEL REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), carrier wave interferer power level increased until PER = 5% Configuration 915 MHz/50 kbps −9 dB Configuration 915 MHz/150 kbps −8 dB Configuration 915 MHz/300 kbps −7 dB UNCALIBRATED IMAGE REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), carrier wave interferer power level increased until PER = 5% Configuration 915 MHz/50 kbps 37 dB Configuration 915 MHz/150 kbps 36 dB Configuration 915 MHz/300 kbps 35 dB ACP Configuration 915 MHz/50 kbps Spectrum analyzer settings: resolution bandwidth = 300 Hz, video bandwidth = 1 kHz Adjacent Channel (±200 kHz) −54 dBc Alternate Channel (±400 kHz) −61 dBc Configuration 915 MHz/150 kbps Spectrum analyzer settings: resolution bandwidth = 300 Hz, video bandwidth = 1 kHz Adjacent Channel (±400 kHz) −52 dBc Alternate Channel (±800 kHz) −65 dBc Configuration 915 MHz/300 kbps Spectrum analyzer settings: resolution bandwidth = 300 Hz, video bandwidth = 1 kHz Adjacent Channel (±600 kHz) −38 dBc Alternate Channel (±1200 kHz) −65 dBc OCCUPIED BANDWIDTH Occupied bandwidth is the bandwidth containing 99% of the total integrated power Configuration 915 MHz/50 kbps 86 kHz Spectrum analyzer settings: resolution bandwidth = 300 Hz, video bandwidth = 1 kHz Configuration 915 MHz/150 kbps 165 kHz Spectrum analyzer settings: resolution bandwidth = 300 Hz, video bandwidth = 1 kHz Configuration 915 MHz/300 kbps 326 kHz Spectrum analyzer settings: resolution bandwidth = 300 Hz, video bandwidth = 1 kHz SPURIOUS EMISSIONS (EXCLUDING Measured conductively at antenna input; HARMONICS) RF frequency = 915 MHz Receive <960 MHz −78 dBm 960 MHz to 12.7 GHz −51 dBm Transmit PA2, output power = 17 dBm, transmitting continuous carrier wave <960 MHz −61 dBc 960 MHz to 12.7 GHz −63 dBc HARMONIC EMISSIONS Measured conductively at antenna input, transmitting continuous carrier wave; RF frequency = 915 MHz 13 dBm Output Power PA1 Second Harmonic −52 dBc Third Harmonic −85 dBc Seventh Harmonic −91 dBc 17 dBm Output Power PA2 Second Harmonic −51 dBc Third Harmonic −68 dBc All Other Harmonics <−90 dBc

Rev. A | Page 18 of 55 Data Sheet ADF7030-1

EXTERNAL 26 MHZ OSCILLATOR The ADF7030-1 requires a 26 MHz reference clock. This reference can be a 26 MHz crystal oscillator operating in parallel mode and connected between the HFXTALP and HFXTALN pins. Alternatively, a 26 MHz TCXO can be dc-coupled to the HFXTALN input. A TCXO is typically used in narrow-band applications where the transmit and receive RF frequency must meet accuracies not supported by a crystal oscillator.

Table 16. Parameter Min Typ Max Unit Test Conditions/Comments DC-COUPLED TCXO HFXTALN pin, clipped sine wave TCXO Frequency 26 MHz Peak-to-Peak Voltage Level 0.8 1.8 V Voltage Level with Respect to Ground −0.1 +1.9 V Duty Cycle 40 60 % CRYSTAL OSCILLATOR Parallel resonant crystal Crystal Frequency 26 MHz Maximum Crystal ESR 50 Ω Crystal Oscillator Load Capacitance 12 pF HFXTALN, HFXTALP Pin Capacitance in Parallel with Crystal Oscillator 5 pF

LOW FREQUENCY OSCILLATOR

Table 17. Parameter Min Typ Max Unit Test Conditions/Comments 26 kHz INTERNAL RC OSCILLATOR Frequency 26 kHz After calibration Frequency Accuracy 0.2 % After calibration at 25°C Frequency Drift Temperature Coefficient 0.3 %/°C Voltage Coefficient 0.5 %/V Calibration Time 30 ms 32 kHz EXTERNAL OSCILLATOR Frequency 32.768 kHz Start-Up Time 1.45 sec

TEMPERATURE SENSOR

Table 18. Parameter Min Typ Max Unit Test Conditions/Comments TEMPERATURE SENSOR Range −40 +85 °C

Accuracy ±5 °C TA = −40°C to +85°C; calibrated at 25°C

Rev. A | Page 19 of 55 ADF7030-1 Data Sheet

DIGITAL INPUT/OUTPUT

Table 19. Parameter Symbol Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS Input Voltage

High VINH 0.7 × VDD V

Low VINL 0.2 × VDD V

Input Capacitance CIN 3.6 pF LOGIC OUTPUTS Output Voltage

High VOH VDD − 0.4 V IOH = 500 µA

Low VOL 0.4 V IOL = 500 µA

Maximum GPIO Drive Strength for VOH 2 mA

Maximum GPIO Drive Strength for VOL 2 mA

DIGITAL TIMING

Table 20. SPI Interface Timing Parameter Description Min Typ Max Unit t1 Falling edge to MISO setup time 15 ns t2 CS low to SCLK setup time 40 ns t3 SCLK high time 40 ns t4 SCLK low time 40 ns t5 SCLK period 80 ns t6 SCLK falling edge to MISO delay 10 ns t7 MOSI to SCLK rising edge setup time 5 ns t8 MOSI to SCLK rising edge hold time 5 ns t9 SCLK falling edge to CS hold time 40 ns t10 CS high time 80 ns t11 CS low to MISO high wake-up time 92 µs 1 t12 MISO high to SCLK setup time SCLK low time µs t13 RST low time 2 µs

1 The minimum for t12 changes with the SCLK frequency.

Rev. A | Page 20 of 55 Data Sheet ADF7030-1

Timing Diagrams

CS 10

2 3 4 5 9

SCLK

1 6

MISO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 0 X BIT 7

8 7

MOSI 7 6 5 4 3 2 1 0 7

14373-002 Figure 2. SPI Interface Timing

12 9

SCLK 7 6 5 4 3 2 1 0

11 6

MISO X

SPI STATE

SLEEP WAKE UP SPI READY 14373-003 Figure 3. PHY_SLEEP to SPI Ready State Timing

t13

RST

14373-004 Figure 4. Reset Pin (RST) Timing

Rev. A | Page 21 of 55 ADF7030-1 Data Sheet

ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All VBATx pins must be tied Stresses at or above those listed under Absolute Maximum together. The LNAIN1 and LNAIN2 inputs must be ac-coupled. Ratings may cause permanent damage to the product. This is a Table 21. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational Supply Pins section of this specification is not implied. Operation beyond VBAT1, VBAT2, VBAT3, VBAT4, VBAT5, −0.3 V to +3.9 V the maximum operating conditions for extended periods may VBAT6 to Ground affect product reliability. LNAIN1, LNAIN2 −0.3 V to +1.98 V Connect the exposed pad of the 40-lead LFCSP device to PAOUT1, PAOUT2 −0.3 V to +3.9 V ground. HFXTALP, HFXTALN −0.3 V to +1.98 V This device is a high performance, RF integrated circuit with an CLF −0.3 V to +1.98 V ESD rating as indicated in Table 21; it is ESD sensitive. Take proper CREG1, CREG2, CREG4, CREG5, CREG6, −0.3 V to +1.98 V precautions for handling and assembly. CREG7 CREG3 −0.3 V to +3.9 V ESD CAUTION Digital Inputs/Outputs, GPIOx −0.3 V to +3.9 V MOSI, MISO, SCLK, CS, RST −0.3 V to +3.9 V Industrial Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C

θJA Thermal Impedance 26°C/W ESD Rating, Human Body Model (HBM) 40-Lead LFCSP Package LNAIN1, LNAIN2, PAOUT1, PAOUT2 ±250 V All Other Pins ±2 kV 48-Lead LQFP Package LNAIN1, LNAIN2, PAOUT1, PAOUT2 ±250 V All Other Pins ±2 kV ESD Rating, Field Induced Charged Device Model (FICDM) 40-Lead LFCSP Package

LNAIN1, LNAIN2, PAOUT1, PAOUT2 ±1250 V All Other Pins ±1250 V 48-Lead LQFP Package LNAIN1, LNAIN2, PAOUT1, PAOUT2 ±1250 V

All Other Pins ±1250 V Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 40 sec

Rev. A | Page 22 of 55 Data Sheet ADF7030-1

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VBAT6 CLF CREG7 CREG6 HFXTALN HFXTALP CREG5 DNC GPIO7 DNC 32 31 40 39 38 37 36 35 34 33

RST 1 30 DNC VBAT1 2 29 GPIO6 CREG1 3 28 CS VBAT2 4 ADF7030-1 27 SCLK CREG2 5 26 MISO TOP VIEW LNAIN1 6 (Not to Scale) 25 MOSI LNAIN2 7 24 VBAT5 DNC 8 23 VBAT4 CREG3 9 22 GPIO5 DNC 10 21 GPIO4 11 12 13 14 15 16 17 18 19 20 DNC DNC GPIO1 GPIO2 GPIO0 GPIO3 VBAT3 CREG4 PAOUT1 PAOUT2 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. CONNECT THE EXPOSED PAD TO GROUND. 14373-005 Figure 5. 40-Lead LFCSP Pin Configuration

Table 22. 40-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1 RST External Reset, Active Low. 2 VBAT1 Power Supply Pin 1 to the Internal Regulators. 3 CREG1 Regulator Output 1. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Also, place a 1.2 nF capacitor between this pin and the CLF pin. 4 VBAT2 Power Supply Pin 2 to the Internal Regulators. 5 CREG2 Regulator Output 2. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 6 LNAIN1 LNA Input 1. 7 LNAIN2 LNA Input 2. 8 DNC Do Not Connect. Do not connect to this pin. 9 CREG3 Regulator Output 3. Connect this pin to the PA choke inductor to provide bias to the PA. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 10 DNC Do Not Connect. Do not connect to this pin. 11 DNC Do Not Connect. Do not connect to this pin. 12 PAOUT1 Single-Ended PA1 Output. 13 PAOUT2 Single-Ended PA2 Output. 14 VBAT3 Power Supply Pin 3 to the Internal Regulators. 15 CREG4 Regulator Output 4. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 16 GPIO0 Digital GPIO Pin 0. 17 GPIO1 Digital GPIO Pin 1. 18 GPIO2 Digital GPIO Pin 2. 19 GPIO3 Digital GPIO Pin 3. 20 DNC Do Not Connect. Do not connect to this pin. 21 GPIO4 Digital GPIO Pin 4. 22 GPIO5 Digital GPIO Pin 5. 23 VBAT4 Power Supply Pin 4 to the Internal Regulators. 24 VBAT5 Power Supply Pin 5 to the Internal Regulators. 25 MOSI Serial Port Master Output/Slave Input. 26 MISO Serial Port Master Input/Slave Output. 27 SCLK Serial Port Clock.

28 CS Chip Select (Active Low). A pull-up resistor of 100 kΩ to VDD is recommended to prevent the host processor from inadvertently waking the ADF7030-1 from sleep.

Rev. A | Page 23 of 55 ADF7030-1 Data Sheet

Pin No. Mnemonic Description 29 GPIO6 Digital GPIO Pin 6. 30 DNC Do Not Connect. Do not connect to this pin. 31 DNC Do Not Connect. Do not connect to this pin. 32 GPIO7 Digital GPIO Pin 7. 33 DNC Do Not Connect. Do not connect to this pin. 34 CREG5 Regulator Output 5. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 35 HFXTALP Positive Reference Input. If a 26 MHz TCXO is used as the external reference, do not connect this pin. If a 26 MHz XTAL is used as the reference, connect this pin to the XTAL. 36 HFXTALN Negative Reference Input. If a 26 MHz TCXO is used as the external reference, connect this pin to the TCXO output. If a 26 MHz XTAL is used as the reference, connect this pin to the XTAL. 37 CREG6 Regulator Output 6. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 38 CREG7 Regulator Output 7. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 39 CLF External Loop Filter Capacitor. Place a 1.2 nF capacitor between this pin and the CREG1 pin. 40 VBAT6 Power Supply Pin 6 to the Internal Regulators. EPAD Exposed Pad. Connect the exposed pad to ground.

Rev. A | Page 24 of 55 Data Sheet ADF7030-1

GPIO6 GPIO7 GND CREG5 GND HFXTALP HFXTALN CREG6 CREG7 GND CLF VBAT6 48 47 46 45 44 43 42 41 40 39 38 37

GND 1 36 GND RST 2 35 GND VBAT1 3 34 CS CREG1 4 33 SCLK DNC 5 32 MISO VBAT2 6 ADF7030-1 31 MOSI TOP VIEW CREG2 7 (Not to Scale) 30 VBAT5 GND 8 29 VBAT4 LNAIN1 9 28 GPIO5 LNAIN2 10 27 GPIO4 GND 11 26 GND CREG3 12 25 GPIO3

13 14 15 16 17 18 19 20 21 22 23 24 DNC GND GND GND GND GPIO0 GPIO1 GPIO2 VBAT3 CREG4 PAOUT1 PAOUT2

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 14373-006 Figure 6. 48-Lead LQFP Pin Configuration

Table 23. 48-Lead LQFP Pin Function Descriptions Pin No. Mnemonic Description 1 GND Connection to Ground. 2 RST External Reset, Active Low. 3 VBAT1 Power Supply Pin 1 to the Internal Regulators. 4 CREG1 Regulator Output 1. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Also, place a 1.2 nF capacitor between this pin and the CLF pin. 5 DNC Do Not Connect. Do not connect to this pin. 6 VBAT2 Power Supply Pin 2 to the Internal Regulators. 7 CREG2 Regulator Output 2. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 8 GND Connection to Ground. 9 LNAIN1 LNA Input 1. 10 LNAIN2 LNA Input 2. 11 GND Connection to Ground. 12 CREG3 Regulator Output 3. Connect this pin to the PA choke inductor to provide bias to the PA. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 13 GND Connection to Ground. 14 PAOUT1 Single-Ended PA1 Output. 15 GND Connection to Ground. 16 PAOUT2 Single-Ended PA2 Output. 17 GND Connection to Ground. 18 DNC Do Not Connect. Do not connect to this pin. 19 VBAT3 Power Supply Pin 3 to the Internal Regulators. 20 CREG4 Regulator Output 4. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 21 GND Connection to Ground. 22 GPIO0 Digital GPIO Pin 0. 23 GPIO1 Digital GPIO Pin 1. 24 GPIO2 Digital GPIO Pin 2. 25 GPIO3 Digital GPIO Pin 3. 26 GND Connection to Ground. 27 GPIO4 Digital GPIO Pin 4. 28 GPIO5 Digital GPIO Pin 5. 29 VBAT4 Power Supply Pin 4 to the Internal Regulators. Rev. A | Page 25 of 55 ADF7030-1 Data Sheet

Pin No. Mnemonic Description 30 VBAT5 Power Supply Pin 5 to the Internal Regulators. 31 MOSI Serial Port Master Output/Slave Input. 32 MISO Serial Port Master Input/Slave Output. 33 SCLK Serial Port Clock.

34 CS Chip Select (Active Low). A pull-up resistor of 100 kΩ to VDD is recommended to prevent the host processor from inadvertently waking the ADF7030-1 from sleep. 35 GND Connection to Ground. 36 GND Connection to Ground. 37 GPIO6 Digital GPIO Pin 6. 38 GPIO7 Digital GPIO Pin 7. 39 GND Connection to Ground. 40 CREG5 Regulator Output 5. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 41 GND Connection to Ground. 42 HFXTALP Positive Reference Input. If a 26 MHz TCXO is used as the external reference, do not connect this pin. If a 26 MHz XTAL is used as the reference, connect this pin to the XTAL. 43 HFXTALN Negative Reference Input. If a 26 MHz TCXO is used as the external reference, connect this pin to the TCXO output. If a 26 MHz XTAL is used as the reference, connect this pin to the XTAL. 44 CREG6 Regulator Output 6. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 45 CREG7 Regulator Output 7. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. 46 GND Connection to Ground. 47 CLF External Loop Filter Capacitor. Place a 1.2 nF capacitor between this pin and the CREG1 pin. 48 VBAT6 Power Supply Pin 6 to the Internal Regulators.

Rev. A | Page 26 of 55 Data Sheet ADF7030-1

TYPICAL PERFORMANCE CHARACTERISTICS 169 MHZ—RECEIVE 80 –121.0dBm –118.0dBm 70 –111.0dBm –50dBm 0dBm 60

TE (%) 50 A

BLOCKING (dB) 20 ACKET ERROR R

P +85°C, 3.0V 10 +85°C, 2.2V +25°C, 3.0V 0 +25°C, 2.2V –40°C, 3.0V –40°C, 2.2V –10 –3 –2 –1 0 1 2 3 –200 –175 –150 –125 –100 –75 –50 –25 0 25 50 75 100 RF FREQUENCY ERROR (kHz) 14373-310 14373-007 INTERFERER FREQUENCY OFFSET (kHz) Figure 7. Packet Error Rate vs. RF Frequency Error and RF Input Power, Figure 10. Receiver Close-In Blocking vs. Interferer Frequency Offset, Temperature, Configuration 169.43125 MHz/2.4 kbps; AFC Enabled; VDD = 3.0 V; and VDD; Configuration 169.43125 MHz/2.4 kbps; Unmodulated Interferer; TA = 25°C Desired Signal 3 dB Above the Sensitivity Level of PER = 5%; PER-Based Test

110 –119.8dBm –116.8dBm 100 –109.8dBm –50dBm 90 0dBm 80

TE (%) 70 A 60 50

BLOCKING (dB) 30 ACKET ERROR R

P 20 +85°C, 3.0V +85°C, 2.2V 10 +25°C, 3.0V +25°C, 2.2V 0 –40°C, 3.0V –40°C, 2.2V 1 8 –10 00 –3 –2 –1 0 1 2 3 - –27–24–21–18–15–12 –9 –6 –3 0 3 6 9 12 15 18 21 24 27 1 14373-3 RF FREQUENCY ERROR (kHz) 14373 INTERFERER FREQUENCY OFFSET (MHz) Figure 8. Packet Error Rate vs. RF Frequency Error and RF Input Power, Figure 11. Receiver Wideband Blocking vs. Interferer Frequency Offset, Configuration 169.43125 MHz/4.8 kbps; AFC Enabled; VDD = 3.0 V; Temperature, and VDD; Configuration 169.43125 MHz/2.4 kbps; TA = 25°C Unmodulated Interferer; Desired Signal 3 dB Above the Sensitivity Level of PER = 5%; PER-Based Test

100 3.0 +85°C, 3.0V ERROR STANDARD DEVIATION 90 +85°C, 2.2V +25°C, 3.0V 2.5 +25°C, 2.2V 80 –40°C, 3.0V –40°C, 2.2V 2.0 70

TE (%) 1.5 A 60

50 1.0

40 0.5 RSSI ERROR (dB) 30 ACKET ERROR R 0 P 20 –0.5 10

0 –1.0 –127 –126 –125 –124 –123 –122 –121 –120 –119 –125 –115 –105 –95 –85 –75 –65 –55 –45 –35 –25

RECEIVE INPUT POWER (dBm) 14373-312 RECEIVED POWER (dBm) 14373-309 Figure 9. Packet Error Rate vs. RF Input Power, Temperature and VDD Figure 12. Packet RSSI Error vs. Rx Input Power with One-Point Calibration Configuration 169.43125 MHz/2.4 kbps at −50 dBm, VDD = 3.0 V, TA = 25°C, Configuration 169.43125 MHz/2.4 kbps (Error is Based on the Mean RSSI of 100 Packets)

Rev. A | Page 27 of 55 ADF7030-1 Data Sheet

169 MHZ—TRANSMIT –110 16 –115 13 10 –120 7 –125 4 –130 1 –2 –135 –5 –140 –8 –145 –11 –14 –150 –17

PHASE NOISE (dBc/Hz) PHASE PA_COARSE = 1 –155 –20

PA1 OUTPUT POWER (dBm) PA_COARSE = 2 PA_COARSE = 3 –160 –23 PA_COARSE = 4 –26 –165 PA_COARSE = 5 –29 PA_COARSE = 6 –170 –32 1k 10k 100k 1M 10M 100M 2 20 200 14373-017 FREQUENCY OFFSET (Hz) 14373-014 PA_FINE SETTING Figure 13. Phase Noise vs. Frequency Offset, RF Frequency = 169.43125 MHz, Figure 16. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting PA2 Output Power = 17 dBm, VDD = 3.0 V, TA = 25°C with PA_FINE on a Log Scale, RF Frequency = 169.43125 MHz, VDD = 3.0 V, TA = 25°C

0.5 0.5 +85°C, 3.6V T = 25°C +85°C, 3.6V 0.4 +85°C, 3.0V VBATx = 3V 0.4 +85°C, 3.0V +85°C, 2.85V +85°C, 2.85V 0.3 +25°C, 3.6V 0.3 +25°C, 3.6V +25°C, 2.85V +25°C, 2.85V –40°C, 3.6V 0.2 0.2 –40°C, 3.6V –40°C, 3.0V –40°C, 3.0V –40°C, 2.85V 0.1 0.1 –40°C, 2.85V

0 0

–0.1 –0.1

–0.2 –0.2

–0.3 –0.3 CHANGE IN OUTPUT POWER (dB) CHANGE IN OUTPUT POWER (dB)

–0.4 –0.4

–0.5 –0.5 1 3 5 7 9 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 17 19 –9 –7 –5 –3 –1 11 13 15 –17 –15 –13 –11

PA2 OUTPUT POWER (dBm) AT T = 25°C, VBAT = 3.0V 14373-018 PA1 OUTPUT POWER (dBm) 14373-015 Figure 14. Change in PA1 Output Power vs. Temperature, and VDD with Figure 17. Change in PA2 Output Power vs. Temperature, and VDD with PA_COARSE = 6, RF Frequency = 169.43125 MHz; Variation Above 11 dBm Can PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = Be Improved by Matching the PA for Higher Output Power 169.43125 MHz

45 80

+85°C, 3.6V 40 70 +85°C, 3.6V +85°C, 3.0V +85°C, 3.0V 35 +85°C, 2.2V +85°C, 2.85V +25°C, 3.6V 60 +25°C, 3.6V +25°C, 3.0V +25°C, 3.0V 30 +25°C, 2.2V +25°C, 2.85V –40°C, 3.6V 50 –40°C, 3.6V 25 –40°C, 3.0V –40°C, 3.0V –40°C, 2.2V 40 –40°C, 2.85V 20 30 15

10 20 VBATx SUPPLY CURRENT (mA) VBATx SUPPLY CURRENT (mA)

5 10

0 3 7 9 1 5 0 –7 –9 –3 –1 11 –5 13 15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 17 19 –17 –15 –11 –13

PA2 OUTPUT POWER (dBm) 14373-019 PA1 OUTPUT POWER (dBm) 14373-016

Figure 15. VBATx Supply Current vs. PA1 Output Power, Temperature, and Figure 18. VBATx Supply Current vs. PA2 Output Power, Temperature, and VDD, VDD with PA_COARSE = 6, RF Frequency = 169.43125 MHz PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 169.43125 MHz

Rev. A | Page 28 of 55 Data Sheet ADF7030-1

18 3.0

14 2.5 2.0 10 1.5 6 1.0

2 0.5 –2 0

–6 –0.5 –1.0 –10 PA_COARSE = 5 –1.5 PA2 OUTPUT POWER (dBm) PA_COARSE = 6 –14 PA_COARSE = 7 FREQUENCY DEVIATION (kHz) –2.0 PA_COARSE = 8 –18 PA_COARSE = 9 –2.5 PA_COARSE = 10 –22 –3.0 2 20 200 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 14373-022 PA_FINE SETTING 14373-020 TRANSMIT SYMBOL (Bits) Figure 19. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting Figure 21. Transmit Eye Diagram, PA2 Output Power = 17 dBm, with PA_FINE on a Logarithmic Scale, VDD = 3.0 V, TA = 25°C, Configuration 169.43125 MHz/2.4 kbps, VDD = 3.0 V, TA = 25°C RF Frequency = 169 MHz

0 20 +85°C, 3.6V –10 +85°C, 3.0V +85°C, 2.85V 0 –20 +25°C, 3.6V –30 +25°C, 3.0V +25°C, 2.85V –40 –20 –40°C, 3.6V –40°C, 3.0V –50 –40°C, 2.85V –60 –40 –70 POWER (dBm) POWER (dBm) –80 –60 –90 –100 –80

–110 –120 –100 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH –20 –15 –10 –5 0 5 10 15 20 14373-021 HARMONIC FREQUENCY OFFSET (kHz) 14373-023 Figure 20. Conductive Harmonic Emission Level, PA2 Output Power = Figure 22. Transmit Spectrum, PA2 Output Power = 17 dBm, 17 dBm, Carrier Unmodulated, RF Frequency = 169.43125 MHz, VDD = 3.0 V, Configuration 169.43125 MHz/2.4 kbps, VDD = 3.0 V, TA = 25°C TA = 25°C

Rev. A | Page 29 of 55 ADF7030-1 Data Sheet

433 MHZ—RECEIVE 100 90 –108.4dBm 90 –105.4dBm 80 –98.4dBm –50dBm 80 0dBm 70

70 60 TE (%) A 60 50

50 40

40 30 BLOCKING (dB) 30 20 ACKET ERROR R

P +85°C, 3.0V 20 10 +85°C, 2.2V +25°C, 3.0V +25°C, 2.2V 10 0 –40°C, 3.0V –40°C, 2.2V 0 –10 –20 –15 –10 –5 0 5 10 15 20 –27–24–21–18–15–12 –9 –6 –3 0 3 6 9 12 15 18 21 24 27

INTERFERER FREQUENCY OFFSET (MHz) 14373-325 RF FREQUENCY ERROR (kHz) 14373-323 Figure 23. Packet Error Rate vs. RF Frequency Error and RF Input Power; Figure 25. Receiver Wideband Blocking vs. Interferer Frequency Offset, Configuration 433 MHz/50 kbps, AFC Enabled; VDD = 3.0 V; TA = 25°C Temperature, and VDD; Configuration 433 MHz/50 kbps; Unmodulated Interferer; Desired Signal 3 dB Above the Sensitivity Level of PER = 5%; PER-Based Test

100 4.0 +85°C, 3.0V ERROR +85°C, 2.2V 3.5 STANDARD DEVIATION 90 +25°C, 3.0V +25°C, 2.2V 3.0 80 –40°C, 3.0V –40°C, 2.2V 2.5 70

TE (%) 2.0 A 60 1.5 50 1.0

40 0.5

RSSI ERROR (dB) 0 30 ACKET ERROR R

P –0.5 20 –1.0 10 –1.5 0 –2.0 –115 –114 –113 –112 –111 –110 –109 –108 –107 –112 –102 –92 –82 –72 –62 –52 –42 –32 –22 14373-324 RECEIVED POWER (dBm) RECEIVE INPUT POWER (dBm) 14373-326 Figure 24. Packet Error Rate vs. RF Input Power, Temperature, and VDD; Figure 26. Packet RSSI Error vs. RX Input Power with One-Point Calibration at Configuration 433 MHz/50 kbps −77 dBm; Configuration 433 MHz/50 kbps; VDD = 3.0 V; TA = 25°C (Error is Based on the Mean RSSI of 100 Packets)

Rev. A | Page 30 of 55 Data Sheet ADF7030-1

433 MHZ—TRANSMIT –100 16 –105 13 10 –110 7 –115 4 –120 1 –2 –125 –5 –130 –8 –135 –11 –14 –140 –17 PA_COARSE = 1 PHASE NOISE (dBc/Hz) PHASE –145 –20 PA_COARSE = 2 PA1 OUTPUT POWER (dBm) PA_COARSE = 3 –23 –150 PA_COARSE = 4 –26 PA_COARSE = 5 –155 –29 PA_COARSE = 6 –160 –32 1k 10k 100k 1M 10M 100M 2 20 200 14373-032 FREQUENCY OFFSET (Hz) 14373-029 PA_FINE SETTING Figure 27. Phase Noise vs. Frequency Offset, RF Frequency = 433 MHz, PA1 Output Figure 30. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting with Power = 10 dBm, VDD = 3.0 V, TA = 25°C PA_FINE on a Logarithmic Scale, RF Frequency = 433 MHz, VDD = 3.0 V, TA = 25°C

0 0.5 +85°C, 3.6V T = 25°C –10 0.4 +85°C, 3.0V VBATx = 3V +85°C, 2.85V –20 0.3 +25°C, 3.6V –30 +25°C, 2.85V 0.2 –40°C, 3.6V –40 –40°C, 3.0V –50 0.1 –40°C, 2.85V –60 0 –70

–0.1 POWER (dBm) –80 –0.2 –90

–0.3 –100 CHANGE IN OUTPUT POWER (dB) –110 –0.4 –120 –0.5 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 1 3 5 7 9 –9 –7 –5 –3 –1 11 13 15

HARMONIC 14373-033 –17 –15 –13 –11

PA1 OUTPUT POWER (dBm) 14373-030 Figure 31. Conductive Harmonic Emission Level, PA1 Output Power = Figure 28. Change in PA1 Output Power vs. Temperature, and VDD with 10 dBm, RF Frequency = 433.92 MHz, VDD = 3.0 V, TA = 25°C PA_COARSE = 6, RF Frequency = 433 MHz 30 50 +85°C, 3.6V 25 45 +85°C, 3.0V +85°C, 2.2V 20 +25°C, 3.6V 40 15 +25°C, 3.0V 35 +25°C, 2.2V 10 –40°C, 3.6V 30 –40°C, 3.0V 5 –40°C, 2.2V 0 25 –5 20 –10 15 –15 FREQUENCY DEVIATION (kHz)

VBATx SUPPLY CURRENT (mA) 10 –20 –25 5 –30 0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 1 3 5 7 9 –9 –7 –5 –3 –1 11 13 15 14373-034 –17 –15 –13 –11 TRANSMIT SYMBOL (Bits)

PA1 OUTPUT POWER (dBm) 14373-031 Figure 32. Transmit Eye Diagram, PA2 Output Power = 17 dBm, Figure 29. VBATx Supply Current vs. PA1 Output Power, Temperature, and Configuration 433 MHz/50 kbps, VDD = 3.0 V, TA = 25°C VDD with PA_COARSE = 6, RF Frequency = 433 MHz

Rev. A | Page 31 of 55 ADF7030-1 Data Sheet

10 +85°C, 3.6V 0 +85°C, 3.0V –10 +85°C, 2.85V +25°C, 3.6V –20 +25°C, 3.0V +25°C, 2.85V –30 –40°C, 3.6V –40°C, 3.0V –40 –40°C, 2.85V

–50

POWER (dBm) –60

–70

–80

–90

–100 –300 –200 –100 0 100 200 300

FREQUENCY OFFSET (kHz) 14373-035 Figure 33. Transmit Spectrum, PA1 Output Power = 10 dBm, Configuration 433 MHz/50 kbps, VDD = 3.0 V, TA = 25°C

Rev. A | Page 32 of 55 Data Sheet ADF7030-1

460 MHZ—RECEIVE 100 100 –115.4dBm 90 –112.4dBm 90 –105.4dBm –50dBm 80 80 0dBm 70 70 TE (%)

A 60 60 50 50 40 40

BLOCKING (dB) 30 30 ACKET ERROR R 20 +85°C, 3.0V P +85°C, 2.2V 20 10 +25°C, 3.0V +25°C, 2.2V 10 –40°C, 3.0V 0 –40°C, 2.2V 0 –10 –3 –2 –1 0 1 2 3 –27–24–21–18–15–12 –9 –6 –3 0 3 6 9 12 15 18 21 24 27 14373-334 RF FREQUENCY ERROR (kHz) INTERFERER FREQUENCY OFFSET (MHz) 14373-337 Figure 34. Packet Error Rate vs. RF Frequency Error and RF Input Power; Figure 37. Receiver Wideband Blocking vs. Inteferer Frequency Offset, Configuration 460 MHz/7.2 kbps; AFC Enabled; VDD = 3.0 V; TA = 25°C Temperature, and VDD; Configuration 460 MHz/7.2 kbps; Unmodulated Interferer; Desired Signal 3 dB Above the Sensitivity Level of PER = 5%; PER-Based Test

100 2.0 +85°C, 3.0V ERROR 90 +85°C, 2.2V STANDARD DEVIATION +25°C, 3.0V +25°C, 2.2V 1.5 80 –40°C, 3.0V –40°C, 2.2V 70

TE (%) 1.0 A 60

50 0.5

RSSI ERROR (dB) 0 30 ACKET ERROR R P 20 –0.5 10

0 –1.0 –123 –122 –121 –120 –119 –118 –117 –116 –115 –114 –113 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

RECEIVED POWER (dBm) 14373-335 RECEIVE INPUT POWER (dBm) 14373-338

Figure 35. Packet Error Rate vs. RF Input Power, Temperature, and VDD; Figure 38. Packet RSSI Error vs. RF Input Power with One-Point Calibration at Configuration 460 MHz/7.2 kbps −77 dBm; Configuration 460 MHz/7.2 kbps, 7.2 kbps; VDD = 3.0 V; TA = 25°C (Error is Based on the Mean RSSI of 100 Packets)

15 BLOCKING (dB)

5 +85°C, 3.0V +85°C, 2.2V +25°C, 3.0V –5 +25°C, 2.2V –40°C, 3.0V –40°C, 2.2V –15 –100 –80 –60 –40 –20 0 20 40 60 80 100

INTERFERER FREQUENCY OFFSET (kHz) 14373-336 Figure 36. Receiver Close-In Blocking vs. Interferer Frequency Offset and Temperature and VDD; Configuration 460 MHz/7.2 kbps; Unmodulated Interferer; Desired Signal 3 dB Above the Sensitivity Level of PER = 5%; PER-Based Test

Rev. A | Page 33 of 55 ADF7030-1 Data Sheet

460 MHZ—TRANSMIT –100 18 –105 14 –110 10 –115 –120 6 –125 2 –130 –2 –135

–140 –6

PHASE NOISE (dBc/Hz) PHASE PA_COARSE = 5 –145 PA2 OUTPUT POWER (dBm) –10 PA_COARSE = 6 –150 PA_COARSE = 7 PA_COARSE = 8 –14 –155 PA_COARSE = 9 PA_COARSE = 10 –160 –18 1k 10k 100k 1M 10M 100M 2 20 200 14373-044 FREQUENCY OFFSET (Hz) 14373-041 PA_FINE SETTING Figure 39. Phase Noise vs. Frequency Offset, RF Frequency = 460 MHz, PA2 Output Figure 42. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting Power = 17 dBm, VDD = 3.0 V, TA = 25°C with PA_FINE on a Logarithmic Scale, PAOLDO_VOUT_CON=15, RF Frequency = 460 MHz, VDD = 3.0 V, TA = 25°C

0.5 0 T = 25°C FUNDAMENTAL = 450.0125MHz –10 FUNDAMENTAL = 460MHz 0.4 VBATx = 3V FUNDAMENTAL = 469.9875MHz –20 0.3 –30 0.2 –40

0.1 –50

0 –60 –70

–0.1 +85°C, 3.6V POWER (dBm) +85°C, 3.0V –80 –0.2 +85°C, 2.85V –90 +25°C, 3.6V –0.3 +25°C, 2.85V CHANGE IN OUTPUT POWER (dB) –100 –40°C, 3.6V –0.4 –40°C, 3.0V –110 –40°C, 2.85V –120 –0.5 ND RD TH TH TH TH TH TH TH –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 17 19 2 3 4 5 6 7 8 9 10

HARMONIC 14373-059 PA2 OUTPUT POWER (dBm) 14373-042 Figure 40. Change in PA2 Output Power vs. Temperature, and VDD with Figure 43. Conductive Harmonic Emission Level, PA2 Output Power = PA_COARSE = 10, PAOLDO_VOUT_CON=15, RF Frequency = 460 MHz; Variation 17 dBm, RF Frequency = 460 MHz, VDD = 3.0 V, TA = 25°C Above 15 dBm Can Be Improved by Matching the PA for Higher Output Power

60 30 +85°C, 3.6V 50 +85°C, 3.0V 25 +85°C, 2.85V +25°C, 3.6V 20 +25°C, 3.0V 40 +25°C, 2.2V 15 –40°C, 3.6V –40°C, 3.0V 10 30 –40°C, 2.85V 0

20 –10

–15 VBATx SUPPLY CURRENT (mA) 10 FREQUENCY DEVIATION (kHz) –20

–25 0 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 17 19 –30

PA2 OUTPUT POWER (dBm) 14373-043 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

Figure 41. VBATx Supply Current vs. PA2 Output Power, Temperature, and TRANSMIT SYMBOL (Bits) 14373-045 VDD with PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 460 MHz Figure 44. Transmit Eye Diagram; PA2 Output Power = 17 dBm; Configuration 460 MHz/7.2 kbps; BT = 0.5; VDD = 3.0 V; TA = 25°C

Rev. A | Page 34 of 55 Data Sheet ADF7030-1

20 10

–10

–20 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V –30 +25°C, 3.6V +25°C, 3.0V POWER (dBm) –40 +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –50 –40°C, 2.85V FCC 90 MASK D –60

–70 –50 –40 –30 –20 –10 0 10 20 30 40 50

FREQUENCY OFFSET (kHz) 14373-046 Figure 45. Transmit Spectrum, PA2 Output Power = 17 dBm, Configuration 460 MHz/7.2 kbps, BT = 0.5, VDD = 3.0 V, TA = 25°C; Margin to the Mask Can Be Improved by Reducing the BT or By Reducing the Data Rate

Rev. A | Page 35 of 55 ADF7030-1 Data Sheet

868 MHZ—RECEIVE 100 100 –118.2dBm +85°C, 3.0V 90 –115.2dBm 90 +85°C, 2.2V –108.2dBm +25°C, 3.0V –50dBm +25°C, 2.2V 80 0dBm 80 –40°C, 3.0V –40°C, 2.2V 70 70 TE (%) TE (%) A 60 A 60

50 50

40 40

30 30 ACKET ERROR R ACKET ERROR R P P 20 20

10 10

0 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 –111 –110 –109 –108 –107 –106 –105 –104 –103

RF FREQUENCY ERROR (kHz) 14373-346 RECEIVED POWER (dBm) 14373-349 Figure 46. Packet Error Rate vs. RF Frequency Error and RF Input Power, Figure 49. Packet Error Rate vs. Rx Input Power, Temperature, and VDD; Configuration 868 MHz/4.8 kbps, AFC Enabled, VDD = 3.0 V, TA = 25°C Configuration 868 MHz/100 kbps

100 65 –106.2dBm 90 –103.2dBm –96.2dBm 55 –50dBm 80 0dBm 45 70 TE (%)

A 35 60

50 25

40 15 BLOCKING (dB) 30 ACKET ERROR R

P 5 +85°C, 3.0V 20 +85°C, 2.2V +25°C, 3.0V –5 +25°C, 2.2V 10 –40°C, 3.0V –40°C, 2.2V 0 –15 –45 –30 –15 0 15 30 45 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 14373-350 RF FREQUENCY ERROR (kHz) 14373-347 INTERFERER FREQUENCY OFFSET (kHz) Figure 47. Packet Error Rate vs. RF Frequency Error and RF Input Power, Figure 50. Receiver Close-In Blocking vs. Interferer Frequency Offset, Temperature, Configuration 868 MHz/100 kbps, AFC Enabled, VDD = 3.0 V, TA = 25°C and VDD; Configuration 868 MHz/4.8 kbps, Unmodulated Interferer; Desired Signal 3 dB Above the Sensitivity Level of PER = 5% PER-Based Test

100 100 90 +85°C, 3.0V 90 +85°C, 2.2V 80 +25°C, 3.0V +25°C, 2.2V 70 80 –40°C, 3.0V –40°C, 2.2V 60 70

TE (%) 50 A 60 40 50 30 BLOCKING (dB) 40 20 10 +85°C, 3.0V 30

ACKET ERROR R +85°C, 2.2V P 0 +25°C, 3.0V 20 +25°C, 2.2V –10 –40°C, 3.0V 10 –40°C, 2.2V –20 –27–24–21–18–15–12 –9 –6 –3 0 3 6 9 12 15 18 21 24 27 0 –124 –123 –122 –121 –120 –119 –118 –117 –116 INTERFERER FREQUENCY OFFSET (MHz) 14373-351

RECEIVED POWER (dBm) 14373-348 Figure 51. Receiver Wideband Blocking vs. Interferer Frequency Offset, Figure 48. Packet Error Rate vs. RF Input Power, Temperature, and VDD; Temperature, and VDD; Configuration 868 MHz/4.8 kbps, Unmodulated Configuration 868 MHz/4.8 kbps Interferer; Desired Signal 3 dB Above the Sensitivity Level of PER = 5%; PER-Based Test

Rev. A | Page 36 of 55 Data Sheet ADF7030-1

90 2.0 ERROR 80 STANDARD DEVIATION 1.5 70

60 1.0 50

40 0.5

30 BLOCKING (dB) RSSI ERROR (dB) 0 20 +85°C, 3.0V 10 +85°C, 2.2V +25°C, 3.0V –0.5 +25°C, 2.2V 0 –40°C, 3.0V –40°C, 2.2V –10 –1.0 –27–24–21–18–15–12 –9 –6 –3 0 3 6 9 12 15 18 21 24 27 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 14373-352 INTERFERER FREQUENCY OFFSET (MHz) RECEIVE INPUT POWER (dBm) 14373-354 Figure 52. Receiver Wideband Blocking vs. Interferer Frequency Offset, Figure 54. Packet RSSI Error vs. Rx Input Power with One-Point Calibration at Temperature, VDD; Configuration 868 MHz/100 kbps; Unmodulated −70 dBm; Configuration 868 MHz/100 kbps; VDD = 3.0 V; TA = 25°C (Error is Interferer; Desired Signal 3 dB Above the Sensitivity Level of PER = 5%; Based on the Mean RSSI of 100 Packets) PER-Based Test

2.0 ERROR STANDARD DEVIATION 1.5

1.0

0.5

RSSI ERROR (dB) 0

–0.5

–1.0 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

RECEIVE INPUT POWER (dBm) 14373-353 Figure 53. Packet RSSI Error vs. Rx Input Power with One-Point Calibration at −77 dBm; Configuration 868 MHz/4.8 kbps; VDD = 3.0 V; TA = 25°C (Error is Based on the Mean RSSI of 100 Packets)

Rev. A | Page 37 of 55 ADF7030-1 Data Sheet

868 MHZ—TRANSMIT –100 60 –40°C, 2.2V –40°C, 3.0V –40°C, 3.6V –110 50 +25°C, 2.2V +25°C, 3.0V +25°C, 3.6V +85°C, 2.2V –120 40 +85°C, 3.0V +85°C, 3.6V

–130 CURRENT (mA) 30 Y

–140 20 TL SUPP PHASE NOISE (dBc/Hz) PHASE A VB –150 10

–160 0 1k 10k 100k 1M 10M 100M –17 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15

FREQUENCY OFFSET (Hz) 14373-057 PA1 OUTPUT POWER (dBm) 14373-258 Figure 55. Phase Noise vs. Frequency Offset, RF Frequency = 868 MHz, PA2 Figure 58. VBATx Supply Current vs. PA1 Output Power, Temperature, and Output Power = 17 dBm, VDD = 3.0 V, TA = 25°C VDD with PA_COARSE = 6, RF Frequency = 868 MHz

0.5 80 T = 25°C –40°C, 2.85V +85°C, 3.6V 0.4 VBATx = 3V –40°C, 3.0V +85°C, 3.0V 70 –40°C, 3.6V +85°C, 2.85V +25°C, 2.85V 0.3 +25°C, 3.6V +25°C, 3.0V +25°C, 2.85V 60 +25°C, 3.6V 0.2 +85°C, 2.85V –40°C, 3.6V +85°C, 3.0V –40°C, 3.0V 50 +85°C, 3.6V 0.1 –40°C, 2.85V

0 CURRENT (mA) 40 Y L –0.1 30

–0.2 T SUPP A 20 –0.3 VB CHANGE IN OUTPUT POWER (dB)

–0.4 10

–0.5 0 1 3 5 7 9

–9 –7 –5 –3 –1 11 15 13 11 9 7 5 3 1 1 3 5 7 9 11 13 15 17 19 –15 –13 –11

PA2 OUTPUT POWER (dBm) 14373-259 PA1 OUTPUT POWER (dBm) 14373-058 Figure 56. Change in PA1 Output Power vs. Temperature, and VDD with Figure 59. VBATx Supply Current vs. PA2 Output Power, Temperature, and PA_COARSE = 10, RF Frequency = 868 MHz VDD with PA_COARSE = 10, RF Frequency = 868 MHz

0.5 17 –40°C, 2.85V T = 25°C PA_COARSE = 1 0.4 –40°C, 3.0V VBATx = 3V 13 PA_COARSE = 2 –40°C, 3.6V PA_COARSE = 3 +25°C, 2.85V 9 PA_COARSE = 4 0.3 +25°C, 3.6V PA_COARSE = 5 +85°C, 2.85V 5 PA_COARSE = 6 0.2 +85°C, 3.0V +85°C, 3.6V 1 0.1 –3 0 –7

–0.1 –11 –15 –0.2 A1 OUTPUT POWER (dBm)

P –19 –0.3 CHANGE IN OUTPUT POWER (dB) –23 –0.4 –27 –0.5 –31 13 11 9 7 5 3 1 1 3 5 7 9 11 13 15 17 19 2 20 200 14373-257 PA2 OUTPUT POWER (dBm) PA_FINE SETTING 14373-260 Figure 57. Change in PA2 Output Power vs. Temperature, and VDD with Figure 60. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 868 MHz with PA_FINE on a Logarithmic Scale, RF Frequency = 868 MHz, VDD = 3.0 V, TA = 25°C

Rev. A | Page 38 of 55 Data Sheet ADF7030-1

19 3.0 17 2.5 15 13 2.0 11 9 1.5 7 1.0 5 3 0.5 1 0 –1 –3 –0.5 –5 –1.0 –7 PA_COARSE = 5 –9 PA_COARSE = 6 –1.5 PA2 OUTPUT POWER (dBm)

–11 PA_COARSE = 7 FREQUENCY DEVIATION (kHz) –13 PA_COARSE = 8 –2.0 –15 PA_COARSE = 9 –2.5 –17 PA_COARSE = 10 –19 –3.0 2 20 200 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 14373-062 PA_FINE SETTING 14373-060 TRANSMIT SYMBOL (Bits) Figure 61. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting Figure 63. Transmit Eye Diagram, PA2 Output Power = 17 dBm, with PA_FINE on a Logarithmic Scale, PAOLDO_VOUT_CON = 15, RF Frequency = Configuration 868 MHz/4.8 kbps; VDD = 3.0 V; TA = 25°C 868 MHz, VDD = 3.0 V, TA = 25°C

0 20 FUNDAMENTAL = 863MHz –10 FUNDAMENTAL = 868MHz +85°C, 3.6V FUNDAMENTAL = 876MHz 0 +85°C, 3.0V –20 +85°C, 2.85V –10 +25°C, 3.6V –30 +25°C, 3.0V –20 +25°C, 2.85V –40 –40°C, 3.6V –50 –30 –40°C, 3.0V –40°C, 2.85V –60 –40 –70 –50 POWER (dBm) POWER (dBm) –80 –60 –90 –70 –100

–110 –80

–120 –90 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH –40 –30 –20 –10 0 10 20 30 40

HARMONIC 14373-061 FREQUENCY OFFSET (kHz) 14373-063 Figure 62. Conductive Harmonic Emission Level, PA2 Output Power = Figure 64. Transmit Spectrum vs. Temperature, and VDD with PA2 Output DD A 17 dBm, RF Frequency = 868 MHz, V = 3.0 V, T = 25°C Power = 17 dBm, Configuration 868 MHz/4.8 kbps, VDD = 3.0 V; TA = 25°C

Rev. A | Page 39 of 55 ADF7030-1 Data Sheet

915 MHZ—RECEIVE 100 100 +85°C, 3.0V –109dBm 90 +85°C, 2.2V 90 –106dBm +25°C, 3.0V –99 dBm +25°C, 2.2V 80 –50dBm 80 –40°C, 3.0V 0dBm –40°C, 2.2V 70 70 TE (%) TE (%) A A 60 60

50 50

40 40

30 30 ACKET ERROR R ACKET ERROR R P P 20 20

10 10

0 0 –106 –105 –104 –103 –102 –101 –100 –99 –98 –97 –96 –50 –40 –30 –20 –10 0 10 20 30 40 50

RECEIVED POWER (dBm) 14373-368 RF FREQUENCY ERROR (kHz) 14373-365 Figure 65. Packet Error Rate vs. RF Frequency Error and RF Input Power; Figure 68. Packet Error Rate vs. Rx Input Power, Temperature, and VDD; Configuration 915 MHz/50 kbps; AFC Enabled; VDD = 3.0 V; TA = 25°C Configuration 915 MHz/150 kbps; FEC Disabled; AFC Enabled

100 100 –100.4dBm +85°C, 3.0V +85°C, 2.2V 90 –97.4dBm 90 –90.4dBm +25°C, 3.0V +25°C, 2.2V –50dBm 80 80 0dBm –40°C, 3.0V –40°C, 2.2V 70 70 TE (%) A

TE (%) 60

A 60 50 50 40 40 30 ACKET ERROR R 30 P ACKET ERROR R

P 20 20 10 10 0 –106 –105 –104 –103 –102 –101 –100 –99 –98 –97 –96 0 RECEIVED POWER (dBm) 14373-369 –45 –30 –15 0 15 30 45

RF FREQUENCY ERROR (kHz) 14373-366 Figure 66. Packet Error Rate vs. RF Frequency Error and RF Input Power; Figure 69. Packet Error Rate vs. Rx Power, Temperature, and VDD; Configuration 915 MHz/150 kbps; AFC Enabled; VDD = 3.0 V; TA = 25°C Configuration 915 MHz/300 kbps; AFC Disabled

100 80 –99dBm 90 –96dBm 70 –86dBm 80 –50dBm 0dBm 60

70 50 TE (%) A 60 40 50 30 40 BLOCKING (dB) 20 30 ACKET ERROR R

P +85°C, 3.0V 10 +85°C, 2.2V 20 +25°C, 3.0V 0 +25°C, 2.2V 10 –40°C, 3.0V –40°C, 2.2V 0 –10 –30 –20 –10 0 10 20 30 –27–24–21–18–15–12 –9 –6 –3 0 3 6 9 12 15 18 21 24 27

INTERFERER FREQUENCY OFFSET (MHz) 14373-370 RF FREQUENCY ERROR (kHz) 14373-367 Figure 67. Packet Error Rate vs. RF Frequency Error and RF Input Power; Figure 70. Receiver Wideband Blocking vs. Interferer Frequency Offset, Configuration 915 MHz/300 kbps; AFC Disabled; VDD = 3.0 V; TA = 25°C Temperature, and VDD; Configuration 915 MHz/150 kbps; Unmodulated Interferer; Desired Signal 3 dB Above the Sensitivity Level of PER = 5%; PER-Based Test

Rev. A | Page 40 of 55 Data Sheet ADF7030-1

3.0 ERROR STANDARD DEVIATION 2.5

2.0

1.5

1.0

0.5 RSSI ERROR (dB) 0

–0.5

–1.0 –105 –95 –85 –75 –65 –55 –45 –35 –25

RECEIVE INPUT POWER (dBm) 14373-371 Figure 71. Packet RSSI Error vs. Rx Input Power with One-Point Calibration at −70 dBm; Configuration 915 MHz/150 kbps; VDD = 3.0 V; TA = 25°C (Error is Based on the Mean RSSI of 100 Packets)

Rev. A | Page 41 of 55 ADF7030-1 Data Sheet

915 MHZ—TRANSMIT –100 19 17 PA_COARSE = 5 15 PA_COARSE = 6 PA_COARSE = 7 –110 13 11 PA_COARSE = 8 PA_COARSE = 9 9 PA_COARSE = 10 –120 7 5 3 1 –130 –1 –3 –5 –140 –7 PHASE NOISE (dBc/Hz) PHASE

A2 OUTPUT POWER (dBm) –9 P –11 –150 –13 –15 –17 –160 –19 1k 10k 100k 1M 10M 100M 2 20 200 14373-176 FREQUENCY OFFSET (Hz) 14373-173 PA_FINE SETTING Figure 72. Phase Noise vs. Frequency Offset, RF Frequency = 915 MHz, PA2 Figure 75. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting Output Power = 17 dBm, VDD = 3.0 V, TA = 25°C with PA_FINE on a Logarithmic Scale, PAOLDO_VOUT_CON = 15, RF Frequency = 915 MHz, VDD = 3.0 V, TA = 25°C

0.5 0 –40°C, 2.85V T = 25°C FUNDAMENTAL = 902.2MHz –10 FUNDAMENTAL = 915MHz 0.4 –40°C, 3.0V VBATx = 3V –40°C, 3.6V FUNDAMENTAL = 927.8MHz +25°C, 2.85V –20 0.3 +25°C, 3.6V +85°C, 2.85V –30 0.2 +85°C, 3.0V +85°C, 3.6V –40 0.1 –50

0 –60

–0.1 –70 POWER (dBm) –80 –0.2 –90 –0.3 CHANGE IN OUTPUT POWER (dB) –100

–0.4 –110

–0.5 –120 –12 –9 –6 –3 0 3 6 9 12 15 18 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH

HARMONIC 14373-177 PA2 OUTPUT POWER (dBm) 14373-174 Figure 73. Change in PA2 Output Power vs. Temperature, and VDD with Figure 76. Conductive Harmonic Emission Level, PA2 Output Power = PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 915 MHz 17 dBm, RF Frequency = 915 MHz, VDD = 3.0 V, TA = 25°C

80 60 –40°C, 2.85V –40°C, 3.0V 50 70 –40°C, 3.6V +25°C, 2.85V 40 +25°C, 3.0V 60 +25°C, 3.6V 30 +85°C, 2.85V +85°C, 3.0V 20

50 +85°C, 3.6V TION (kHz) A 10

CURRENT (mA) 0

40 DEVI Y L Y –10 30 –20 Tx SUPP A 20 –30 FREQUENC VB –40 10 –50

0 –60 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 17 19 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

TRANSMIT SYMBOL (Bits) 14373-178 PA2 OUTPUT POWER (dBm) 14373-175 Figure 74. VBATx Supply Current vs. PA2 Output Power, Temperature, and Figure 77. Transmit Eye Diagram, PA2 Output Power = 17 dBm, VDD with PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 915 MHz Configuration 915 MHz/150 kbps, VDD = 3.0 V, TA = 25°C

Rev. A | Page 42 of 55 Data Sheet ADF7030-1

200 0 +25°C, 2.2V –10 +25°C, 3.0V 150 +25°C, 3.6V –40°C, 2.2V –20 –40°C, 3.0V 100 –40°C, 3.6V –30 +85°C, 2.2V +85°C, 3.0V

TION (Hz) TION 50 +85°C, 3.6V

A –40

0 –50 Y DEVI –60 –50 POWER (dBm) –70 –100 FREQUENC –80 –150 –90

–200 –100 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 –900 –700 –500 –300 –100 100 300 500 700 900 14373-183 TRANSMIT SYMBOL (Bits) 14373-179 FREQUENCY OFFSET (kHz) Figure 78. Transmit Eye Diagram, PA2 Output Power = 17 dBm, Figure 80. Transmit Spectrum vs. Temperature, and VDDPA2 Output Power = Configuration 915 MHz/300 kbps, VDD = 3.0 V, TA = 25°C 17 dBm, Configuration 915 MHz/300 kbps; VDD = 3.0 V; TA = 25°C

0 +25°C, 2.2V +25°C, 3.0V –10 +25°C, 3.6V –40°C, 2.2V –20 –40°C, 3.0V –40°C, 3.6V +85°C, 2.2V –30 +85°C, 3.0V +85°C, 3.6V –40

–50 POWER (dBm) –60

–70

–80

–90 –600 –400 –200 0 200 400 600

FREQEUNCY OFFSET (kHz) 14373-181 Figure 79. Transmit Spectrum, PA2 Output Power = 17 dBm, Configuration: 915 MHz/150 kbps, VDD = 3.0 V, TA = 25°C

Rev. A | Page 43 of 55 ADF7030-1 Data Sheet

THEORY OF OPERATION STATE MACHINE The ADF7030-1 processor handles the sequencing of various The ADF7030-1 operates as a simple state machine as radio circuits and critical timing functions, thereby simplifying illustrated in Figure 81. The host processor can transition the radio operation and easing the burden on the host processor. ADF7030-1 between states by issuing single-byte commands The ADF7030-1 states are described in Table 24. over the SPI interface.

COLD START (BATTERY APPLIED) GPIO WAKEUP/CS LOW

CMD_CFG_DEV (0x85) PHY_OFF CMD_PHY_SLEEP (0x80) CONFIGURING (0x05) PHY_SLEEP (0x01)

CMD_PHY_ON (0x82)

CMD_PHY_OFF (0x81) MONITORING NOTE THAT THE CALIBRATION FIRMWARE (0x0A) MODULE MUST BE DOWNLOADED BEFORE THE CMD_DO_CAL COMMAND IS SUPPORTED

CALIBRATING CMD_DO_CA CMD_CCA (0x86) (0x09) L (0x89)

CMD_CCA (0x86) PHY_ON (0x02) CCA CMD_PHY_ON (0x82) (0x06) BUSY CHANNEL RX_EOF CMD_PHY_RX (0x83)

CMD_PHY_ON (0x82) CLEAR CHANNE CMD_PHY_TX (0x84) TX_EOF

L CMD_PHY_TX (0x84)

CMD_PHY_ON (0x82)

CMD_PHY_TX (0x84) PHY_TX PHY_RX (0x04) CMD_PHY_RX (0x83) (0x03) CMD_PHY_TX (0x84)

RX_TO_TX_AUTO_TURNAROUND CMD_PHY_RX (0x83) KEY TX_TO_RX_AUTO_TURNAROUND TRANSITION TRIGGERED BY A RADIO COMMAND TRANSITION TRIGGERED BY ADF7030-1 META STATE (FOR EXAMPLE, RETURN FROM THIS STATE TO THE PREVIOUS STATE IS TRIGGERED BY THE ADF7030-1) STATES REQUIRING A FIRMWARE MODULE DOWNLOAD RADIO STATE 14373-087 Figure 81. Radio State Machine Diagram

Table 24. Radio States State Description Typical Current PHY_SLEEP In this state, the ADF7030-1 is in sleep. Memory can be optionally retained. 10 nA PHY_OFF In this state, the ADF7030-1 executes using its own internal oscillator clock. The host 3.7 mA configures the radio from this state. PHY_ON In this state, the external reference clock source is enabled. After entering this state, 3.7 mA the ADF7030-1 is ready for the transmission and reception of packets. PHY_RX In this state, the ADF7030-1 can receive and process an incoming packet. 21 mA to 25.4 mA (RF frequency and data rate dependent) PHY_TX In this state, the ADF7030-1 transmits the programmed packet data. 16 mA to 65 mA (RF frequency and Tx power dependent) CCA In this state, the ADF7030-1 performs clear channel assessment. 21 mA to 25.4 mA (frequency and data rate dependent)

Rev. A | Page 44 of 55 Data Sheet ADF7030-1

RADIO TIMING Table 25. Radio Timing Specifications Transition Time Transition Time (μs), Typical at (μs), Typical at Present Command Data Rate = Data Rate = State Next State Command/Bit Initiated By 2.4 kbps 300 kbps Condition PHY_SLEEP PHY_OFF Wakeup from Automatic 101 101 None PHY_SLEEP (RTC timeout event) PHY_SLEEP PHY_OFF Wakeup from Host 101 101 From CS low to PHY_OFF PHY_SLEEP (CS low) PHY_OFF PHY_SLEEP CMD_PHY_SLEEP Host 95 95 From CS low to PHY_SLEEP, memory retention enabled PHY_OFF PHY_ON CMD_PHY_ON Host 206, 188 206, 188 First transition after cold start or wake from PHY_SLEEP, subsequent transitions; 26 MHz TCXO reference PHY_OFF PHY_ON CMD_PHY_ON Host 490, 188 490, 188 First transition after cold start or wake from PHY_SLEEP, subsequent transitions; 26 MHz XTAL reference PHY_OFF PHY_OFF CMD_CFG_DEV Host 36 36 RTC not enabled PHY_ON PHY_SLEEP CMD_PHY_SLEEP Host 30 30 None PHY_ON PHY_OFF CMD_PHY_OFF Host 19 19 None PHY_ON PHY_ON CMD_LFRC_CAL Host 30000 30000 None PHY_ON CCA CMD_CCA Host 230 230 To receiver enabled PHY_ON PHY_TX CMD_PHY_TX Host 245 245 To start of PA ramp PHY_ON PHY_RX CMD_PHY_RX Host 223 225 To receiver enabled CCA PHY_ON CMD_PHY_ON Host 46 46 None CCA PHY_ON Channel busy Automatic 16 16 From receiver disabled CCA PHY_TX Clear channel Automatic 208 203 From receiver disabled to start of PA ramp CCA PHY_TX CMD_PHY_TX Host 239 239 From receiver disabled to start of PA ramp PHY_TX PHY_ON CMD_PHY_ON Host 36 36 From PA ramp finished to PHY_ON PHY_TX PHY_ON TX_EOF Automatic 26 26 From PA ramp finished to PHY_ON PHY_TX PHY_TX CMD_PHY_TX Host 258 231 From start of PA ramp down (at fastest PA ramp rate) to start of PA ramp up on new channel PHY_TX PHY_RX CMD_PHY_RX Host 204 208 From PA ramp finished to receiver enabled PHY_TX PHY_RX Autoturnaround Automatic 204 208 From PA ramp finished to receiver enabled PHY_RX PHY_ON CMD_PHY_ON Host 46 46 None PHY_RX PHY_ON RX_EOF Automatic 32 32 From end of frame IRQ to PHY_ON PHY_RX PHY_RX CMD_PHY_RX Host 216 220 From CS high to receiver enabled on new channel PHY_RX PHY_TX Autoturnaround Automatic 220 220 From end of frame IRQ to start of PA ramp PHY_RX PHY_TX CMD_PHY_TX Host 203 203 From CS high to start of PA ramp

Rev. A | Page 45 of 55 ADF7030-1 Data Sheet

HOST INTERFACE Status Byte Physical Interface The ADF7030-1 reports the status via a status byte. The The ADF7030-1 provides a simple host interface (HIF) that ADF7030-1 returns this byte on the SPI MISO in response consists of a 4-wire standard SPI, a hardware reset pin (RST) to a no operation command (NOP) (0xFF) on the SPI MOSI. and GPIOs. The ADF7030-1 always acts as a slave to the host RECEIVER processor. The host uses the SPI to read and write ADF7030-1 The ADF7030-1 features a fully integrated, highly configurable memory and registers, to issue commands, to track the status of receiver that enables exceptionally high performance reception the state machine, and to wake up the ADF7030-1 from of narrow-band and wideband 2FSK/2GFSK signals. The receiver PHY_SLEEP. is based on a low IF architecture. Figure 82 shows a simplified Host Interface Protocol block diagram of the receiver. The ADF7030-1 implements a very simple protocol over the SPI RF Front End interface. Using this protocol, the host processor can perform a The receive signal is amplified by a differential LNA. The LNA number of operations, as described in the Memory Access section, is followed by a quadrature downconversion mixer that converts the Radio Commands section, and the Status Byte section. the RF signal to the IF frequency. The automatic gain control Memory Access (AGC) circuit automatically controls the gain of the RF front The memory access commands allow the host processor to read end. The fully integrated, fractional-N frequency synthesizer from and write to the internal memory of the ADF7030-1. generates the LO for the mixer. When the ADF7030-1 enters the Typically, the host uses these commands to update the configura- PHY_RX state, the bandwidth of the synthesizer is set automati- tion of the ADF7030-1 and to write packets for transmission or cally to ensure optimum interference rejection performance. to read received packets. IF Processing Radio Commands The quadrature IF signal is band-pass filtered using a high A state machine command triggers a change of radio state as performance, configurable analog filter. The filter is followed by described in Table 26. a programmable gain array (PGA) that is controlled by the AGC circuit. Table 26. State Machine Radio Commands The ADF7030-1 features a narrow-band and wideband IF Command Description processing path. In the narrow-band path, the IF signal is CMD_PHY_SLEEP Performs a transition of the device into the digitized by a high performance, high dynamic range analog-to- PHY_SLEEP state digital converter (ADC). RSSI, decimation, and offset CMD_PHY_OFF Performs a transition of the device into the correction are performed before the digitized IF is filtered using PHY_OFF state a configurable narrow-band digital channel filter. CMD_PHY_ON Performs a transition of the device into the PHY_ON state In the wideband path, a limiter converts the IF signal to digital CMD_PHY_RX Performs a transition of the device into the levels for the demodulator. The limiter also provides offset PHY_RX state correction and RSSI, which is digitized using the ADC. CMD_PHY_TX Performs a transition of the device into the PHY_TX state CMD_CFG_DEV Configures the ADF7030-1 based on the radio profile

CMD_CCA Performs a transition of the device into the CCA state CMD_DO_CAL Executes selected calibration routines; requires the OffLineCalibrations.cfg firmware module CMD_MON Measures and reports the ADF7030-1 temperature CMD_LFRC_CAL Performs a frequency calibration of the internal 26kHz RC oscillator; requires the OffLineCalibrations.cfg firmware module

Rev. A | Page 46 of 55 Data Sheet ADF7030-1

AGC NARROW-BAND Rx PATH

I ADC QEC LNAIN1 OCL LNAIN2 Q RSSI ADC LNA

PGA 2FSK/2GFSK CDR SERDES DEMOD Rx DATA RF TO Cortex-M0 AFC PROCESSOR SYNTHESIZER LIMITER, RSSI OCL

WIDEBAND Rx PATH 14373-088 Figure 82. Receiver Block Diagram Table 27 and Table 28 list the supported channel bandwidths and IF frequencies. The ADF7030-1 graphic user interface (GUI) Table 28. Wideband Rx Path Channel Bandwidths and IFs automatically chooses the correct receive path, channel bandwidth, Channel Bandwidth (kHz) IF (kHz) and IF frequency based on the data rate and modulation settings. 77.38 103.17 82.63 110.17 Table 27. Narrow-Band Rx Path Channel Bandwidths and IFs 101.57 135.42 Channel Bandwidth (kHz) IF (kHz) 121.88 162.50 2.6 81.25 135.42 180.55 3.0 81.25 147.73 196.97 3.2 81.25 162.50 216.67 3.4 81.25 180.56 240.74 3.7 81.25 203.12 270.83 3.9 81.25 221.59 295.45 4.2 81.25 243.75 325.00 4.4 81.25 270.83 361.11 4.7 81.25 353.00 361.11 5.1 81.25 395.00 406.25 5.4 81.25 406.25 433.33 5.8 81.25 AGC 6.2 81.25 6.6 81.25 AGC is enabled by default and keeps the receiver gain at the 7.0 81.25 correct level by selecting the LNA, mixer, and filter gain settings 7.5 81.25 based on the measured RSSI level. 8.1 81.25 AFC 8.5 81.25 The ADF7030-1 features an internal real-time automatic 8.7 81.25 frequency control loop. In receive mode, the control loop 9.1 81.25 automatically monitors the frequency error during the packet 9.7 81.25 preamble sequence and adjusts the receiver synthesizer local 10.4 81.25 oscillator. AFC is supported without the need for any additional 10.6 81.25 preamble bits in the received packet. 11.1 81.25 Baseband Processing 11.7 81.25 11.9 81.25 The demodulator is based on a digital frequency correlator 12.7 81.25 that performs filtering and frequency discrimination of the 13.5 81.25 2FSK/2GFSK spectrum. Following the demodulator is an 14.4 81.25 oversampled digital clock and data recovery (CDR) phase- 15.4 81.25 locked loop (PLL) that resynchronizes the received bit stream to 16.4 81.25 a local clock in all modulation modes. A serializer/deserializer 17.6 81.25 (SERDES) block processes the received bit stream, carries out 18.7 81.25 pattern matching, and produces the byte sized data for the 20.0 81.25 ARM Cortex-M0 processor.

Rev. A | Page 47 of 55 ADF7030-1 Data Sheet

The ARM Cortex-M0 processor performs all of the byte level Power Amplifiers packet processing and packet management. The ADF7030-1 has two integrated power amplifiers. PA1 and Received Signal Strength Indicator (RSSI) PA2 are designed for optimum power consumption performance The ADF7030-1 supports accurate measurement of the received at 13 dBm and 17 dBm, respectively. The PAs cannot be operated signal strength. To achieve the calibrated absolute accuracy simultaneously. The user selects the appropriate PA for their specification, a one-point factory calibration is required (see the specific system. The power amplifiers are implemented as Class F Radio System Calibration section). The ADF7030-1 measures type amplifiers. the RSSI during packet reception and the value is stored in a For systems where very fine power control is required, a PA register for access by the host processor. The RSSI measurement microsetting can be used to achieve 0.1 dB of resolution across is also used during CCA, where the RSSI measurement is evalu- the power range. To reduce spectral splatter when the PA is ated against a user set threshold. The RSSI is reported in dBm. turning on and off, a programmable PA ramp is provided. TRANSMITTER Transmit Modulation Schemes The ADF7030-1 transmitter supports 2FSK/2GFSK, 4FSK/4GFSK, The ADF7030-1 supports 2FSK/2GFSK and 4FSK/4GFSK and OOK modulation. It comprises a high performance PLL modulation in transmit mode. In 2FSK/2GFSK mode, a binary synthesizer and power efficient dual PAs. A block diagram of the zero value generates a frequency deviation tone, –fDEV. A binary ADF7030-1 transmitter architecture is shown in Figure 83. All one generates a +fDEV tone. In 4FSK/4GFSK, the symbol mapping blocks are fully integrated. is configurable. Synthesizer and VCO OOK modulation is also supported in transmit mode at a data An integrated, low noise PLL synthesizer and VCO generate rate of 16.384 kbps. both the transmit signal and the receiver LO signal. Transmit Filtering The synthesizer loop filter has a programmable bandwidth. The ADF7030-1 supports Gaussian filtering in both 2FSK and Upon entering the PHY_RX state, the ADF7030-1 sets a narrow 4FSK mode. Gaussian filtering reduces the occupied bandwidth bandwidth to ensure optimum receiver rejection. In the PHY_TX of the signal by digitally prefiltering the transmit data. The BT state, the bandwidth is chosen to ensure optimum modulation factors are configurable with the following options: 0.5, 0.4, quality. 0.35, or 0.3. Reducing BT increases the roll-off factor of the filter resulting in a narrower signal bandwidth. As BT is reduced, A high speed, fully automatic calibration scheme ensures that intersymbol interference is introduced, which affects the the VCO performance is maintained over temperature, supply receiver sensitivity performance. voltage, and process variations. The calibration is automatically performed when the CMD_PHY_RX or CMD_PHY_TX command is issued.

OOK PA RAMP

RF PAOUT2 FREQ PA2

26MHz REFERENCE PFD CHARGE VCO DIVIDER (TCXO OR XTAL) PUMP PAOUT1 LOOP PA1 FILTER

N Rx LO DIVIDER

Tx DATA BIT GAUSSIAN Σ-Δ (FROM Cortex-M0 MAPPER FILTER MODULATOR PROCESSOR)

FSK AFC FREQUECY DEVIATION 14373-089 Figure 83. Transmitter Block Diagram

Rev. A | Page 48 of 55 Data Sheet ADF7030-1

CALIBRATION the calibration uses internally generated RF signals to perform Table 29 provides an overview of the calibrations associated certain aspects of the receiver calibration. If an interferer signal with the ADF7030-1 and when to run calibrations. is present on the RF input of the ADF7030-1 during calibration, this signal can degrade the calibration performance. The conse- Radio System Calibration quence of a degraded calibration is a reduction in the image To ensure that the ADF7030-1 radio performance meets the rejection performance of the receiver. data sheet specifications, it is necessary to perform a one-time If the application uses an external switch, the switch can be used radio system calibration at 25°C ± 10°C. to provide extra isolation between the antenna and the RF input The radio system calibration routine is provided as a firmware of the ADF7030-1 during calibration. module, OffLineCalibrations.cfg, that the host processor must 26 kHz RC Oscillator Calibration download to the ADF7030-1 memory. The firmware module is available as part of the ADF7030-1 design package. The calibration To ensure that the 26 kHz RC oscillator meets the calibrated is fully autonomous when initiated by the CMD_DO_CAL frequency accuracy specification, it is necessary to perform a command. calibration. During calibration, the OffLineCalibrations.cfg firmware module must be downloaded to the ADF7030-1. The The radio system calibration firmware module can be downloaded calibration is fully autonomous when initiated by the CMD_LFRC_ to the ADF7030-1 and run as part of a factory calibration proce- CAL command. Refer to the ADF7030-1 Software Reference dure and the calibration data stored on the host processor as part of Manual for further details. the configuration settings for the ADF7030-1. Calibration data is RSSI Offset Calibration maintained in PHY_SLEEP if memory retention is enabled. If the memory is not retained, the host processor must replay the To ensure that the ADF7030-1 RSSI performance meets the calibration data to the ADF7030-1. Refer to the ADF7030-1 calibrated RSSI data sheet specifications, it is necessary to perform Software Reference Manual for further details on downloading a measurement of the ADF7030-1 RSSI measurement offset. and using firmware modules with the ADF7030-1. The offset can be measured as part of a factory calibration pro- In the Field Radio System Calibration cedure where an RF signal source applies a signal to the receiver input while the ADF7030-1 is in the continuous CCA state. The The only receiver performance metric that benefits appreciably offset between the applied signal power and the ADF7030-1 RSSI from a recalibration over temperature, is the image rejection. In result is stored on the host processor as part of the configuration applications where image rejection performance is critical over settings for the ADF7030-1. The ADF7030-1 has allocated temperature, it may be necessary to perform a recalibration as registers for the RSSI offset, and the ADF7030-1 automatically the temperature changes. applies these offsets to the RSSI measurement result returned If the application requires the calibration to be performed in the over the SPI. Refer to the ADF7030-1 Software Reference field (in addition to the one-time factory calibration), it is Manual for further details on the RSSI offset calibration important to consider interferer signals during calibration, because procedure and the RSSI offset registers. Table 29. ADF7030-1 Calibrations Typical Radio Calibration Calibration Description When to Run this Calibration Firmware Module Required Command Time (ms) Radio System Calibration of A one-time calibration is required to The OffLineCalibrations.cfg CMD_DO_CAL 660 the radio meet the data sheet specifications. This firmware module must be system calibration can be performed as part of a downloaded to the ADF7030-1. factory calibration of the end product. 26 kHz RC Frequency A frequency calibration of the 26 kHz RC The OffLineCalibrations.cfg CMD_LFRC_CAL 30 Oscillator calibration of oscillator is required to meet the typical firmware module must be the internal frequency accuracy specification. downloaded to the ADF7030-1. 26 kHz RC Depending on the frequency accuracy oscillator requirements of the application, it may also be necessary to calibrate as the temperature changes. Refer to Table 17 for specifications. RSSI Offset A single point, A single-point, one-time, RSSI offset None required. Not applicable Not one-time, calibration is required to meet the RSSI applicable offset accuracy specification of Table 3. This calibration of calibration can be performed as part of a the RSSI factory calibration of the end product.

Rev. A | Page 49 of 55 ADF7030-1 Data Sheet

PACKET HANDLING Transmitting and Receiving packets The ADF7030-1 includes comprehensive transmit and receive The ADF7030-1 can be programmed to transmit and receive packet management capabilities and can be configured for use variable and fixed length payloads. The packet data to be with a wide variety of packet-based radio protocols. transmitted must be written by the host into the ADF7030-1 IEEE 802.15.4g Packet Mode internal memory. 511 bytes of dedicated RAM are available to store, transmit, and receive packets. For payload lengths greater The ADF7030-1 supports the multirate frequency shift keying than 511 bytes, the ADF7030-1 provides a rolling buffer mode. (MR-FSK) PHY 802.15.4g specified packet format in the IEEE 802.15.4g-2012 standard with FEC, whitening, and interleaving To transmit or receive a packet, the host processor must first at data rates of up to 150 kbps. configure the ADF7030-1. Then, the host processor issues the commands to place the ADF7030-1 into the PHY_RX state or Generic Packet Mode the PHY_TX state. After either state is entered, the ADF7030-1 The ADF7030-1 supports a wide variety of packet formats via automatically starts transmitting or receiving a packet. its fully flexible generic packet format. In generic packet In transmit mode, a preamble, sync word, and CRC can be added transmit mode, the ADF7030-1 can be configured to add the by the ADF7030-1 to the payload data stored in the RAM. In preamble, sync word, and cyclic redundancy check (CRC) to the receive mode, the ADF7030-1 can qualify received packets payload data stored in the packet memory. The number of based on preamble detection, sync word detection, or CRC preamble bits and sync bits is programmable, and an optional validation. When the ADF7030-1 receives a valid packet, the length field can be added to allow packet length decoding at the received payload data is loaded to packet memory. receiver. The CRC polynomial and length are fully programmable in generic packet mode. The host can track the progress of the transmission or reception of a packet by monitoring the interrupt signals coming from the ADF7030-1. There are two independent logical interrupts from the ADF7030-1, and events can be configured to trigger one or both of these logical interrupts.

Rev. A | Page 50 of 55 Data Sheet ADF7030-1

APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT guide on application circuits, external hardware requirements, A typical application circuit is shown in Figure 84. Refer to the and RF matching for the ADF7030-1. ADF7030-1 Hardware Reference Manual for a comprehensive

26MHz TCXO 220nF OPTIONAL 220nF 220nF WAKE-UP CRYSTAL 1.2nF 32.768kHz P T6 A CLF AL ALN DNC DNC T T GPIO7 100nF VB CREG5 100kΩ CREG7 CREG6 HFX HFX RST DNC 100kΩ 220nF VBAT1 GPIO6 GPIO CREG1 CS CS 100nF VBAT2 SCLK SCLK 220nF HOST CREG2 ADF7030-1 MISO MISO LNAIN1 TOP VIEW MOSI MOSI LNAIN2 (Not to Scale) VBAT5

220nF DNC VBAT4 INT1 MICROPROCESSOR CREG3 GPIO5 100nF INT2 DNC GPIO4 T3 A

Rx MATCH AOUT1 AOUT2 DNC P P VB CREG4 GPIO0 GPIO1 GPIO2 GPIO3 DNC

HARMONIC 100nF 220nF OPTIONAL FILTER GPIO CONNECTION PA2 MATCH FROM ADF7030-1 100nF

14373-090 Figure 84. Typical Application Circuit with External Switch and TCXO Reference

Rev. A | Page 51 of 55 ADF7030-1 Data Sheet

SILICON ANOMALY This anomaly list describes the known bugs, anomalies, and workarounds for the ADF7030-1. Analog Devices, Inc., is committed, through future silicon revisions and/or firmware module revisions, to continuously improve functionality. Analog Devices tries to ensure that these future revisions of the ADF7030-1 silicon or firmware modules remain compatible with your present software/systems by implementing the recommended workarounds outlined here. The silicon revision information can be electronically determined by reading the PART_ID and ROM_ID fields from the ADF7030-1 memory locations described in Table 30.

Table 30. Silicon Revision ID IF Field Length (Bytes) Memory Address PART_ID 2 0x00007FF6 ROM_ID 1 0x00007FF9

ADF7030-1 FUNCTIONALITY ISSUES Silicon Revision ID Chip Marking Silicon Status No. of Reported Anomalies PART_ID = 0x0602, ROM_ID = 0x02 ADF7030-1BCPZN or ADF7030-1BSTZN Release 2

FUNCTIONALITY ISSUES

Table 31. Short Transmit Pulse Preceding Packet preamble on OOK Transmit [er001] Background In OOK transmit, a preamble sequence with the length controlled by PREAMBLE_LEN in the GENERIC_PKT_FRAME_CFG0 register is transmitted at the start of a packet. Issue The first OOK transmit packet after a reset event or cold start has the correct preamble sequence. Subsequent OOK transmit packets prepend a short transmit pulse with a duration of less than one bit, before the preamble sequence. The output power of the pulse is at the configured output power. Workaround None. Related None. Issues

Table 32. CCA After Aborting PHY_TX During Packet Transmission for Data Rates < 3.064 kbps [er002] Background The host processor can abort a transmission by issuing any radio command while the ADF7030-1 is in the PHY_TX state. Issue For data rates < 3.064 kbps, the first CCA operation is inoperative after aborting a transmission. Workaround After aborting a transmission, enter the CCA state twice. On the first CCA entry, CCA is inoperative. On the second and subsequent entries to the CCA state, CCA is fully operational. Related None. Issues

Section 1. ADF7030-1 Functionality Issues Reference Number Description Status er001 Short transmit pulse preceding packet preamble on OOK transmit Open er002 CCA after aborting PHY_TX during packet transmission for data rates < 3.064 kbps Open

This completes the Silicon Anomaly section.

Rev. A | Page 52 of 55 Data Sheet ADF7030-1

DEVELOPMENT SUPPORT DESIGN PACKAGE EVALUATION KITS The ADF7030-1 design resource package is a complete Evaluation and development kits are available that include the documentation and resource package for the ADF7030-1. It is ADF7030-1 radio daughter boards. The ADF7030-1 EZ-KIT® is recommended to download this package as a starting point for an evaluation and development system for the ADF7030-1 high evaluation and development from the ADF7030-1 product page. It performance, sub GHz, RF transceiver, and includes four contains manuals, application notes, hardware information, and models. These kits are listed in Table 33. firmware modules. Table 33. ADF7030-1 EZ-KIT Models REFERENCE MANUALS Model Frequency (MHz) ADF7030-1 Software Reference Manual (UG-1002) ADF70301-915EZKIT 902 to 928 The ADF7030-1 Software Reference Manual is the detailed ADF70301-868EZKIT 863 to 876 programming guide for the device. The ADF7030-1 hardware ADF70301-433EZKIT 433 to 434 reference manual provides a description of the ADF7030-1 ADF70301-169EZKIT 169 hardware features and application circuit requirements. A selection of individual daughter boards is also available ADF7030-1 Hardware Reference Manual (UG-957) covering various frequency bands and matching topologies. The ADF7030-1 Hardware Reference Manual provides a EVALUATION SOFTWARE description of the ADF7030-1 radio functionality, hardware The ADF7030-1 design center is a graphical user interface features, and application circuit requirements. It is intended as a (GUI) that can be used for configuring the ADF7030-1, resource for a hardware engineer designing a printed circuit evaluating transmit and receive operation, and transmitting and board (PCB) that includes the ADF7030-1. receiving packets. This ADF7030-1 design center allows the user to rapidly prototype different configurations with the ADF7030-1 and simplifies the migration to host code development.

Rev. A | Page 53 of 55 ADF7030-1 Data Sheet

OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 6.10 0.30 6.00 SQ 0.25 PIN 1 5.90 0.18 INDICATOR PIN 1 AREA IN D IC ATO R AR E A OP T IO N S SEE DETAIL A) 31 40 ( 30 1

0.50 BSC 4.60 EXPOSED 4.50 SQ PAD 4.40

21 10 0.45 20 11 TOP VIEW BOTTOM VIEW 0.20 MIN 0.40 0.35 0.80 0.75 SIDE VIEW FOR PROPER CONNECTION OF 0.05 MAX 0.70 THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS SEATING 0.08 SECTION OF THIS DATA SHEET. PLANE 0.20 REF PKG-004524 COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5 10-08-2018-B Figure 85. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm × 6 mm Body and 0.75 mm Package Height (CP-40-17) Dimensions shown in millimeters

SIDE VIEW 9.20 1.60 9.00 SQ 0.75 MAX 0.60 8.80 0.45 TOP VIEW

48 37 1.00 REF 1 36 SEATING PLANE 7.20 1.45 0.20 7.00 SQ 1.40 0.15 6.80 1.35 0.09

0.15 12 25 7° 13 24 0.10 0° 0.05 0.08 MAX 0.50 0.27 COPLANARITY VIEW A BSC 0.22 VIEW A 0.17

ROTATED 90° CCW A 01-17-2018- PKG-005430 COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 86. 48-Lead Low Profile Quad Flat Package [LQFP] 7 mm × 7 mm Body (ST-48) Dimensions shown in millimeters

Rev. A | Page 54 of 55 Data Sheet ADF7030-1

ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADF7030-1BCPZN −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-17 ADF7030-1BCPZN-RL −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-17 ADF7030-1BSTZN −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 ADF7030-1BSTZN-RL −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 EV-ADF70301-169BZ Evaluation Daughter Board (169 MHz, Separate PA and LNA Match, 26 MHz XTAL) EV-ADF70301-433AZ Evaluation Daughter Board (433 MHz, Separate PA and LNA Match, 26 MHz XTAL) EV-ADF70301-460BZ Evaluation Daughter Board (450 MHz to 470MHz, Separate PA and LNA match, 26 MHz TCXO) EV-ADF70301-868BZ Evaluation Daughter Board (863 MHz to 876 MHz, Separate PA and LNA match, 26 MHz TCXO) EV-ADF70301-915AZ Evaluation Daughter Board (902 MHz to 928 MHz, Separate PA and LNA match, 26 MHz XTAL) ADF70301-169EZKIT Evaluation and Development Kit (169 MHz) ADF70301-433EZKIT Evaluation and Development Kit (433 MHz to 434 MHz) ADF70301-868EZKIT Evaluation and Development Kit (863 MHz to 876 MHz) ADF70301-915EZKIT Evaluation and Development Kit (902 MHz to 928 MHz)

1 Z = RoHS Compliant Part.

Rev. A | Page 55 of 55