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QSFP28 Optical Transceiver –100 Gigabit Ethernet for up to 10 Km Reach LQ2 Series

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QSFP28 Optical Transceiver –100 Gigabit Ethernet for up to 10 Km Reach LQ2 Series QSFP28 Optical Transceiver –100 Gigabit Ethernet for up to 10 km Reach LQ2 Series www.lumentum.com Data Sheet QSFP28 Optical Transceiver –100 Gigabit Ethernet for up to 10 km Reach The Lumentum 100G QSFP28 LR4 Optical Transceiver is a full duplex, photonic-integrated optical transceiver that provides a high-speed link at aggregated data rate of either 103.125 Gbps or 111.81 Gbps over up to 10 km of SMF28. The module complies with IEEE 802.3-2015 Clause 88 and 83E standard and ITU-T G.959.1-2016-04. The transceiver integrates the receive and transmit path on one Key Features module. On the transmit side, four lanes of serial data are • Supports 100GBASE-LR4 for line rate of 103.125 Gbps and recovered by a programmable continuous time linear equalizer OTU4 for line rate of 111.81 Gbps (CTLE), retimed and passed to four laser drivers, which control • Integrated LAN WDM TOSA/ROSA for up to 10 km reach over four lasers with center wavelengths of 1296 nm, 1300 nm, 1305 SMF28 nm and 1309 nm. The optical signals are multiplexed to a • Duplex single mode LC optical receptacle single-mode fiber through an industry standard LC connector. On the receive side, four lanes of optical data streams are optically • Operating temperature range from 0°C to 70°C de-multiplexed by an integrated optical demultiplexer. Each data • Low power dissipation < 4 W stream is recovered by a PIN photodetector transimpedance • RoHS 6/6 compliant amplifier, retimed and passed to a CAUI-4 compliant output • Single 3.3 V power supply driver. • External reference clock is not required This module features a hot-pluggable electrical interface, low • Compliant with CEI-28G-VSR/CAUI-4 electrical interface power consumption and 2-wire I2C management interface. • Digital diagnostic monitoring support • Tx and Rx re-timers • Hot pluggable 38 pin electrical interface • 2-wire I2C management interface • Blue handle Applications • Local area network (LAN) • Wide area network (WAN) • Ethernet switches and router applications Compliance • IEEE 802.3-2015 Clause 88 standard • IEEE 802.3-2015 Clause 83E standard • ITU-T G.959.1-2016-04 standard • OIF-CEI-03.1 CEI-28G-VSR standard • SFF-8661 Rev 2.3 QSFP28 module mechanical • SFF-8679 Rev 1.7 QSFP28 Base Electrical • SFF-8636 Rev 2.7 Common Management Interface • Class 1 laser safety • Tested in accordance with Telcordia GR-468 www.lumentum.com 2 QSFP28 Optical Transceiver –100 Gigabit Ethernet for up to 10 km Reach Section 1 Functional Description Receiver The receiver takes incoming combined four lanes of DC balanced The 100G QFP28 LR4 optical transceiver is a fully duplex device LAN-WDM NRZ optical data from line rate of 25.78 Gbps to 27.95 Gbps through an industry standard LC optical connector. The four with both transmit and receive functions contained in a single incoming wavelengths are separated by an optical demultiplexer module. The optical signals are multiplexed to a single-mode fiber into four separated channels. Each output is coupled to a PIN through an industry standard LC connector. photodetector. The electrical currents from each PIN photodetector are converted to a voltage in a high-gain The module provides a high speed link at an aggregated signaling transimpedance amplifier. The electrical output is recovered and rate of 103.125 Gbps or 111.81 Gbps. It is compliant with IEEE retimed by the CDR chip. The four lanes of reshaped electrical 802.3-2015 Clause 88 100GBASE-LR4 and ITU-T G.959.1-2016- signals are output on the RDxp and RDxn pins as a 100 Ω 04 OTL4.4 (OTU4 striped across four physical lanes) 4I1-9D1F for differential CEI signals. up to 10 km reach over SMF28 fiber. The two-wire management interface complies with SFF-8636. The transceiver mechanical Low-Speed Signaling design complies with SFF-8661 and the base electrical design The Lumentum 100G QSFP28 LR4 Optical Transceiver has several complies with SFF-8679. A block diagram is shown in Figure 1. low-speed interface connections including a 2-wire serial interface (SCL and SDA). These connections include; Low Power Mode (LPMode), Module Select (ModSelL), Interrupt (IntL), Module Vcc_Tx Vcc_Rx Power Present (ModPrsL) and Reset (ResetL) as shown in Figure 1. Vcc1 Supplies TIA D ModSelL: The ModSelL is an input pin. When held low by the CDR/ uple 38-pin Limiting host, the module responds to 2-wire serial communication Amplier TIA Optical DeMux x commands. The ModSelL allows the use of multiple QSFP28 TIA LC Connector 2-Wire SCL, SDA modules on a single 2-wire interface bus. When the ModSelL is Connector TIA ModselL “High”, the module does not respond to or acknowledge any IntL Monitoring & 2-wire interface communication from the host. ModPresL Control ResetL LDD LPMode In order to avoid conflicts, the host system shall not attempt LDD Optical 2-wire interface communications within the ModSelL de-assert CDR/ Mux LDD Equalizer time after any QSFP28 modules are deselected. Similarly the host LDD must wait at least for the period of the ModSelL assert time before communicating with the newly selected module. The assertion and de-assertion periods of different modules may Figure 1 Functional block diagram overlap as long as the above timing requirements are met. Transmitter ResetL: The ResetL pin is pulled up to Vcc inside the QSFP28 The transmitter path converts four lanes of serial NRZ electrical module. A low level on the ResetL pin for longer than the data from line rate of 25.78 Gbps to 27.95Gbps to a standard minimum pulse length (t_Reset_init) initiates a complete module compliant optical signal. Each signal path, accepts a 100 Ω reset, returning all user module settings to their default state. differential 100 mV peak-to-peak to 900 mV peak-to-peak Module Reset Assert Time (t_init) starts upon the rising edge electrical signal on TDxn and TDxp pins. after the low level on the ResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits Inside the module, each differential pair of electric signals is input until the module indicates a completion of the reset interrupt. to a CDR (clock-data recovery) chip. The recovered and retimed The module indicates this by posting an IntL signal with the signals are then passed to a laser driver which transforms the Data_Not_Ready bit negated. Note that on power up (including small swing voltage to an output modulation that drives a cooled hot insertion) the module will post this completion of reset EML laser. The laser drivers control four EMLs with center interrupt without requiring a reset. wavelengths of 1296 nm, 1300 nm, 1305 nm and 1309 nm, respectively. The control of transmitted laser power and LPMode: The LPMode pin is pulled up to Vcc inside the QSFP28 modulation swing over temperature and voltage variations is module. This function is affected by the LPMode pin and the combination of the Power_over-ride and Power_set software provided on each laser. The optical signals from the four lasers control bits (Address A0h, byte 93, bits 0,1). are multiplexed together optically. The combined optical signals are coupled to single-mode optical fiber through an industry The module has three modes: a low power mode, a limit power standard LC optical connector. The optical signals are engineered mode and a high power mode. The high power mode operates in to meet the 100 Gigabit Ethernet or OTU4 specifications. one of the four power classes. www.lumentum.com 3 QSFP28 Optical Transceiver –100 Gigabit Ethernet for up to 10 km Reach When the module is in a low power mode it has a maximum power Application Schematics consumption of 1.5W. The maximum power consumption of a limit An example application schematic (reference SFF 8679) showing power mode is 3.5W. This protects hosts that are not capable of connections from a host IC and host power supply to the Lumentum cooling higher power modules, should such modules be accidentally 100G QSFP28 LR4 optical transceiver is shown in Figure 2. inserted. QSFP28 LR4 modules are hot pluggable and active connections are The module’s 2-wire serial interface and all laser safety functions are powered by individual power connection at 3.3 V nominal voltage. fully operational in this low power mode. The module still supports Multiple modules can share a single 3.3 V power supply with the completion of reset interrupt in this low power mode. individual filtering. To limit wide band noise power, the host system and module shall each meet a maximum of 2% peak-to-peak noise The Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate when measured with a 1 MHz low pass filter. In addition, the host that our module has power consumption greater than 1.5W. When system and the module shall each meet a maximum of 3% peak-to- the module is in low power mode, the module will reduce its power peak noise when measured with a filter from 1 MHz - 10 MHz. consumption to less than 1.5W while still maintaining the functionality above. However, the Tx or Rx may not be operational in A module will meet all electrical requirements and remain fully this state. operational in the presence of noise on the 3.3V power supply. Power supply filtering components should be placed as close to the The module will be in low power mode if the LPMode pin is in the Vcc pins of the host connector as possible for optimal performance. high state, or if the Power_over-ride bit (Page 00h, byte 93 bit 0)is in Note: Decoupling Capacitor values vary depending on the the high state and the Power_set bit (Page 00h, byte 93 bit 1) is also application.
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