electronics

Article ESD Design and Analysis by Drain Electrode-Embedded Horizontal Schottky Elements for HV nLDMOSs

Shi-Zhe Hong and Shen-Li Chen *

Department of Electronic Engineering, National United University, Miaoli City 36063, Taiwan; [email protected] * Correspondence: [email protected]; Tel.: +886-37-382525

Abstract: (ESD) events can severely damage miniature components. Therefore, ESD protection is critical in integrated circuits. In this study, drain-electrode-embedded horizontal Schottky contact modulation and Schottky length reduction modulation were performed on a high-voltage 60-V n-channel laterally diffused metal-oxide– (nLDMOS) element. The effect of the on-voltage characteristics of cascade Schottky on ESD protection was investigated. By using a transmission-line pulse tester, the trigger voltage, holding voltage,

and secondary breakdown current (It2) of the nLDMOS element were determined using the I–V characteristic. As the N+ area was gradually replaced by the parasitic Schottky area at the drain electrode, an equivalent circuit of series Schottky diodes formed, which increased the on-resistance.

The larger the Schottky area was the higher the It2 value was. This characteristic can considerably improve the ESD immunity of nLDMOS components (highest improvement of 104%). This is a good strategy for improving ESD reliability without increasing the production steps and fabrication cost.

Keywords: electrostatic discharge (ESD); holding voltage (Vh); lateral diffusion MOS (LDMOS); schottky diode; secondary breakdown current (It2); transmission-line pulse system (TLP system)

 

Citation: Hong, S.-Z.; Chen, S.-L. 1. Introduction ESD Design and Analysis by Drain Although the efficiency and speed of components have improved with the evolution Electrode-Embedded Horizontal of semiconductor processes, component integration and cost considerations have become a Schottky Elements for HV nLDMOSs. Electronics 2021, 10, 178. https:// concern. Generally, compact components are desired. Although the economic benefits of doi.org/10.3390/electronics10020178 advanced components have increased, reliability uncertainties have also increased. Even a small defect during manufacturing can cause considerable losses to the manufacturer. Received: 7 December 2020 Electrostatic discharge (ESD) events [1–10] for integrated circuits (ICs) are the major hazard Accepted: 13 January 2021 to reliability. Published: 15 January 2021 Common discrete ESD protection devices are laterally diffused metal-oxide– semiconductor (LDMOSs), gas discharge tube (GDTs), spark gap (SPGs), tran- Publisher’s Note: MDPI stays neu- sient voltage suppressor (TVSs), and voltage-dependent (VDRs). However, in tral with regard to jurisdictional clai- this paper, a power management high-voltage manufactured by a very- ms in published maps and institutio- large-scale interaction bipolar-CMOS-DMOS (VLSI BCD) process uses LDMOS devices nal affiliations. to form HV circuits and discusses how to protect their ESD reliability. This LDMOS ESD protection device can be used to protect the I/O port of the circuit. Therefore, LDMOSs have been effectively used in integrated circuits for power electronics, Internet of things (IoT) applications, vehicle electronics, and ESD protection components [11–25], and their Copyright: © 2021 by the authors. Li- censee MDPI, Basel, Switzerland. importance is gradually increasing. A high-voltage LDMOS has a longer drift region and This article is an open access article shallow trench isolation (STI) region. Then, this device has a larger depletion region and distributed under the terms and con- higher on-resistance (Ron) allowing it to operate under high voltage. However, the operat- ditions of the Creative Commons At- ing voltage of LDMOSs is considerably high. Good reliability and the ability to withstand tribution (CC BY) license (https:// large currents are critical in high-current devices. Therefore, the effective discharge of large creativecommons.org/licenses/by/ currents is essential. However, the of these high-voltage LDMOS devices 4.0/). is often concentrated between the drain and STI. Therefore, the LDMOS has lower ESD

Electronics 2021, 10, 178. https://doi.org/10.3390/electronics10020178 https://www.mdpi.com/journal/electronics Electronics 2021, 10, x FOR PEER REVIEW 2 of 16

ity and the ability to withstand large currents are critical in high-current devices. There- fore, the effective discharge of large currents is essential. However, the current density Electronics 2021, 10, 178 of these high-voltage LDMOS devices is often concentrated between the drain and2 STI. of 15 Therefore, the LDMOS has lower ESD protection capabilities and at the same time is prone to disadvantages such as latch-up effects [26–32]. Schottky diodes [33–39] typical- lyprotection include capabilities metals and and semiconductor at the same junctions.time is prone In this to disadvantages work, we combined such as latch-up the low turneffects-on [ 26 voltage–32]. Schottky characteristic diodes of [33 Schottk–39] typicallyy diodes include with metals nLDMOSs and semiconductor to form a parasitic junc- horizontaltions. In this Schottky work, we region combined at the thedrain low electrode turn-on voltageof the nLDMOS characteristic element. of Schottky Such compo- diodes nentswith nLDMOSsexhibit superior to form reliability a parasitic and horizontal can withstand Schottky high region ESD atcurrents. the drain electrode of the nLDMOS element. Such components exhibit superior reliability and can withstand high 2.ESD Sample currents. Designs of the HV nLDMOS 2.1. HV nLDMOS Reference Device 2. Sample Designs of the HV nLDMOS High-voltage (HV) laterally diffused metal-oxide–semiconductor transistors 2.1. HV nLDMOS Reference Device (LDMOS) are often used as ESD protection components at the input/output electrodes of circuitsHigh-voltage to prevent (HV)the circuit laterally latch diffused-up effect, metal-oxide–semiconductor which causes the element transistors to burn (LDMOS) out. We designedare often usedLDMOSs as ESD with protection a protective components ring. Typically, at the input/outputto withstand electrodeshigh voltage, of circuitsa long driftto prevent region the is necessary circuit latch-up and various effect, whichconcentration causes theregions element of N to-type burn and out. P- Wetype designed arLDMOSse used to with form a protectivea concentration ring. Typically,gradient. Furthermore, to withstand highthe element voltage, has a long a high drift drift region re- gionis necessary resistance. and Various various concentration concentration regions gradients of N-type are used and to P-type disperse doping strong are usedelectric to fieldsform aand concentration extend the gradient.length of Furthermore, the depletion the region element to increase has a high the drift breakdown region resistance. voltage. FigureVarious 1a concentration displays the gradients cross-sectional are used view to disperse of the strong parasitic electric equivalent fields and circuit extend of the LDMOSlength of component, the depletion Figure region 1b to displays increase the the 3 breakdown-D structure voltage. view, and Figure Figure1a displays 1c displays the thecross-sectional layout view view of the of HV the parasiticnLDMOS equivalent referencecircuit element. ofthe The LDMOS test element component, used in Figure this e1x-b perimentdisplays the was 3-D a structure nonbutted view, structure and Figure that 1 wasc displays fabricated the layout using view the ofTSMC the HV 0.25 nLDMOS-μm HV reference element. The test element used in this experiment was a nonbutted structure that 60-V bipolar-CMOS-DMOS (BCD) process. The component was developed to improve was fabricated using the TSMC 0.25-µm HV 60-V bipolar-CMOS-DMOS (BCD) process. the ESD discharge current capability. The multifinger symmetrical layout design was The component was developed to improve the ESD discharge current capability. The used in these HV LDMOS transistors to reduce the layout area of elements. The total multifinger symmetrical layout design was used in these HV LDMOS transistors to reduce finger number is four. The channel width (Wf) of each finger of the element was 75 µm. the layout area of elements. The total finger number is four. The channel width (Wf) of each Therefore, the total channel width (Wtot) was 300 μm. A gate-grounded nMOSFET con- finger of the element was 75 µm. Therefore, the total channel width (W ) was 300 µm. A figuration was used in the HV ESD protection structure. The instantaneoustot ESD surge gate-grounded nMOSFET configuration was used in the HV ESD protection structure. The current was discharged through the parasitic BJT path below the nLDMOS below instantaneous ESD surge current was discharged through the parasitic BJT path below the nLDMOS. nLDMOS below nLDMOS.

Guard Bulk ring Bulk Source Gate Drain ring

+ + + + + N STI P STI P STI N STI N

HVPB Qnpn Rbulk SH_P HVNW Rdrift HVNW H60NW H60PW H60NW

P Sub.

(a)

Figure 1. Cont.

Electronics 2021, 10, x FOR PEER REVIEW 3 of 16 Electronics 2021, 10, 178 3 of 15

Bulk ring Source Guard Bulk Gate Drain ring

+ + + + + N STI P STI P STI N STI N HVPB HVNW SH_P HVNW

H60NW H60PW H60NW

P Sub.

(b)

B S G D G S B S G D G S B

Poly N+ Implant P+ Implant Bulk Ring OD Contact Guard Ring

(c)

FigureFigure 1. 1.(a ()a Parasitic) Parasitic equivalent equivalent circuit circuit & & cross-sectional cross-sectional view, view, (b) ( 3-Db) 3- structureD structure view, view, and and (c) layout(c) diagramlayout diagram of the high-voltage of the high n-channel-voltage n- laterallychannel diffusedlaterally metal-oxide–semiconductordiffused metal-oxide–semiconductor transistor tran- (HV sistor (HV nLDMOS) reference device. nLDMOS) reference device.

2.2.2.2. HV HV nLDMOSs nLDMOSs with with Drain Drain Electrode-Embedded Electrode-Embedded Horizontal Horizontal Schottky Schottky Elements Elements (Contact (Contact RowsRows Modulation) Modulation) + InIn this this study, study, we we removed removed the the N Narea+ area in thein the nLDMOS_ref nLDMOS_ref drain drain electrode electrode to form to form an equivalentan equivalent series series Schottky Schottky area structure.area structure. Figure Fig2a,bure display 2a,b display the 3D the structure 3D structure view and view layout view, respectively, of the nLDMOS with the drain electrode parasitic full Schottky and layout view, respectively, of the nLDMOS with the drain electrode parasitic full diode modulation. The nLDMOS formed a Schottky diode and series parasitic BJT-NPN. Schottky diode modulation. The nLDMOS formed a Schottky diode and series parasitic Arranging Schottky diodes in series increases the on-resistance of the HV nLDMOS. BJT-NPN. Arranging Schottky diodes in series increases the on-resistance of the HV nLDMOS.

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Bulk ring Source Guard Bulk Gate Drain ring

+ + + + N STI P STI P STI N STI HVPB HVNW SH_P HVNW

H60NW H60PW H60NW

P Sub.

(a)

B S G D G S B S G D G S B

Poly N+ Implant P+ Implant Bulk Ring OD Contact Guard Ring

(b)

FigureFigure 2. 2.(a )(a 3D) 3D structure structure view view and and (b )(b layout) layout diagram diagram of theof the HV HV nLDMOS nLDMOS with with the the drain drain electrode- elec- embeddedtrode-embedded full Schottky full Schottky device modulation. device modulation.

FigureFigure3a–c 3a– arec are the the 3D 3D structure structure diagram, diagram, layout layout view, view, and and equivalent equivalent circuit circuit of of drain-electrode-embeddeddrain-electrode-embedded horizontal horizontal Schottky Schottky element element modulation modulation of of the the nLDMOS nLDMOS of of thethe nLDMOS. nLDMOS. The The parasitic parasitic Schottky Schottky area area was was modulated modulated by by varying varying the the row row of of contact contact ofof the the Schottky Schottky area. area. The The modulation modulation method method involves involves varying varying the the Schottky Schottky area area by by symmetricallysymmetrically adding adding the the contact contact windows windows laying laying on on the the top top and and bottom bottom rows rows above above the the chipchip surface. surface. The The Schottky Schottky diode diode region region was was gradually gradually increased increased to to 2, 2, 4, 4, 8, 8, 16, 16, 32 32 and and 36 36 rowsrows of of contact contact windows, windows, and and the the effect effect of of the the increase increase in in rows rows on on ESD ESD capability capability was was observed.observed. The The ratio ratio of of the the heavily heavily doped doped NN++ areas to Schottky diode areas areas is is displayed displayed in inTable Table 11.. Equivalently,Equivalently, fromfrom FigureFigure3 c,3c, the theR Ronon willwill bebe increasedincreased as as an an HV HV nLDMOS nLDMOS by by addingadding series series Schottky Schottky diodes diodes in in the the drain drain side. side. Under Under this this parasitic parasitic Schottky Schottky structure, structure, thethe drain drain electrode electrode is equivalent is equivalent to a series to a series Schottky Schottky element element and a high and impedance a high impedance R’drain.

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Furthermore, it is hoped that, through this technique, the It2 can be increased to improve the ESD withstanding capability of the device.

Table 1. Area ratios of N+ and Schottky diode regions in the drain side.

nLDMOS N+ Area (%) Schottky Area (%) Ref. DUT 100 0 HorSchottky_02 94 6 HorSchottky_04 84 16 Electronics 2021, 10, x FOR PEER REVIEW 5 of 16 HorSchottky_08 58 42 HorSchottky_16 42 58 HorSchottky_32 16 84 HorSchottky_36 6 94 R’drain. Furthermore, it is hoped that, through this technique, the It2 can be increased to Full Schottky 0 100 improve the ESD withstanding capability of the device.

Bulk ring Source Guard Bulk Gate Drain ring

+ + + + + N STI P STI P STI N STI N HVPB HVNW SH_P HVNW

H60NW H60PW H60NW

P Sub.

(a)

B S GG D G S B S G D G S B

Poly N+ Implant P+ Implant Bulk Ring OD Contact Guard Ring

(b)

Figure 3. Cont.

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VDD Schottky Diode (1) (2) Rdrain R'drain

Rdrift D

G B Qnpn Rbulk S

GND (c)

Figure 3. (aFigure) 3D structure 3. (a) 3D view,structure (b) layout view, ( diagram,b) layout anddiagram, (c) equivalent and (c) equivalent circuit of thecircuit HV of nLDMOS the HV nLDMOS with the drainwith electrode-embedded the drain electrode-embedded horizontal horizontal Schottky elements Schottky modulation. elements modulation.

2.3. HV nLDMOSsTable 1. Area with ratios the Drain of N+ Electrode-Embeddedand Schottky diode regions Horizontal in the Schottky drain side. Elements (Length Modulation) nLDMOS N+ Area (%) Schottky Area (%) Next, another Schottky modulation for the upper and lower rows of contact windows were used as the variableRef. DUT parameter for Schottky length100 modulation. The Schottky0 area was then graduallyHorSchottky_02 reduced, which effectively reduced94 the length of the Schottky6 area by 1.5 µm on the leftHorSchottky_04 and right sides, 3 µm on the left and84 right sides, and 4.5 µm on16the left and right sides. TheHorSchottky_08 effect of decreasing the ratio of the58 Schottky diode area and the42 length of the current pathHorSchottky_16 to the drain electrode on ESD42 capability was observed. Finally,58 the area ratio of heavilyHorSchottky_32 doped N+ to Schottky diode is16 listed in Table2. Figure4a,b84 display the structure andHorSchottky_36 layout diagrams of HV nLDMOSs6 with the drain electrode-embedded94 horizontal SchottkyFull length Schottky modulation. 0 100

+ Table 2. Area2.3. ratios HV nLDMOSs of N and Schottkywith the diodeDrain regionsElectrode in- theembedded drain electrode. Horizontal Schottky Elements (Length Modulation) nLDMOS N+ Area (%) Schottky Area (%) Next, another Schottky modulation for the upper and lower rows of contact win- Ref. DUT 100 0 DSchottky_450dows were used as the variable parameter 98 for Schottky length modulation. 2 The Schottky DSchottky_300area was then gradually reduced, 97 which effectively reduced the 3 length of the Schottky DSchottky_150area by 1.5 μm on the left and right 96 sides, 3 μm on the left and right 4 sides, and 4.5 μm on DSchottky_0the left and right sides. The effect of decreasing the ratio of the Schottky diode area and 94 6 (Same asthe HorSchottky_02) length of the current path to the drain electrode on ESD capability was observed. Fi- nally, the area ratio of heavily doped N+ to Schottky diode is listed in Table 2. Figure 4a,b display the structure and layout diagrams of HV nLDMOSs with the drain elec- trode-embedded horizontal Schottky length modulation.

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Bulk ring Source Guard Bulk Gate Drain ring

+ + + + + N STI P STI P STI N STI N HVPB HVNW SH_P HVNW

H60NW H60PW H60NW

P Sub.

(a)

Drain Drain

B S G D G S B S G D G S B

Shorten ref 0 m 1.5µm

Drain Drain Poly N+ Implant P+ Implant Bulk Ring OD Contact Guard Ring

Shorten Shorten 3µm 4.5µm (b) Figure 4. (a) 3D structure view and (b) layout diagram of the HV nLDMOS with the drain elec- Figure 4. (a) 3D structure view and (b) layout diagram of the HV nLDMOS with the drain electrode- trode-embedded horizontal Schottky length modulation. embedded horizontal Schottky length modulation.

3.Table Test Method2. Area ratios and of Test N+ Instrumentand Schottky diode regions in the drain electrode. TransmissionnLDMOS line pulse (TLP) systems [40N+– Area42] are (%) generally Schottky used to measureArea (%) the high-voltage andRef. high-current DUT snapback behavior of100 a test device. This TLP0 system uses LabVIEW softwareDSchottky_450 to control and match the peripheral98 electronic instruments2 such as ESD pulse generators,DSchottky_300 high-frequency digital oscilloscopes,97 and digital power3 meters, thus enabling automated measurement mechanisms. This machine can provide a continuous DSchottky_150 96 4 rising square wave to track the I–V characteristic curve of the DUTs, and the short rise and DSchottky_0 fall time of this continuous square wave can be used94 to simulate a fast ESD6 surge. The TLP system(Same is used as HorSchottky_02) to simulate the human body model. Thus, the voltage and current response of the element can be obtained through element measurement, and the behavior of3. short Test ESDMethod pulses and on Test the Instrument protection device can be simulated. Through the TLP system, Transmission line pulse (TLP) systems [40–42] are generally used to measure the high-voltage and high-current snapback behavior of a test device. This TLP system uses

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we can measure I–V characteristics, such as the trigger voltage (Vt1), holding voltage (Vh), secondary breakdown current (It2), and other physical parameters of the component.

4. Experimental Test Results 4.1. HV nLDMOSs with Drain Electrode-Embedded Horizontal Schottky Elements (Contact Rows Modulation) The TLP tester system was used to measure the HV nLDMOS reference device and the DUTs characteristics with drain-electrode-embedded horizontal Schottky modulation (contact rows modulation). The snapback I–V characteristic curve, Vt1/Vh distribution, and secondary breakdown current distribution are displayed in Figures5–7, respectively. The number of contact window rows increased with the drain-electrode-embedded horizontal Schottky area to completely remove the heavily doped N+ area. Obviously, from Figure3c, Schottky_Drain exhibited a higher secondary breakdown current performance than other DUTs because the drain electrode in the series Schottky diode increased the on-resistance (Ron) of the nLDMOS parasitic BJT. Meanwhile, through the measuring test, it can be found that an nLDMOS with the parasitic horizontal Schottky diode at the drain electrode had a limited effect on the breakdown voltage of the device. This modulation of the drain- electrode-embedded horizontal Schottky did not obviously influence the DC breakdown voltage (the maximum value only by 3.95%). Finally, all the measured parameters are displayed in Table3. The Schottky area increased with the increase in the drain side, which increased It2 from 2.23 A in the nLDMOS reference device to a maximum of 4.55 A (104% improvement). From the measured data, it is found that the area of the parasitic Schottky diode in the drain side greatly affects the ESD capability. When the area percentage of an nLDMOS drain side added the Schottky diode exceeds 50%, the ESD robustness (I ) of Electronics 2021, 10, x FOR PEER REVIEW t2 9 of 16 the device is significantly increased. Then, the ESD immunity of nLDMOS was effectively improved by using these techniques.

Leakage Current (A) 10-8 10-7 10-6 10-5 10-4 10-3 10-2

5 Ref HorSchottky_02 HorSchottky_04 4 HorSchottky_08 HorSchottky_16 3 HorSchottky_32 HorSchottky_36 Full Schottky 2

Current (A)

1

0

0 20 40 60 80 100 120 Voltage(V)

Figure 5. Snapback I-V curves and leakage currents of HV nLDMOSs with the drain electrode- Figure embedded5. Snapback horizontal I-V curve Schottkys and leakage rows modulation. currents of HV nLDMOSs with the drain elec- trode-embedded horizontal Schottky rows modulation.

Trigger Voltage(V) 108.0 Holding Voltage(V) 37.5 107.5 37.0 107.0 106.5 36.5 106.0 36.0 105.5

Voltage(V) 105.0 35.5 104.5 35.0

Holding Voltage(V)

Trigger 104.0

103.5 34.5 103.0

Ref Full Schottky HorSchottky_02HorSchottky_04HorSchottky_08HorSchottky_16 HorSchottky_36 HorSchottky_32 Figure 6. Trigger voltage and holding voltage distribution charts of HV nLDMOSs with the drain electrode-embedded horizontal Schottky rows modulation.

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Leakage Current (A) 10-8 10-7 10-6 10-5 10-4 10-3 10-2

5 Ref HorSchottky_02 HorSchottky_04 4 HorSchottky_08 HorSchottky_16 3 HorSchottky_32 HorSchottky_36 Full Schottky 2

Current (A)

1

0

0 20 40 60 80 100 120 Voltage(V)

Electronics 2021, 10, 178 Figure 5. Snapback I-V curves and leakage currents of HV nLDMOSs with the drain elec- 9 of 15 trode-embedded horizontal Schottky rows modulation.

Trigger Voltage(V) 108.0 Holding Voltage(V) 37.5 107.5 37.0 107.0 106.5 36.5 106.0 36.0 105.5

Voltage(V) 105.0 35.5 104.5 35.0

Holding Voltage(V)

Trigger 104.0

103.5 34.5 103.0

Ref Electronics 2021, 10, x FOR PEER REVIEW 10 of 16 Full Schottky HorSchottky_02HorSchottky_04HorSchottky_08HorSchottky_16 HorSchottky_36 HorSchottky_32 FigureFigure 6. 6.TriggerTrigger voltage voltage and and holding holding voltage voltage distribution distribution chart chartss of HV of HV nLDMOS nLDMOSss with with the thedrain drain electrodeelectrode-embedded-embedded horizontal horizontal Schottky Schottky rows rows modulation. modulation.

4.5

4.0

3.5

3.0

2.5

2nd Breakdown Current (A)

2.0

Ref Full Schottky HorSchottky_02HorSchottky_04HorSchottky_08HorSchottky_16 HorSchottky_32HorSchottky_36

FigureFigure 7. Secondary 7. Secondary breakdown breakdown-current-current distribution distribution chart chart of of HV HV nLDMOSs nLDMOS withs with the drain the drain electrode- elec- trodeembedded-embedded horizontal horizontal Schottky Schottky rows rows modulation. modulation.

TableTable 3. Snapback 3. Snapback extracted extracted parameters parameters of HV of HV nLDMOS nLDMOSss with with the the drain drain electrode electrode-embedded-embedded horizontalhorizontal Schottky Schottky rows rows modulation modulation..

nLDMOSnLDMOS Schottky AreaSchottky % Area Vt1 (V) % V Vht1 (V)(V) Vh (V) It2 (A) It2 (A) Ref.Ref. DUTDUT 00 105.18105.1 34.808 34.80 2.23 2.23 HorSchottky_02 6 105.40 34.54 2.33 HorSchottky_02HorSchottky_04 166 106.75105. 35.0740 34.54 2.34 2.33 HorSchottky_04HorSchottky_08 4216 106.45106. 35.4175 35.07 2.35 2.34 HorSchottky_08HorSchottky_16 5842 106.65106. 35.1145 35.41 2.63 2.35 HorSchottky_32 84 105.52 35.83 2.67 HorSchottky_16HorSchottky_36 9458 107.20106.6 37.155 35.11 2.73 2.63 HorSchottky_32Full Schottky 10084 106.55105.5 36.492 35.83 4.55 2.67 HorSchottky_36 94 107.20 37.15 2.73 Full Schottky 100 106.55 36.49 4.55

4.2. HV nLDMOSs with the Drain Electrode-Embedded Horizontal Schottky Elements (Length Modulations) Furthermore, the Schottky length of the nLDMOS drain electrode was reduced to achieve modulation. The components were measured using the TLP tester. The snap- back I–V characteristic curve, Vt1/Vh distribution, and secondary breakdown current dis- tribution are displayed in Figures 8–10, respectively. When the length of the Schottky area was decreased by reducing the length of the drain-electrode-embedded horizontal Schottky diode. The Schottky area of the drain electrode of the element gradually de- creased, and the contact resistance of the drain electrode equivalent series to the Schott- ky diode also decreased. Similarly, through the measuring test, it can be found that an nLDMOS with the parasitic horizontal Schottky diode at the drain electrode of this modulation did not influence the DC breakdown voltage (the maximum value was only 2.51%). The secondary breakdown current of ESD immunity was reduced considerably. The measured parameters measured are displayed in Table 4. As the area of Schottky decreased to its minimum value, its It2 also reached the minimum (2.13 A).

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4.2. HV nLDMOSs with the Drain Electrode-Embedded Horizontal Schottky Elements (Length Modulations) Furthermore, the Schottky length of the nLDMOS drain electrode was reduced to achieve modulation. The components were measured using the TLP tester. The snapback I–V characteristic curve, Vt1/Vh distribution, and secondary breakdown current distribu- tion are displayed in Figures8–10, respectively. When the length of the Schottky area was decreased by reducing the length of the drain-electrode-embedded horizontal Schottky diode. The Schottky area of the drain electrode of the element gradually decreased, and the contact resistance of the drain electrode equivalent series to the Schottky diode also decreased. Similarly, through the measuring test, it can be found that an nLDMOS with the parasitic horizontal Schottky diode at the drain electrode of this modulation did not influence the DC breakdown voltage (the maximum value was only 2.51%). The secondary Electronics 2021, 10, x FOR PEER REVIEW 11 of 16 breakdown current of ESD immunity was reduced considerably. The measured parameters Electronics 2021, 10, x FOR PEER REVIEW measured are displayed in Table4. As the area of Schottky decreased to its11 minimumof 16 value,

its It2 also reached theLeakage minimum Current (2.13 A).(A) 10-8 10-7 10-6 10-5 10-4 10-3 10-2 3.0 Leakage Current (A) 10-8 10-7 10-6 10-5 10-4 10-3 10-2 3.0 Ref. 2.5 DSchottky_450 DSchottky_300Ref. 2.5 2.0 DSchottky_150DSchottky_450 DSchottky_0DSchottky_300 2.0 DSchottky_150 1.5 DSchottky_0 1.5

Current (A) 1.0

Current (A) 1.0 0.5

0.5 0.0

0.0 0 20 40 60 80 100 120 Voltage(V) 0 20 40 60 80 100 120 Voltage(V) Figure 8. Snapback I-V curves and leakage currents of HV nLDMOSs with the drain elec-

trodeFigure-embedded 8. Snapbackhorizontal Schottky I-V curves length and modulation. leakage currents of HV nLDMOSs with the drain electrode- Figure 8. Snapback I-V curves and leakage currents of HV nLDMOSs with the drain elec- trodeembedded-embedded horizonta horizontall Schottky Schottky length length modulation. modulation.

107 Trigger Voltage(V) 37 Holding Voltage(V) 107 Trigger Voltage(V) 37 Holding Voltage(V) 36 106 36 106 35

Voltage (V) Voltage 35

Voltage (V) Voltage 105 34

Holding Voltage(V) Holding

Trigger Trigger 105 34

Holding Voltage(V) Holding

Trigger Trigger

104 33

104 Ref 33 DSchottky_0 RefDSchottky_450DSchottky_300DSchottky_150

FigureFigure 9. Trigger 9. Trigger voltage voltageand holding and voltage holding distribution voltage distribution charts ofDSchottky_0 HV chartsnLDMOS ofs HV with nLDMOSs the drain with the drain DSchottky_450DSchottky_300DSchottky_150 electrodeelectrode-embedded-embedded horizontal horizontal Schottky Schottkylength modulation. length modulation. Figure 9. Trigger voltage and holding voltage distribution charts of HV nLDMOSs with the drain electrode-embedded horizontal Schottky length modulation.

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2.6

2.4

2.2

2.0

1.8

2nd Breakdown Current (A) Current Breakdown 2nd 1.6

Ref DSchottky_0 DSchottky_450DSchottky_300DSchottky_150 FigureFigure 10. Secondary 10. Secondary breakdown breakdown-current-current distribution distribution chart of HV chart nLDMOS of HV nLDMOSss with the drain with elec- the drain electrode- trode-embedded horizontal Schottky length modulation. embedded horizontal Schottky length modulation. Table 4. Snapback extracted parameters of HV nLDMOSs with the drain electrode-embedded horizontalTable Schottky 4. Snapback length extractedmodulation. parameters of HV nLDMOSs with the drain electrode-embedded horizontal Schottky length modulation. nLDMOS Schottky Area % Vt1 (V) Vh (V) It2 (A) Ref. DUT 0 105.18 34.80 2.23 nLDMOS Schottky Area % Vt1 (V) Vh (V) It2 (A) DSchottky_450 2 105.41 34.28 2.13 Ref. DUT 0 105.18 34.80 2.23 DSchottky_300 3 106.60 35.21 2.22 DSchottky_450 2 105.41 34.28 2.13 DSchottky_150 4 105.34 34.99 2.26 DSchottky_300 3 106.60 35.21 2.22 DSchottky_0DSchottky_150 46 105.34105.40 34.54 34.99 2.33 2.26 DSchottky_0 6 105.40 34.54 2.33 4.3. Summary of HV nLDMOSs with Drain Electrode-Embedded Horizontal Schottky Elements 4.3.As Summarydescribed of above, HV nLDMOSs the ESD capability with Drain (It2 Electrode-Embedded) value and Schottky Horizontal-area percentage Schottky Elements comparisons of HV nLDMOSs with the drain electrode-embedded horizontal Schottky elements Asby the described row and above,length modula the ESDtions capability are organized (It2) as value shown and in Schottky-areaFigure 11a and percentage b, respectively.comparisons According of HV nLDMOSsto the equivalent with circuit the drain diagram electrode-embedded of Figure 3c, if the Schottky horizontal Schottky diodeelements is parasitically by the embedded row and in length the drain modulations side of an nLDMOS, are organized the ESD as transient shown cur- in Figure 11a,b, rentrespectively. under the action According of an ESD to w theill flow equivalent through circuit the path diagram (1) (the of partial Figure nLDMOS)3c, if the and Schottky diode the pathis parasitically (2) (the parasitic embedded Schottky in thediode). drain In sidethe case of an of nLDMOS, an HV nLDMOS the ESD with transient the drain current under electrodethe action-embedded of an horizontal ESD will Schottky flow through elements the, the path conduction (1) (the partial-on resistance nLDMOS) of this and the path nLDMOS(2) (the with parasitic a parasitic Schottky Schottky diode). diode In (path the case (2)) ofis higher an HV than nLDMOS that of with others the nLD- drain electrode- MOSembedded part (path horizontal(1)). The main Schottky ESD current elements, flows thethrough conduction-on the nLDMOS resistance path (1). How- of this nLDMOS ever, when the area of the Schottky diode increases, it means that the area of the with a parasitic Schottky diode (path (2)) is higher than that of others nLDMOS part (path drain-electrode for removing heavily doped N+ increases. Due to the low-doped NWell (1)). The main ESD current flows through the nLDMOS path (1). However, when the area under the drain-electrode, it has a high impedance and favor to limit the ESD current. of the Schottky diode increases, it means that the area of the drain-electrode for removing Therefore, when the Schottky area of the component is higher, the improvement of It2 is + moreheavily obvious, doped especially N increases.as the area Duepercentage to the of low-doped an nLDMOS NWell drain underside added the drain-electrode,to the it Schottkyhas a diode high exceeds impedance 50%. andWhen favor the area to limitpercentage the ESD of drain current.-side Therefore,added the Schottky when the Schottky diodearea exceeds of the 94%, component this ESD transient is higher, current the improvement cannot have more of Ipatht2 is options more obvious, (it will be especially as morethe uniform), area percentage the robustness of an (It2 nLDMOS) of the device drain is significantly side added increased. to the Schottky This is diodealso the exceeds 50%. reasonWhen why the the area It2 will percentage be the highest of drain-side value for an added nLDMOS the Schottky device with diode drain exceeds side cov- 94%, this ESD eredtransient 100% full current parasitic cannot Schottky have diode. more pathHowever, options as the (it will area be ratio more of uniform), the parasitic the robustness Schottky diode is small, the conduction path of the device is dominated by the nLDMOS (It2) of the device is significantly increased. This is also the reason why the It2 will be the highest value for an nLDMOS device with drain side covered 100% full parasitic Schottky diode. However, as the area ratio of the parasitic Schottky diode is small, the conduction

path of the device is dominated by the nLDMOS path (1). Then, the characteristics of the parasitic series Schottky diode are not obvious. This leads to the lower It2 values of these components corresponding to Figure 11b. Electronics 2021, 10, x FOR PEER REVIEW 13 of 16

path (1). Then, the characteristics of the parasitic series Schottky diode are not obvious. Electronics 2021, 10, 178 12 of 15 This leads to the lower It2 values of these components corresponding to Figure 11b.

5.0 100 Schottky area(%) 90 ESD capability (A) 4.5 80 70 4.0 60 3.5 50 40 Fig.(b) 3.0

ESD capability (A) Schottky area (%) 30 20 2.5 10 0 2.0 Ref Full Schottky HorSchottky_02HorSchottky_04HorSchottky_08HorSchottky_16 HorSchottky_32HorSchottky_36

(a)

10 4.0

Schottky area (%) 8 ESD capability (A) 3.5

6 3.0

4

2.5 ESD capability (A) Schottky area (%) 2

0 2.0 Ref DSchottky_450DSchottky_300DSchottky_150DSchottky_0

(b)

Figure 11. ESD capability (It2) values and Schottky-area % comparison of HV nLDMOSs with the Figure 11. ESD capability (It2) values and Schottky-area % comparison of HV nLDMOSs with the draindrain electrode electrode-embedded-embedded horizontal horizontal Schottky Schottky elements elements by the by (a) the row (a )modulation row modulation and (b and) length (b) length modulation. modulation.

5. Conclusion5. Conclusionss This Thisstudy study described described the effect the effectof the of drain the- drain-electrodeelectrode of horizontal of horizontal Schottky Schottky modu- mod- lationulation on ESD on protection. ESD protection. When Whenthe contact the contact row modulation row modulation was performedwas performed for the for the draindrain-electrode-embedded-electrode-embedded horizontal horizontal Schottky Schottky diode, diode, the the area area of of the the Schottky Schottky diode diode grad- graduallyually increased. increased. UnderUnder the the parasitic parasitic Schottky Schottky structure structure of part of part or all or of all the of drain the drain electrode, electrode,the equivalent the equivalent ON-resistance ON-resistance of the overall of the HV overall LDMOS HV device LDMOS will devicebe increased. will be Therefore, in- creased.a higher Therefore, Schottky a higher area inSchottky the drain area electrode in the drain of the electrode element resultsof the element in a higher results secondary in a higherbreakdown secondary current. breakdown The component current. The can com withstandponent a can larger withstand ESD current. a larger Therefore, ESD cur- when the area of the drain electrode Schottky diode increases, the ESD immunity will increase significantly, especially when the area percentage of the Schottky diode exceeds 50%. Espe- cially, when the nLDMOS drain side is all covered with the parasitic Schottky diode, its ESD capability (It2) will increase from 2.23 A in the nLDMOS Reference device to a maxi- Electronics 2021, 10, 178 13 of 15

mum value of 4.55 A (an increase of 104%). The It2 was excellent, and the ESD protection capability of the device was also satisfactory.

Author Contributions: Conceptualization, S.-Z.H. and S.-L.C.; data curation, S.-Z.H.; formal analy- sis, S.-Z.H.; investigation, S.-Z.H. and S.-L.C.; project administration, S.-L.C.; supervision, S.-L.C.; validation, S.-Z.H. and S.-L.C.; writing—original draft, S.-Z.H.; writing—review and editing, S.-L.C. All authors have read and agreed to the published version of the manuscript. Funding: This research was no external funding. Data Availability Statement: Data can be provided according to industry R&D requirements (The data used in the study may be available depending on the corresponding author). Acknowledgments: In this work, the authors would like to thank the Taiwan Semiconductor Re- search Institute in Taiwan for providing the process information and fabrication platform of TSMC. Conflicts of Interest: The authors declare no conflict of interest.

Abbreviations

BCD Bipolar-CMOS-DMOS BJT Bipolar transistor ESD Electrostatic discharge GDT Gas discharge tube HV High-voltage It2 Secondary breakdown current LDMOS Lateral diffused metal-oxide-semiconductor transistor SPG Spark gap STI Shallow trench isolation TLP Transmission-line Pulse TVS Transient voltage suppressor VDR Voltage-dependent resistor Vh Holding voltage VLSI Very-large-scale integration Vt1 Trigger voltage

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