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ESD Design and Analysis by Drain Electrode-Embedded Horizontal Schottky Elements for HV Nldmoss

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ESD Design and Analysis by Drain Electrode-Embedded Horizontal Schottky Elements for HV Nldmoss electronics Article ESD Design and Analysis by Drain Electrode-Embedded Horizontal Schottky Elements for HV nLDMOSs Shi-Zhe Hong and Shen-Li Chen * Department of Electronic Engineering, National United University, Miaoli City 36063, Taiwan; [email protected] * Correspondence: [email protected]; Tel.: +886-37-382525 Abstract: Electrostatic discharge (ESD) events can severely damage miniature components. Therefore, ESD protection is critical in integrated circuits. In this study, drain-electrode-embedded horizontal Schottky diode contact modulation and Schottky length reduction modulation were performed on a high-voltage 60-V n-channel laterally diffused metal-oxide–semiconductor transistor (nLDMOS) element. The effect of the on-voltage characteristics of cascade Schottky diodes on ESD protection was investigated. By using a transmission-line pulse tester, the trigger voltage, holding voltage, and secondary breakdown current (It2) of the nLDMOS element were determined using the I–V characteristic. As the N+ area was gradually replaced by the parasitic Schottky area at the drain electrode, an equivalent circuit of series Schottky diodes formed, which increased the on-resistance. The larger the Schottky area was the higher the It2 value was. This characteristic can considerably improve the ESD immunity of nLDMOS components (highest improvement of 104%). This is a good strategy for improving ESD reliability without increasing the production steps and fabrication cost. Keywords: electrostatic discharge (ESD); holding voltage (Vh); lateral diffusion MOS (LDMOS); schottky diode; secondary breakdown current (It2); transmission-line pulse system (TLP system) Citation: Hong, S.-Z.; Chen, S.-L. 1. Introduction ESD Design and Analysis by Drain Although the efficiency and speed of components have improved with the evolution Electrode-Embedded Horizontal of semiconductor processes, component integration and cost considerations have become a Schottky Elements for HV nLDMOSs. Electronics 2021, 10, 178. https:// concern. Generally, compact components are desired. Although the economic benefits of doi.org/10.3390/electronics10020178 advanced components have increased, reliability uncertainties have also increased. Even a small defect during manufacturing can cause considerable losses to the manufacturer. Received: 7 December 2020 Electrostatic discharge (ESD) events [1–10] for integrated circuits (ICs) are the major hazard Accepted: 13 January 2021 to reliability. Published: 15 January 2021 Common discrete ESD protection devices are laterally diffused metal-oxide– semiconductor transistors (LDMOSs), gas discharge tube (GDTs), spark gap (SPGs), tran- Publisher’s Note: MDPI stays neu- sient voltage suppressor (TVSs), and voltage-dependent resistor (VDRs). However, in tral with regard to jurisdictional clai- this paper, a power management high-voltage integrated circuit manufactured by a very- ms in published maps and institutio- large-scale interaction bipolar-CMOS-DMOS (VLSI BCD) process uses LDMOS devices nal affiliations. to form HV circuits and discusses how to protect their ESD reliability. This LDMOS ESD protection device can be used to protect the I/O port of the circuit. Therefore, LDMOSs have been effectively used in integrated circuits for power electronics, Internet of things (IoT) applications, vehicle electronics, and ESD protection components [11–25], and their Copyright: © 2021 by the authors. Li- censee MDPI, Basel, Switzerland. importance is gradually increasing. A high-voltage LDMOS has a longer drift region and This article is an open access article shallow trench isolation (STI) region. Then, this device has a larger depletion region and distributed under the terms and con- higher on-resistance (Ron) allowing it to operate under high voltage. However, the operat- ditions of the Creative Commons At- ing voltage of LDMOSs is considerably high. Good reliability and the ability to withstand tribution (CC BY) license (https:// large currents are critical in high-current devices. Therefore, the effective discharge of large creativecommons.org/licenses/by/ currents is essential. However, the current density of these high-voltage LDMOS devices 4.0/). is often concentrated between the drain and STI. Therefore, the LDMOS has lower ESD Electronics 2021, 10, 178. https://doi.org/10.3390/electronics10020178 https://www.mdpi.com/journal/electronics Electronics 2021, 10, x FOR PEER REVIEW 2 of 16 ity and the ability to withstand large currents are critical in high-current devices. There- fore, the effective discharge of large currents is essential. However, the current density Electronics 2021, 10, 178 of these high-voltage LDMOS devices is often concentrated between the drain and2 STI. of 15 Therefore, the LDMOS has lower ESD protection capabilities and at the same time is prone to disadvantages such as latch-up effects [26–32]. Schottky diodes [33–39] typical- lyprotection include capabilitiesmetals and andsemiconductor at the same junctions. time is prone In this to disadvantages work, we combined such as latch-upthe low turneffects-on [ 26voltage–32]. Schottky characteristic diodes of [33 Schottk–39] typicallyy diodes include with metalsnLDMOSs and semiconductorto form a parasitic junc- horizontaltions. In this Schottky work, we region combined at the thedrain low electrode turn-on voltageof the nLDMOS characteristic element. of Schottky Such compo- diodes nentswith nLDMOSsexhibit superior to form reliability a parasitic and horizontal can withstand Schottky high region ESD atcurrents. the drain electrode of the nLDMOS element. Such components exhibit superior reliability and can withstand high 2.ESD Sample currents. Designs of the HV nLDMOS 2.1. HV nLDMOS Reference Device 2. Sample Designs of the HV nLDMOS High-voltage (HV) laterally diffused metal-oxide–semiconductor transistors 2.1. HV nLDMOS Reference Device (LDMOS) are often used as ESD protection components at the input/output electrodes of circuitsHigh-voltage to prevent (HV)the circuit laterally latch diffused-up effect, metal-oxide–semiconductor which causes the element transistors to burn (LDMOS) out. We designedare often usedLDMOSs as ESD with protection a protective components ring. Typically, at the input/outputto withstand electrodeshigh voltage, of circuitsa long driftto prevent region the is necessary circuit latch-up and various effect, whichconcentration causes theregions element of N to-type burn and out. P- Wetype designed doping arLDMOSse used to with form a protectivea concentration ring. Typically,gradient. Furthermore, to withstand highthe element voltage, has a long a high drift drift region re- gionis necessary resistance. and Various various concentrationconcentration regionsgradients of N-typeare used and to P-type disperse doping strong are usedelectric to fieldsform aand concentration extend the gradient.length of Furthermore, the depletion the region element to increase has a high the drift breakdown region resistance. voltage. FigureVarious 1a concentration displays the gradients cross-sectional are used view to disperse of the strongparasitic electric equivalent fields andcircuit extend of the LDMOSlength of component, the depletion Figure region 1b to displays increase the the 3 breakdown-D structure voltage. view, and Figure Figure1a displays 1c displays the thecross-sectional layout view view of the of HV the parasiticnLDMOS equivalent referencecircuit element. ofthe The LDMOS test element component, used in Figure this e1x-b perimentdisplays thewas 3-D a structurenonbutted view, structure and Figure that 1wasc displays fabricated the layout using view the ofTSMC the HV 0.25 nLDMOS-μm HV reference element. The test element used in this experiment was a nonbutted structure that 60-V bipolar-CMOS-DMOS (BCD) process. The component was developed to improve was fabricated using the TSMC 0.25-µm HV 60-V bipolar-CMOS-DMOS (BCD) process. the ESD discharge current capability. The multifinger symmetrical layout design was The component was developed to improve the ESD discharge current capability. The used in these HV LDMOS transistors to reduce the layout area of elements. The total multifinger symmetrical layout design was used in these HV LDMOS transistors to reduce finger number is four. The channel width (Wf) of each finger of the element was 75 µm. the layout area of elements. The total finger number is four. The channel width (Wf) of each Therefore, the total channel width (Wtot) was 300 μm. A gate-grounded nMOSFET con- finger of the element was 75 µm. Therefore, the total channel width (W ) was 300 µm. A figuration was used in the HV ESD protection structure. The instantaneoustot ESD surge gate-grounded nMOSFET configuration was used in the HV ESD protection structure. The current was discharged through the parasitic BJT path below the nLDMOS below instantaneous ESD surge current was discharged through the parasitic BJT path below the nLDMOS. nLDMOS below nLDMOS. Guard Bulk ring Bulk Source Gate Drain ring + + + + + N STI P STI P STI N STI N HVPB Qnpn Rbulk SH_P HVNW Rdrift HVNW H60NW H60PW H60NW P Sub. (a) Figure 1. Cont. Electronics 2021, 10, x FOR PEER REVIEW 3 of 16 Electronics 2021, 10, 178 3 of 15 Bulk ring Source Guard Bulk Gate Drain ring + + + + + N STI P STI P STI N STI N HVPB HVNW SH_P HVNW H60NW H60PW H60NW P Sub. (b) B S G D G S B S G D G S B Poly N+ Implant P+ Implant Bulk Ring OD Contact Guard Ring (c) FigureFigure 1. 1.(a ()a Parasitic) Parasitic equivalent equivalent circuit circuit & & cross-sectional cross-sectional view, view, (b)
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