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Introduction to Semico Nductor Manufacturing and FA Process IPC Technical Seminar Kenny Seon (IFKOR QM IPC) 13-Sep-2017 Table of Contents

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Introduction to Semico Nductor Manufacturing and FA Process IPC Technical Seminar Kenny Seon (IFKOR QM IPC) 13-Sep-2017 Table of Contents Introduction to Semico nductor Manufacturing and FA Process IPC Technical Seminar Kenny Seon (IFKOR QM IPC) 13-Sep-2017 Table of Contents 1 Course Objective 2 Basic Semiconductor 3 Semiconductor Supply Chain 4 Semiconductor Manufacturing Processes Overview 5 Frontend End(Wafer Fabrication) Process 6 Back End(Assembly & Test) Process 7 Semiconductor FA(Failure Analysis) Process Copyright © Infineon Technologies AG 2017. All rights reserved. Table of Contents 1 Course Objective 2 Basic Semiconductor 3 Semiconductor Supply Chain 4 Semiconductor Manufacturing Processes Overview 5 Frontend End(Wafer Fabrication) Process 6 Back End(Assembly & Test) Process 7 Semiconductor FA(Failure Analysis) Process Copyright © Infineon Technologies AG 2017. All rights reserved. Course Objective • Provide basic understanding on Semiconductor. • Introduce semiconductor process flow from wafer fabrication to package assembly and final test, and what the semiconduc tor device failure analysis is and how it is conducted. Copyright © Infineon Technologies AG 2017. All rights reserved. Table of Contents 1 Course Objective 2 Basic Semiconductor 3 Semiconductor Supply Chain 4 Semiconductor Manufacturing Processes Overview 5 Frontend End(Wafer Fabrication) Process 6 Back End(Assembly & Test) Process 7 Semiconductor FA(Failure Analysis) Process Copyright © Infineon Technologies AG 2017. All rights reserved. Basic Semiconductor What is a Semiconductor? • A conductor is a material which “conducts” electricity easily (su ch as metals). • An insulator is a material which is a very poor conductor of ele ctricity (such as glass). • A semiconductor (silicon) is a material which acts like an insu lator, but can behave like a conductor when it is combined wit h other materials. “Semi + Conductor” or “半 + 導體” Copyright © Infineon Technologies AG 2017. All rights reserved. Basic Semiconductor Silicon in the environment • Silicon is the seventh-most abundant element in the universe and the second-most abundant element on the planet, after oxygen. • Silicon makes up about 25 percent of the Earth's crust. • Silicon has good thermal conductivity. Copyright © Infineon Technologies AG 2017. All rights reserved. Basic Semiconductor Semiconductors in the Periodic System Periodic Table of the Elements Copyright © Infineon Technologies AG 2017. All rights reserved. Basic Semiconductor Silicon Crystalline Structure • A crystal is a solid composed of atoms in a SINGLE UNIFORM array/structure. • Each silicon atom is “connected” to its four nearest neighb oring silicon atoms. – – – – – – – – – Si – Si – Si – Si –– Si – Si – Si – Si – – – – – – – – – – Si – Si – Si – Si –– Si – Si – Si – Si – – – – – – – – – – Si – Si – Si – Si –– Si – Si – Si – Si – – – – – – – – – – Si – Si – Si – Si –– Si – Si – Si – Si – – – – – – – – – Copyright © Infineon Technologies AG 2017. All rights reserved. Basic Semiconductor Covalent Bond(Sharing Electron) • Many atoms including silicon like to have EIGHT electrons in the ir outer “orbit”. • But, silicon only has FOUR outer electrons. • Solution: Bonding between two Si atoms by sharing 1 electron f rom each atom. Diamond cubic crystal structure Copyright © Infineon Technologies AG 2017. All rights reserved. Basic Semiconductor Bond Pictures of N-type & P-Type Silicon N-Type P-Type Additional hole in donor acceptor electron valence band Si As / P Si B electron electron hole covalent bond covalent bond Arsenic (As) and Phosphor (P) have Boron (B) has 3 valence electrons 5 valence electrons 1 electron is missing, a hole can 1 additional electron can move move through the crystal through the crystal Conduction Conduction Copyright © Infineon Technologies AG 2017. All rights reserved. Basic Semiconductor From Sand to Silicon Wafer Sand Silicon Wafers Copyright © Infineon Technologies AG 2017. All rights reserved. Basic Semiconductor Silicon Wafer Production Process 1. Polycrystalline Silicon 5. Slicing 9. Polishing 2. Crystal Growth 6. Edge Rounding 10. Cleaning 3. Single Crystal 7. Lapping 11. Inspection Silicon Ingot 4. Crystal Trimming 8. Etching(Chemical 12. Packing / Shipping and Grinding Polishing) Copyright © Infineon Technologies AG 2017. All rights reserved. Basic Semiconductor Chronology of Silicon Wafer Size Increase Copyright © Infineon Technologies AG 2017. All rights reserved. Basic Semiconductor Wafer Size Comparison:200mm vs. 300mm Chips per Cost per wafer(%) wafer(%) Copyright © Infineon Technologies AG 2017. All rights reserved. Table of Contents 1 Course Objective 2 Basic Semiconductor 3 Semiconductor Supply Chain 4 Semiconductor Manufacturing Processes Overview 5 Frontend End(Wafer Fabrication) Process 6 Back End(Assembly & Test) Process 7 Semiconductor FA(Failure Analysis) Process Copyright © Infineon Technologies AG 2017. All rights reserved. Semiconductor Supply Chain Wafer Assembly & Fabrication Test Customers (Front End) (Back End) Copyright © Infineon Technologies AG 2017. All rights reserved. Table of Contents 1 Course Objective 2 Basic Semiconductor 3 Semiconductor Supply Chain 4 Semiconductor Manufacturing Processes Overview 5 Frontend End(Wafer Fabrication) Process 6 Back End(Assembly & Test) Process 7 Semiconductor FA(Failure Analysis) Process Copyright © Infineon Technologies AG 2017. All rights reserved. Semiconductor Manufacturing Processes Overview Copyright © Infineon Technologies AG 2017. All rights reserved. Table of Contents 1 Course Objective 2 Basic Semiconductor 3 Semiconductor Supply Chain 4 Semiconductor Manufacturing Processes Overview 5 Frontend End(Wafer Fabrication) Process 6 Back End(Assembly & Test) Process 7 Semiconductor FA(Failure Analysis) Process Copyright © Infineon Technologies AG 2017. All rights reserved. Front End Process (Wafer Fabrication) Front End(FE) Process Wafer Fabrication Process Wafer Semiconductor Pattern Preparation Circuit Design Preparation Stepper Photoresist Oxidation Exposure Coating Layering Ion Development Etching Implantation Chemical Wafer Test Metallization Vapor Deposition Copyright © Infineon Technologies AG 2017. All rights reserved. Front End(FE) Process Wafer Frabrication Processes FURNACE IMPLANT DD ETCH PVD / MCVD IN/OUT TEST Pure Silicon Wafer Structured Wafer CVD C M P W E T METROLOGY LITHO Copyright © Infineon Technologies AG 2017. All rights reserved. Front End(FE) Process Cross section view of full process Cross Section Single Chip(Die) PA SION Al PAD PA OX M IMD 5 5 Via 4 M IMD 4 4 Via 3M IMD 3 3 Via M 2 IMD 2 2 Via 1 IMD 1 M 1 P+ P+ N+ N+ N-Well P-Well Copyright © Infineon Technologies AG 2017. All rights reserved. Front End(FE) Process Front End Process Line Copyright © Infineon Technologies AG 2017. All rights reserved. Table of Contents 1 Course Objective 2 Basic Semiconductor 3 Semiconductor Supply Chain 4 Semiconductor Manufacturing Processes Overview 5 Frontend End(Wafer Fabrication) Process 6 Back End(Assembly & Test) Process 7 Semiconductor FA(Failure Analysis) Process Copyright © Infineon Technologies AG 2017. All rights reserved. Back End Process (Assembly & Test) Back End(BE) Process Semiconductor Packaging(Assembly & Test) • The process of encasing a die(chip) in materials such as plastic or metal. • Prevent physical damage and corrosion. • Support the electrical contacts which connect the device to a circuit board. • Dissipate heat produced in the device. Copyright © Infineon Technologies AG 2017. All rights reserved. Back End(BE) Process Package Variations LEAD FRAME PACKAGE LAMINATE WAFER PACKAGE LEVEL P-DSO 430mils P-DSO 300mils P-LCC (Plastic Dual-in- PACKAGE (Plastic Dual-in- (Plastic Leaded PBGA WLB line Small Outline) line Small Outline) Chip Carrier (Plastic Ball (Wafer Level Grid Array) Ball Grid Array) SC70 (Small Outline Transistor) LFBGA P-DIP TSSOP (Low Profile Fine- WLP (Plastic Dual-In- (Thin Shrink Small Pitch Ball Grid Array) (Wafer Level line Package) Outline Package) Package) SOT-23 (Small Outline Transistor) MQFP (Metric Quad VQFN DPAK LF2BGA Flat Package) (Very thin Quad (Decawatt (Low Profile Fine- Flat No lead) Package) Pitch Flip Chip Ball Grid Array) Copyright © Infineon Technologies AG 2017. All rights reserved. Back End(BE) Process Package Technologies Copyright © Infineon Technologies AG 2017. All rights reserved. Back End(BE) Process Back-End(Assembly and Test) Process Wafer Wafer Wafer Die Die Attach Back Mounting Sawing Attach Cure Grinding Post Mold Lead Finish Wire Marking Cure Molding (Plating) Bonding (PMC) Final Visual Trim/Form/S Final Test Inspection Packing Shipping ingulation (FVI) Copyright © Infineon Technologies AG 2017. All rights reserved. Back End(BE) Process Wafer Back Grinding • The typical wafer supplied from ‘wafer fab’ is 600 to 750μm thick. • Wafer thinned down to the required thickness, 50um to 75um, by abrasive grinding wheel. › 1st step : Use a large grit to coarsely grind the wafer and remove the bulk of the excess wafer thickness. › 2nd step : Use a finer grit to polish the wafer and to accurately grind the wafer to the required thickness. Copyright © Infineon Technologies AG 2017. All rights reserved. Back End(BE) Process Wafer Mounting • Mount a wafer backside onto a sticky tape which is stretched onto a wafer frame for easy handling purpose during the wafer saw and die attach processes. Sticky Tape for Wafer Mount Wafer Mount Frame (Blue tape) Copyright © Infineon Technologies AG 2017. All rights reserved. Back End(BE) Process Wafer Sawing(Dicing Saw) • Process by which individual silicon chips (die) are separated from each other on the wafer. • Get the wafer cut per each lines
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