Innoswitch4-CZ Family

InnoSwitch4-CZ Family

Off-Line CV/CC ZVS Flyback Integrated Switcher IC with 750 V PowiGaN, Active Clamp Drive and Synchronous Rectification

Product Highlights VBUS ClampZero Highly Integrated, Compact Footprint • Zero voltage switching (ZVS) flyback controller with driver for TM ClampZero (active clamp IC) RTN • Unique control algorithm to enable ZVS in both DCM and CCM • Robust 750 V PowiGaNTM primary switch SR BPS FB GND IS • Steady-state switching frequency up to 140 kHz minimizes D V FW InnoSwitch4-CZ transformer size VOUT Primary Switch • Synchronous rectification driver and secondary-side sensing and Controller • Integrated FluxLinkTM, HIPOT-isolated, feedback link S HSD BPP Secondary Control IC • Exceptional CV/CC accuracy, independent of external components PI-9288-122220 • Adjustable accurate output current sense using external sense resistor Figure 1. Typical Application schematic EcoSmart™ – Energy Efficient • Up to 95% efficient • Less than 30 mW no-load consumption including line sense Advanced Protection / Safety Features • Open SR FET-gate detection • Fast input line UV/OV protection Optional Features • Variable output voltage, constant current profiles • Auto-restart or latching fault response for output OVP/UVP • Multiple output UV fault thresholds • Latching or hysteretic primary over-temperature protection Figure 2. High Creepage, Safety-Compliant InSOP-24D Package. Full Safety and Regulatory Compliance • Reinforced isolation >4000 VAC • 100% production HIPOT testing • UL1577 and TUV (EN60950) safety approved Output Power Table • Excellent noise immunity enables designs that achieve class “A” performance criteria for EN61000-4 suite; EN61000-4-2, 4-3 85-264 VAC 385 VDC (PFC Input)

(30 V/m), 4-4, 4-5, 4-6, 4-8 (100 A/m) and 4-9 (1000 A/m) 3 Product Open Open Adapter1 Adapter1 Green Package Frame2 Frame2 • Halogen free and RoHS compliant INN4073C 60 W 70 W 75 W 80 W Applications INN4074C 75 W 85 W 95 W 100 W • High density flyback designs up to 110 W • High efficiency CV/CC power supplies INN4075C 80 W 90 W 105 W 110 W • High efficiency USB PD adapters Table 1. Output Power Table. Description Notes: 1. Minimum continuous power in a typical non-ventilated enclosed typical size The InnoSwitch™4-CZ family of ICs partners with the ClampZero family adapter measured at 40 °C ambient. Max output power is dependent on the of active clamp ICs to dramatically improve the efficiency of flyback design. With condition that package temperature must be < 125 °C. 2. Minimum peak power capability. power converters, particularly those requiring a compact form-factor. 3. Package: InSOP-24D. The InnoSwitch4-CZ family incorporates primary and secondary controllers and safety-rated feedback into a single IC. The combination of InnoSwitch4-CZ with ClampZero greatly reduces system and primary switch losses, allowing for extremely high power densities. InnoSwitch4-CZ also incorporates multiple protection features including output overvoltage and over-current limiting, and over-temperature shutdown. Devices are available that support the common combinations of latching and auto-restart protection mode required by applications such as chargers, adapters, consumer electronics and industrial systems.

www.power.com May 2021 This Product is Covered by Patents and/or Pending Patent Applications. InnoSwitch4-CZ

D V BPP

BPP REGULATOR

LINE INTERFACE

CONTROL LOGIC From Secondary RECEIVER Contoller CONTROLLER

THERMAL SHUTDOWN

BPP SenseFET Power HSD Switch CONTROL DRIVER

PI-9263-121820

S HSD

Figure 3. Primary Controller Block Diagram.

FW SR BPS VOUT

REGULATOR VBPS VO BPSUV

DETECTOR

FW_VALLEY

HANDSHAKE /LATCH-OFF SECONDARY CONTROLLER LATCH FB INH VCTRL + COMP

INH FW_VALLEY VREF FluxLink SEC_REQ FEEDBACK DRIVER

TSMAX + COMP OSCILLATOR ICTRL tOFF /TIMER MIN tSECINHMAX

VIS

PI-9264-121820

GND IS

Figure 4. Secondary Controller Block Diagram.

Rev. F 05/21 www.power.com InnoSwitch4-CZ

Pin Functional Description

ISENSE (IS) Pin (Pin 1) Connection to the power supply return output terminals. An external current sense resistor should be connected between this and the GND pin. If current regulation is not required, this pin should be tied C to the GND pin. 4 C S C SECONDARY GROUND (GND) (Pin 2) C GND for the secondary IC. Note this is not the power supply output C S - GND due to the presence of the sense resistor between this and the ISENSE pin. S 4 S FEEDBACK (FB) Pin (Pin 3) Connection to an external resistor divider to set the power supply output voltage. 4 IS SECONDARY BYPASS (BPS) Pin (Pin 4) Connection point for an external bypass capacitor for the secondary IC supply. 1011 SYNCHRONOUS RECTIFIER DRIVE (SR) Pin (Pin 5) Gate driver for external SR FET. If no SR FET is used connect this pin Figure 5. Pin Configuration. to GND. OUTPUT VOLTAGE (VOUT) Pin (Pin 6) InnoSwitch4-CZ Functional Description Connected directly to the output voltage, to provide current for the The InnoSwitch4-CZ combines a high-voltage power switch, along controller on the secondary-side and provide secondary protection. with both primary-side and secondary-side controllers in one device. FORWARD (FWD) Pin (Pin 7) The connection point to the switching node of the transformer output The architecture incorporates a novel inductive coupling feedback winding providing information on primary switch timing. Provides power scheme (FluxLink) using the package lead frame and bond wires to for the secondary-side controller when V is below a threshold value. provide a safe, reliable, and cost-effective means to transmit OUT accurate, output voltage and current information from the secondary NC Pin (Pin 8-12) controller to the primary controller. Leave open. Should not be connected to any other pins. The primary controller on InnoSwitch4-CZ is a zero voltage switching UNDER/OVER INPUT VOLTAGE (V) Pin (Pin 13) (ZVS) flyback controller that has the ability to operate in continuous A high-voltage pin connected to the AC or DC side of the input bridge conduction mode (CCM), and discontinuous conduction mode (DCM) for detecting undervoltage and overvoltage conditions at the power with virtually no switching loss. The controller uses both variable supply input. This pin should be tied to GND to disable UV/OV frequency and variable current limit control scheme. The primary protection. controller consists of a frequency jitter oscillator, a receiver circuit PRIMARY BYPASS (BPP) Pin (Pin 14) magnetically coupled to the secondary controller, a current limit The connection point for an external bypass capacitor for the controller, 5 V regulator on the PRIMARY BYPASS pin, audible noise primary-side supply. This is also the ILIM selection pin for choosing reduction engine for light load operation, bypass overvoltage standard ILIM or ILIM+1. Must be connected to BP1 pin of Clamp detection circuit, a lossless input line sensing circuit, current limit Zero. selection circuitry, over-temperature protection, leading edge blanking and power switch. HSD Pin (Pin 15) High-side drive signal for active clamp. Must be connected to IN pin The InnoSwitch4-CZ secondary controller consists of a transmitter of ClampZero. circuit that is magnetically coupled to the primary receiver, a constant voltage (CV) and a constant current (CC) control circuit, a 4.5 V SOURCE (S) Pin (Pin 16-19) regulator on the SECONDARY BYPASS pin, synchronous rectifier FET These pins are the power switch source connection. It is also ground driver, QR mode circuit (for optimal ZVS in DCM operation), oscillator reference for primary BYPASS pin. and timing circuit, and numerous integrated protection features. DRAIN (D) Pin (Pin 24) Power switch drain connection. Figure 3 and Figure 4 show the functional block diagrams of the primary and secondary controller, highlighting the most important features.

www.power.com Rev. F 05/21 InnoSwitch4-CZ

Primary Controller 1.05 InnoSwitch4-CZ is a variable frequency controller allowing CCM/DCM operation for enhanced efficiency and extended output power 1.00 capability. PI-9094a-120320 LIM PRIMARY BYPASS Pin Regulator 0.95 The PRIMARY BYPASS pin has an internal regulator that charges the

PRIMARY BYPASS pin capacitor to VBPP by drawing current from the 0.90 DRAIN pin whenever the power switch is off. The PRIMARY BYPASS pin is the internal supply voltage node. When the power switch is on, 0.85 the device operates from the energy stored in the PRIMARY BYPASS Normalized I Normalized pin capacitor. 0.80 In addition, a shunt regulator clamps the PRIMARY BYPASS pin voltage to VSHUNT when current is provided to the PRIMARY BYPASS pin through an external resistor. This allows the InnoSwitch4-CZ to 0.75 be powered externally through a bias winding, decreasing the no-load 30 50 70 90 110 130 150 consumption to less than 30 mW in a 5 V output design. Steady-State Switching Frequency (kHz) Primary Bypass ILIM Programming Figure 6. Normalized Primary Current vs. Frequency. InnoSwitch4-CZ ICs allows the user to adjust current limit (ILIM) settings through the selection of the PRIMARY BYPASS pin capacitor Current Limit Operation value. A ceramic capacitor can be used. The primary-side controller has a current limit threshold ramp that is There are 2 selectable capacitor sizes – 0.47 mF and 4.7 mF for setting inversely proportional to the time from the end of the previous standard and increased ILIM settings respectively. primary switching cycle (i.e. from the time the primary switch turns off at the end of a switching cycle). Primary Bypass Undervoltage Threshold The PRIMARY BYPASS pin undervoltage circuitry disables the power This characteristic produces a primary current limit that increases as switch when the PRIMARY BYPASS pin voltage drops below ~4.5 V the switching frequency (load) increases (Figure 6). (V - V ) in steady-state operation. Once the PRIMARY BYPASS BPP BP(H) This algorithm enables the most efficient use of the primary switch pin voltage falls below this threshold, it must rise to VSHUNT to re-enable turn-on of the power switch. with the benefit that this algorithm responds to digital feedback information immediately when a feedback switching cycle request is Primary BYPASS Pin Overvoltage Function received. The PRIMARY BYPASS pin has an optional latching OV protection feature. A Zener diode in parallel with the resistor in series with the At full load, switching cycles have a maximum current approaching PRIMARY BYPASS pin capacitor is typically used to detect an 100% ILIM. This gradually reduces to 30% of the full current limit as overvoltage on the primary bias winding and activate the protection load decreases. Once 30% current limit is reached, there is no mechanism. In the event that the current into the PRIMARY BYPASS further reduction in current limit (since this is low enough to avoid pin exceeds I , the device will latch-off or disable the power switch audible noise). The time between switching cycles will continue to SD increase as load reduces. switching for a time tAR(OFF), after which time the controller will restart and attempt to return to regulation. Jitter VOUT OV protection is also included as an integrated feature on the The normalized current limit is modulated between 100% and 95% at a modulation frequency of f this results in a frequency jitter of ~7 kHz secondary controller (see Output Voltage Protection). M with average frequency of ~100 kHz. Over-Temperature Protection The thermal shutdown circuitry senses the primary switch die Auto-Restart In the event a fault condition occurs (such as an output overload, temperature. The threshold is set to TSD with either a hysteretic or latch-off response. output short-circuit, or external component/pin fault), the InnoSwitch4-CZ enters auto-restart (AR) or latches off. The latching Hysteretic response: If the die temperature rises above the threshold, condition is reset by bringing the PRIMARY BYPASS pin below ~ 3 V the power switch is disabled and remains disabled until the die or by going below the UNDER/OVER INPUT VOLTAGE pin UV (IUV-) temperature falls by TSD(H) at which point switching is re-enabled. A threshold. large amount of hysteresis is provided to prevent over-heating of the In auto-restart, switching of the power switch is disabled for t . PCB due to a continuous fault condition. AR(OFF) There are 2 ways to enter auto-restart: Latch-off response: If the die temperature rises above the threshold the power switch is disabled. The latching condition is reset by 1. Continuous secondary requests at above the overload detection frequency fOVL for longer than 82 ms (tAR). bringing the PRIMARY BYPASS pin below VBPP(RESET) or by going below 2. No requests for switching cycles from the secondary for > tAR(SK). the UNDER/OVER INPUT VOLTAGE pin UV (IUV-) threshold. The second is included to ensure that if communication is lost, the primary tries to restart. Although this should never be the case in normal operation, it can be useful when system ESD events (for example) causes a loss of communication due to noise disturbing the secondary controller. The issue is resolved when the primary restarts after an auto-restart off-time.

Rev. F 05/21 www.power.com InnoSwitch4-CZ

The auto-restart is reset as soon as an AC reset occurs. HSD Resistor Programmed Delay (tLLDL) SOA Protection 130 kW 80 ns In the event that there are two consecutive cycles where the ILIM is reached within ~500 ns (the blanking time + current limit delay time), 60 kW 100 ns the controller will skip 2.5 cycles or ~25 ms. This provides sufficient 30 kW 120 ns time for the transformer to reset with large capacitive loads without extending the start-up time. 15 kW 140 ns

Input Line Voltage Monitoring At input high-line/full load in DCM operation, the required amount The UNDER/OVER INPUT VOLTAGE pin is used for input undervoltage delay is a function of the drain node capacitance and the sum of and overvoltage sensing and protection. magnetizing and leakage inductance of transformer. The delay is pre-programmed to t ~430 ns. A sense resistor is tied between the high-voltage DC bulk capacitor HLDL after the bridge (or to the AC side of the bridge rectifier for fast AC This delay switches between tLLDL and tHLDL based on input line voltage reset) and the UNDER/OVER INPUT VOLTAGE pin to enable this information. When the UNDER/OVER VOLTAGE pin current rises functionality. This function can be disabled by shorting the UNDER/ above 53.75 mA, the delay becomes tHLDL and remains tHLDL until the OVER INPUT VOLTAGE pin to primary GND. current falls by 7.5 mA at which point tLLDL is enabled. Hysteresis is provided to ensure longer delay for high-line ZVS. At power-up, after the primary bypass capacitor is charged and the ILIM state is latched, and prior to switching, the state of the UNDER/ Primary-Secondary Handshake OVER INPUT VOLTAGE pin is checked to confirm that it is above the At start-up, the primary-side initially switches without any feedback brown-in and below the overvoltage shutdown thresholds. information (this is very similar to the operation of a standard TOPSwitch™, TinySwitch™ or LinkSwitch™ controllers). In normal operation, if the UNDER/OVER INPUT VOLTAGE pin current falls below the brown-out threshold and remains below brown-in for If no feedback signals are received during the auto-restart on-time longer than tUV-, the controller enters auto-restart. Switching will only (tAR), the primary goes into auto-restart mode. Under normal resume once the UNDER/OVER INPUT VOLTAGE pin current is above conditions, the secondary controller will power-up via the FORWARD the brown-in threshold. pin or from the OUTPUT VOLTAGE pin and take over control. From this point onwards the secondary controls switching. In the event that the UNDER/OVER INPUT VOLTAGE pin current is above the overvoltage threshold, the controller will also enter If the primary controller stops switching or does not respond to cycle auto-restart. Again, switching will only resume once the UNDER/ requests from the secondary during normal operation (when the OVER INPUT VOLTAGE pin current has returned to within its normal secondary has control), the handshake protocol is initiated to ensure operating range. that the secondary is ready to assume control once the primary begins to switch again. An additional handshake is also triggered if The input line UV/OV function makes use of a internal high-voltage the secondary detects that the primary is providing more cycles than MOSFET on the UNDER/OVER INPUT VOLTAGE pin to reduce power were requested. consumption. If the cycle off-time tOFF is greater than 50 ms, the internal high-voltage MOSFET will disconnect the external sense The most likely event that could require an additional handshake is resistor from the internal IC to eliminate current drawn through the when the primary stops switching as the result of a momentary line sense resistor. The line sensing function will activate again at the brown-out event. When the primary resumes operation, it will default beginning of the next switching cycle. to a start-up condition and attempt to detect handshake pulses from the secondary. HSD Operation When the primary controller receives a request from the secondary to If secondary does not detect that the primary responds to switching begin a conduction cycle the InnoSwitch4-CZ first sends a signal requests for 8 consecutive cycles, or if the secondary detects that the through the HSD pin to turn on the high-side switch in the ClampZero primary is switching without cycle requests for 4 or more consecutive cycles, the secondary controller will initiate a second handshake for a fixed time of tHSD. The amount of time required to build up energy in transformer for ZVS is a function of clamp capacitor and sequence. This provides additional protection against cross-conduction transformer leakage inductance. After this on-time, the InnoSwitch4-CZ of the SR FET while the primary is switching. This protection mode will wait for a programmed delay (see: HSD to ZVS Delay Programming) also prevents an output overvoltage condition in the event that the before turning on the main primary switch to begin a flyback primary is reset while the secondary is still in control. conduction cycle. Wait and Listen HSD to ZVS Delay Programming When the primary resumes switching after initial power-up recovery In order to successfully achieve zero voltage switching (ZVS), some from an input line voltage fault (UV or OV) or an auto-restart event, it delay is necessary between turn-off of the ClampZero switch and will assume control and require a successful handshake to relinquish conduction of the InnoSwitch4-CZ. At input low-line/full load in CCM control to the secondary controller. operation, the required amount delay is a function of the drain node As an additional safety measure the primary will pause for an capacitance and the leakage inductance present in the transformer. auto-restart on-time period, t (~82 ms), before switching. During To tune this delay t , a resistor must be placed between the HSD AR LLDL this “wait” time, the primary will “listen” for secondary requests. If it pin and the SOURCE pin. This resistor can program one of four sees two consecutive secondary requests, separated by ~30 ms, the delays. Centering this delay at the lowest point of the Drain voltage primary will infer secondary control and begin switching in slave is critical for optimizing ZVS operation. mode. If no pulses occurs during the tAR “wait” period, the primary will begin switching under primary control until handshake pulses are received.

www.power.com Rev. F 05/21 InnoSwitch4-CZ

Audible Noise Reduction Engine If the output voltage reaches regulation within the soft-start time The InnoSwitch4-CZ features an active audible noise reduction mode period, the frequency ramp is immediately aborted and the secondary whereby the controller (via a “frequency skipping” mode of operation) controller is permitted to go full frequency. This will allow the avoids the resonant band (where the mechanical structure of the controller to maintain regulation in the event of a sudden transient power supply is most likely to resonate − increasing noise amplitude) loading soon after regulation is achieved. The frequency ramp will between 7 kHz and 12 kHz – 143 ms and 83 ms. If a secondary only be aborted if quasi-resonant-detection programming has already controller switch request occurs within this time window from the last occurred. conduction cycle, the gate drive to the power switch is inhibited. Maximum Secondary Inhibit Period Secondary Controller Secondary requests to initiate primary switching are inhibited to maintain operation below maximum frequency and ensure minimum As shown in the block diagram in Figure 4, the IC is powered by a off-time. Besides these constraints, secondary-cycle requests are 4.5 V (V ) regulator which is supplied by either VOUT or FWD. The BPS also inhibited during the “ON” time cycle of the primary switch (time SECONDARY BYPASS pin is connected to an external decoupling between the cycle request and detection of FORWARD pin falling capacitor and fed internally from the regulator block. edge). The maximum time-out in the event that a FORWARD pin The FORWARD pin also connects to the negative edge detection falling edge is not detected after a cycle requested is ~30 ms. block used for both handshaking and timing to turn on the SR FET Output Voltage Protection connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The In the event that the sensed voltage on the FEEDBACK pin is 2% FORWARD pin voltage is used to determine when to turn off the higher than the regulation threshold, a bleed current of ~2.5 mA SR FET in discontinuous mode operation. This is when the voltage (3 mA max) is applied on the OUTPUT VOLTAGE pin (weak bleed). across the RDS(ON) of the SR FET drops below zero volts. This bleed current increases to ~200 mA (strong bleed) in the event In continuous conduction mode (CCM) the SR FET is turned off when that the FEEDBACK pin voltage is raised beyond ~10% of the internal the feedback pulse is sent to the primary to demand the next FEEDBACK pin reference voltage. The current sink on the OUTPUT switching cycle, providing excellent synchronous operation, free of VOLTAGE pin is intended to discharge the output voltage after any overlap for the FET turn-off. momentary overshoot events. The secondary does not relinquish control to the primary during this mode of operation. The mid-point of an external resistor divider network between the OUTPUT VOLTAGE and SECONDARY GROUND pins is tied to the If the voltage on the FEEDBACK pin is sensed to be 20% higher than FEEDBACK pin to regulate the output voltage. The internal voltage the regulation threshold, a command is sent to the primary to either latch-off or begin an auto-restart sequence (see Secondary Fault comparator reference voltage is VFB (1.265 V). Response in Feature Code Addendum). This integrated VOUT OVP can The external current sense resistor connected between ISENSE and be used independently from the primary sensed OVP or in conjunction. SECONDARY GROUND pins is used to regulate the output current in FEEDBACK Pin Short Detection constant current regulation mode. If the sensed FEEDBACK pin voltage is below VFB(OFF) at start-up, the Minimum Off-Time secondary controller will complete the handshake to take control of The secondary controller initiates a cycle request using the inductive- the primary complete tSS(RAMP) and will stop requesting cycles to initiate connection to the primary. The maximum frequency of secondary- auto-restart (no cycle requests made to primary for longer than tAR(SK) cycle requests is limited by a minimum cycle off-time of tOFF(MIN). second triggers auto-restart). This is in order to ensure that there is sufficient reset time after primary conduction to deliver energy to the load. During normal operation, the secondary will stop requesting pulses from the primary to initiate an auto-restart cycle when the FEEDBACK Maximum Switching Frequency pin voltage falls below the VFB(OFF) threshold. The deglitch filter on the The maximum switch-request frequency of the secondary controller protection mode is on for less than ~10 ms. By this mechanism, the is fSREQ. secondary will relinquish control after detecting that the FEEDBACK Frequency Soft-Start pin is shorted to ground. At start-up the primary controller is limited to a maximum switching Auto-Restart Thresholds frequency of fSW and 75% of the maximum programmed current limit The FEEDBACK pin includes a comparator to detect when the output at the switch-request frequency of 100 kHz. voltage falls below VFB(AR) of VFB, for a duration exceeding tFB(AR). The The secondary controller temporarily inhibits the FEEDBACK short secondary controller will relinquish control when this fault condition is sensed. This threshold is meant to limit the range of constant current protection threshold (VFB(OFF)) until the end of the soft-start timer ~10 ms. After hand-shake is completed the secondary controller (CC) operation. linearly ramps up the switching frequency from fSW to fSREQ over the SECONDARY BYPASS Pin Overvoltage Protection 10 ms time period. The InnoSwitch4-CZ secondary controller features SECONDARY BYPASS pin OV feature similar to PRIMARY BYPASS pin OV feature. In the event of a short-circuit or overload at start-up, the device will When the secondary is in control: in the event the SECONDARY move directly into CC (constant-current) mode. The device will go BYPASS pin current exceeds I (~7 mA) the secondary will send a into auto-restart (AR), if the output voltage does not rise above the BPS(SD) command to the primary to initiate an auto-restart off-time (t ) or V threshold before the expiration of the soft-start timer after AR(OFF) FB(AR) latch-off event (see Secondary Fault Response in Feature Code handshake has occurred. Addendum). The secondary controller enables the FEEDBACK pin-short protection Output Constant Current mode (V ) at the end of the soft-start time period. If the output FB(OFF) The InnoSwitch4-CZ regulates the output current through an external short maintains the FEEDBACK pin below the short-circuit threshold, current sense resistor between the ISENSE and SECONDARY the secondary will stop requesting pulses triggering an auto-restart cycle.

Rev. F 05/21 www.power.com InnoSwitch4-CZ

GROUND pins where the voltage generated across the resistor is ZVS Operation in DCM and CCM Operating Modes compared to an internal reference of ISV(TH) (~35 mV). If constant In order to improve conversion efficiency and eliminate switching current regulation is not required, the ISENSE pin must be tied to losses, the InnoSwitch4-CZ features a drive signal to the companion SECONDARY GROUND pin. Clamp Zero device as means to force the voltage across the primary power switch to zero before every conduction cycle. This mode of SR Disable Protection operation is automatically engaged in both DCM and CCM, In each cycle SR is only engaged if a set cycle was requested by the dramatically simplifying system design. In DCM, stress across the secondary controller and the negative edge is detected on the high-side clamp switch is minimized to control the timing of the FORWARD pin. In the event that the voltage on the ISENSE pin clamp-switch turn on. By restricting conduction cycles to the peak of exceeds approximately 3 times the CC threshold, the SR FET drive is the drain voltage ring, switching loss across the ClampZero switch is disabled until the surge current has diminished to nominal levels. minimized. SR Static Pull-Down To ensure that the SR gate is held low when the secondary is not in Rather than detecting the magnetizing ring peak on the primary-side, control, the SYNCHRONOUS RECTIFIER DRIVE pin has internal pull the valley voltage of the FORWARD pin voltage as it falls below the down circuit “ON” device to pull the pin low and reduce any voltage output voltage level is used to gate secondary requests to initiate the on the SR gate due to capacitive coupling from the FORWARD pin. switch “ON” cycle in the primary controller. Open SR Protection The secondary controller detects when the controller enters in In order to protect against an open SYNCHRONOUS RECTIFIER discontinuous-mode and opens secondary cycle request windows DRIVE pin system fault the secondary controller has a protection corresponding to maximum switching voltage across the primary mode to ensure the SYNCHRONOUS RECTIFIER DRIVE pin is power switch. connected to an external FET. If the external capacitance on the Secondary valley switching is enabled for 20 ms after DCM is SYNCHRONOUS RECTIFIER DRIVE pin is below 200 pF, the device will detected or when (Forward Pin) ring amplitude (pk-pk) >2 V. assume the SYNCHRONOUS RECTIFIER DRIVE pin is “open” and Afterwards, valley switching is disabled, at which point switching of there is no FET to drive. If the pin capacitance detected is above the active clamp switch may occur at any time a secondary request is 200 pF, the controller will assume an SR FET is connected. initiated. In the event the SYNCHRONOUS RECTIFIER DRIVE pin is detected to The secondary controller includes blanking of ~800 ns to prevent be open, the secondary controller will stop requesting pulses from false detection of the primary “ON” cycle when the FORWARD pin the primary to initiate auto-restart. rings below ground. If the SYNCHRONOUS RECTIFIER DRIVE pin is tied to ground at Unlike in InnoSwitch3 devices, the valley switching mode does not start-up, the SR drive function is disabled and the open play a direct role in initiating the turn-on of the primary-side power SYNCHRONOUS RECTIFIER DRIVE pin protection mode is also switch, instead the active clamp circuit creates the low VDS condition disabled. on the primary power switch necessary for the it to operate with ZVS.

Request Window PI-9095-121119

Output Voltage

FORWARD Pin Voltage

Primary VDS

Time

Figure 7. Intelligent Zero Voltage Switching.

www.power.com Rev. F 05/21 InnoSwitch4-CZ

Applications Example

C6 220 pF 250 VAC

C10 330 µF 1 FL2 25 V VOUT

C17 VR1 R14 R16 R3 100 nF SMBJ200A 150 kΩ 10 kΩ 2.00 MΩ 630 V 200 V D7 1% C12 1% BAV19WS C9 1/8 W 6.8 nF 220 pF 50 V C13 BR1 1 C11 µ 3KBP08M 3 100 V µ 1 F R4 330 F 50 V Ω 2.00 M D1 FL1 25 V 2 3 1% US1K-13-F R10 Ω C8 D2 10 R15 1% D3 330 pF ClampZero C4 BAV21WS-7-F 10 kΩ 22 µF 50 V U2 C19 1% 4 35 V 1/16 W CPZ1061M D 2.2 nF V12P10-M3/86A RTN 630 V 4 FL3 T1 Q1 R17 RM8 3 2 D4 AON6220 0.009 Ω L2 US1M-13-F 1% 18 mH HS S2

BP2 C15 C18 4 1 100 nF 1 µF D6 C14 50 V 100 V US1M-13-F 1 µF 25 V LS R18 3.09 kΩ R1 R2 S1 IN R8 1.3 MΩ 1.3 MΩ C2 1% 2 kΩ µ R11 C7 1% 1% 100 F VR2 R9 1% 400 V 47 Ω 47 Ω 2.2 µF 1/10 W 25 V MMSZ5243BT1G C1 BP1 330 nF 310 VAC C16 R5 4.7 µF 30 kΩ 50 V 3 4 1% L1 200 µH

2 1 SR BPS FB GND IS F1 D V FW 3.15 A CONTROL VOUT

L N AC S HSD BPP IN InnoSwitch4-CZ U1 INN4073C

C5 4.7 µF 50 V PI-9247-031821

Figure 8. Schematic 20 V / 3.25 A Notebook Adapter Power Supply.

The circuit shown in Figure 8 is a 20 V, 3.25 A single output power inductance of the transformer in the case of DCM operation. Ultrafast supply using INN4073C and CPZ1061M. This single output design is diodes D1 and D4 are used to divert the transformer current from the DOE Level 6 and EC CoC v5 compliant. body diode of ClampZero’s high-side switch to minimize the reverse recovery energy. A small delay is provided from the instant the Input fuse F1 isolates the circuit and provides protection from high-side switch turns off in order to achieve zero voltage switching component failure, and the common mode choke L1 and L2 with on the primary switch. This delay is programmable by different capacitor C1 attenuation for EMI. Bridge rectifier BR1 rectifies the AC resistor values of R5. Capacitor C19 will help reduce the voltage on line voltage and provides a full wave rectified DC across the filter the ClampZero IC (U2) to provide soft turn-on. capacitor C2. Y capacitor C6 connected between the power supply output and input helps to reduce common mode EMI. Capacitor C16 is used to provide local decoupling at the BP1 pin. Capacitor C15 provides the decoupling for BP2 pin. Diode D6 and Resistors R1 and R2 discharge capacitor C1 when the power supply is capacitor C18 form a bootstrap circuit to provide the bias for the disconnected from AC mains. high-side BP2 pin. This prevents high-side internal tap turn-on and One end of the transformer primary is connected to the rectified DC minimizes excess energy loss in drain-tap. Resistor R18 limits the bus; the other is connected to the drain terminal of the switch inside current flowing into the BP2 pin. the InnoSwitch4 IC (U1). Resistors R3 and R4 provide input voltage The InnoSwitch4 IC is self-starting, using an internal high-voltage sense protection for undervoltage and overvoltage conditions. current source to charge the PRIMARY BYPASS pin capacitor (C5) The primary clamp formed by diode D1 and capacitor C17 limits the when AC is first applied. During normal operation, the primary-side peak drain voltage of U1 at the instant of turn-off of the switch inside block is powered from an auxiliary winding on the transformer T1. U1. The energy stored in the leakage inductance of transformer T1 Output of the auxiliary (or bias) winding is rectified using diode D2 will be transferred to capacitor C17. Part of the magnetizing energy and filtered using capacitor C4. Resistor R8 limits the current being will also get transferred to C17 depending on the capacitance value supplied to the PRIMARY BYPASS pin of InnoSwitch4 IC (U1). used. VR1 is used to protect the InnoSwitch4 from excessive drain Output regulation is achieved using modulation control, where the voltages if there is any malfunction of the power supply. frequency and ILIM of switching cycles are adjusted based on the When the FluxLink signal is received from the secondary-side, the output load. At high load, most switching cycles are enabled for a InnoSwitch4 generates an HSD signal to turn on the ClampZero high value of ILIM in the selected ILIM range, and at light load or device. When the ClampZero IC (U2) turns on, to achieve soft no-load, most cycles are disabled, and the ones enabled have a low switching of the InnoSwitch4 primary switch, clamp capacitor C17 value of ILIM in the selected ILIM range. Once a cycle is enabled, starts to charge the leakage inductance of the transformer in the the switch remains on until the primary current ramps to the device case of CCM operation and both the leakage and the magnetizing current limit for the specific operating state.

Rev. F 05/21 www.power.com InnoSwitch4-CZ

The latch-off/auto-restart primary-side overvoltage protection is 2. Efficiency assumptions depend on power level. Smallest device obtained using Zener diode VR2 with current limiting resistor R9. In power level assumes efficiency >87% increasing to >92% for the a flyback converter, output of the auxiliary winding tracks the output largest device. voltage of the converter. In case of overvoltage at the output of the 3. Transformer primary inductance tolerance of ±7%. converter, the auxiliary winding voltage increases and causes 4. Reflected output voltage (VOR) is set to maintain KP = 0.7 at breakdown of VR2, which then causes a current to flow into the BPP minimum input voltage for universal line and KP = 1 for high input pin of InnoSwitch4 IC U1. If the current flowing into the BPP pin line designs (for thermally constrained environment efficiency increases above the ISD threshold, the U1 controller latches off to should be >92% with larger devices). prevent any further increase in output voltage. 5. Maximum conduction losses for adapters is limited to 0.6 W, 0.8 W for open frame designs. The secondary-side of the InnoSwitch4 IC provides output voltage, 6. Increased current limit is selected for peak and open frame power output current sensing, and drive to a MOSFET providing synchronous columns and standard current limit for adapter columns. rectification. The secondary of the transformer is rectified by SR FET 7. The part is board mounted with SOURCE pins soldered to a Q1/D3 and filtered by capacitors C10 and C11. Capacitor C13 is used sufficient area of copper and/or a heat sink to keep the SOURCE to reduce the high-frequency output voltage ripple. High-frequency pin temperature at or below 110 °C. ringing during switching transients that would otherwise create 8. Ambient temperature of 50 °C for open frame designs and 40 °C radiated EMI is reduced via RCD snubber R10, C9, and D7. Diode D7 for sealed adapters. minimizes the dissipation in resistor R10. 9. Below a value of 1, KP is the ratio of ripple to peak primary The gate of Q1 is turned on by the secondary-side controller of IC U1, current. To prevent reduced power delivery, due to premature based on the winding voltage sensed via resistor R11 and fed into the termination of switching cycles, a transient KP limit of ≥0.25 is

FWD pin of the IC. recommended. This prevents the initial current limit (IINT) from being exceeded at switch turn-on. In continuous conduction mode of operation, the SR MOSFET is turned off just prior to the secondary-side commanding a new Primary-Side Overvoltage Protection switching cycle from the primary. In discontinuous mode of operation, (Latch-Off/Auto-Restart Mode) the power MOSFET is turned off, when the voltage drop across the Primary-side output overvoltage protection provided by the InnoSwitch4-CZ IC uses an internal protection depending on H code MOSFET falls below a threshold of approximately VSR(TH). that is triggered by a threshold current of ISD into the PRIMARY The secondary side of the IC U1 is self-powered from either the BYPASS pin. In addition to an internal filter, the PRIMARY BYPASS pin secondary winding forward voltage or the output voltage. Capacitor capacitor forms an external filter helping noise immunity. For the C7 connected to the BPS pin of IC U1 provides decoupling for the bypass capacitor to be effective as a high frequency filter, the internal circuitry. capacitor should be located as close as possible to the SOURCE and PRIMARY BYPASS pins of the device. Below the constant current (CC) regulation threshold, the device operates in constant voltage mode. During constant voltage (CV) The primary sensed OVP function can be realized by connecting a mode operation, output voltage regulation is achieved through series combination of a Zener diode, a resistor and a blocking diode sensing the output voltage via divider resistors R14 and R15. The from the rectified and filtered bias winding voltage supply to the voltage across R15 is fed into the FEEDBACK pin with an internal PRIMARY BYPASS pin. The rectified and filtered bias winding output reference voltage threshold of 1.265 V. The output voltage is voltage may be higher than expected (up to 1.5X or 2X the desired regulated so as to achieve a voltage of 1.265 V on the FEEDBACK pin. value) due to poor coupling of the bias winding with the output Capacitor C8 provides noise filtering of the signal at the FEEDBACK pin. winding and the resulting ringing on the bias winding voltage waveform. It is therefore recommended that the rectified bias winding voltage During CC operation, when the output voltage falls, the device be measured. This measurement should be ideally done at the directly powers itself from the secondary winding. During the lowest input voltage and with highest load on the output. This on-time of the primary-side power switch, the forward voltage that measured voltage should be used to select the components required appears across the secondary winding is used to charge the to achieve primary sensed OVP. It is recommended that a Zener decoupling capacitor C7 via resistor R11 and an internal regulator. diode with a clamping voltage approximately 6 V lower than the bias This allows output current regulation to be maintained down to winding rectified voltage at which OVP is expected to be triggered be ~3.4 V. Output current is sensed by monitoring the voltage drop selected. A forward voltage drop of 1 V can be assumed for the across resistor R17 between the IS and SECONDARY GROUND pins. blocking diode. A small signal standard recovery diode is A threshold of approximately 35 mV reduces losses. C14 provides recommended. The blocking diode prevents any reverse current filtering on the IS pin from external noise. Once the internal current discharging the bias capacitor during start-up. Finally, the value of sense threshold is exceeded, the device regulates the number of the series resistor required can be calculated such that a current switch pulses to maintain a fixed output current. higher than ISD will flow into the PRIMARY BYPASS pin during an output overvoltage. Key Application Considerations Reducing No-Load Consumption Output Power Table The InnoSwitch-4 IC can start in self-powered mode, drawing energy The data sheet output power table (Table 1) represents the maximum from the BYPASS pin capacitor charged through an internal current practical continuous output power level that can be obtained under source. Internal current source also charges the BP1 pin decoupling the following conditions: capacitor of the ClampZero device at start up. Use of a bias winding, however, is required to provide supply current to the PRIMARY 1. The minimum DC input voltage is 90 V or higher for 85 VAC input, BYPASS pin, once the InnoSwitch-4 IC has started switching. An 220 V or higher for 230 VAC input or 115 VAC with a voltage- auxiliary (bias) winding provided on the transformer serves this doubler. Input capacitor voltage should be sized to meet these purpose. A bias winding driver supply to the PRIMARY BYPASS pin criteria for AC input designs. enables design of power supplies with no-load power consumption

9 www.power.com Rev. F 05/21 InnoSwitch4-CZ less than 30 mW. The high-side BP2 pin decoupling capacitor of the diode with low junction capacitance is recommended to avoid the ClampZero device draws energy from the internal current source of snappy recovery typically seen with fast or ultrafast diodes that can ClampZero device, once the power supply starts switching. Resistor lead to higher radiated EMI. R8 shown in Figure 8 should be adjusted to achieve the lowest An aluminum capacitor of at least 22 mF with a voltage rating 1.2 no-load input power. times greater than the highest voltage developed across the capacitor Secondary-Side Overvoltage Protection (Auto-Restart Mode) is recommended. Highest voltage is typically developed across this The secondary-side output overvoltage protection provided by the capacitor when the supply is operated at the highest rated output InnoSwitch4-CZ IC uses an internal auto restart circuit that is voltage and load with the lowest input AC supply voltage. triggered by an input current exceeding a threshold of I into the BPS(SD) Line UV and OV Protection SECONDARY BYPASS pin. The direct output sensed OVP function can Resistors connected from the UNDER/OVER INPUT VOLTAGE pin to be realized by connecting a Zener diode from the output to the the DC bus enable sensing of input voltage to provide line SECONDARY BYPASS pin. The Zener diode voltage needs to be the undervoltage and overvoltage protection. For a typical universal difference between 1.25 × V and 4.5 V − the SECONDARY BYPASS OUT input application, a resistor value of 4 MW is recommended. Figure 14 pin voltage. It is necessary to add a low value resistor in series with shows circuit configurations that only enable either the line UV or the the OVP Zener diode to limit the maximum current into the line OV feature. SECONDARY BYPASS pin. InnoSwitch4-CZ features a primary sensed OV protection feature that Selection of Components can be used to latch-off the power supply. Once the power supply is latched off, it can be reset if the UNDER/OVER INPUT VOLTAGE pin Components for InnoSwitch4-CZ current is reduced to zero. Once the power supply is latched off, Primary-Side Circuit even after the input supply is turned off, it can take considerable amount of time to reset the InnoSwitch4-CZ controller as the energy BPP Capacitor stored in the DC bus will continue to provide current to the controller. A capacitor connected from the PRIMARY BYPASS pin of the A fast AC reset can be achieved using the modified circuit configuration InnoSwitch4-CZ IC to GND provides decoupling for the primary-side shown in Figure 15. The voltage across capacitor C5 reduces rapidly controller and also selects current limit. A 0.47 mF or 4.7 mF capacitor after input supply is disconnected reducing current into the INPUT may be used. Though electrolytic capacitors can be used, often VOLTAGE MONITOR pin of the InnoSwitch4-CZ IC and resetting the surface mount multi-layer ceramic capacitors are preferred for use on InnoSwitch4-CZ controller. double sided boards as they enable placement of capacitors close to the IC. Their small size also makes it ideal for compact power supplies. Primary Sensed OVP (Overvoltage Protection) At least 10 V, 0805 or larger size rated X5R or X7R dielectric capacitors The voltage developed across the output of the bias winding tracks are recommended to ensure that minimum capacitance requirements the power supply output voltage. Though not precise, a reasonably are met. The ceramic capacitor type designations, such as X7R, X5R accurate detection of the amplitude of the output voltage can be from different manufacturers or different product families do not have achieved by the primary-side controller using the bias winding the same voltage coefficients. It is recommended that capacitor voltage. A Zener diode connected from the bias winding output to datasheets be reviewed to ensure that the selected capacitor will not the PRIMARY BYPASS pin can reliably detect a secondary overvoltage have more than 20% drop in capacitance at 5 V. Do not use Y5U or fault and cause the primary-side controller to latch-off/auto-restart Z5U / 0603 rated MLCC due to this type of SMD ceramic capacitor has depending on feature code. It is recommended that the highest very poor voltage and temperature coefficient characteristics. voltage at the output of the bias winding should be measured for normal steady-state conditions (at full load and lowest input voltage) Bias Winding and External Bias Circuit and also under transient load conditions. A Zener diode rated for The internal regulator connected from the DRAIN pin of the switch to 1.25 times this measured voltage will typically ensure that OVP the PRIMARY BYPASS pin of the InnoSwitch4-CZ primary-side protection will only operate in case of a fault. controller charges the capacitor connected to the PRIMARY BYPASS pin to achieve start-up. A bias winding should be provided on the Primary-Side Clamp transformer with a suitable rectifier and filter capacitor to create a Clamp Zero IC is used to provide soft switching at turn-on of the bias supply that can be used to supply at least 4 mA of current to the Innoswitch4-CZ primary switch as shown in Figure 8. Clamp capacitor PRIMARY BYPASS pin clamp BP1 and BP2 pins. C17 stores the leakage energy when the primary switch is turned off and delivers the stored leakage energy to the secondary when the The turns ratio for the bias winding should be selected such that 7 V clamp Zero device turns on while simultaneously charging up the to 8 V minimum is developed across the bias winding at the lowest leakage inductance in reverse direction in CCM operation and charges rated output voltage of the power supply at the lowest load condition. both leakage and magnetizing inductance in reverse direction during If the voltage is lower than this, no-load input power will increase. DCM operation. This prevents the excess voltage spike at the drain In USB PD or rapid charge applications, the output voltage range is during the primary switch turn off on a cycle by cycle basis. VR1 is very wide. For example, a 45 W adapter would need to support 5 V, used across the clamp capacitor just to provide backup protection in 9 V and 15 V and a 100 W adapter would have output voltages case ClampZero IC stops switching due to any circuit fault condition. selectable from 5 V to 20 V. Such a wide output voltage variation It is recommended to choose the value of the clamp capacitor such results in a large change in bias winding output voltage as well. that ~0.25 times the resonant period of the CCLAMP and LLKG equals the A linear regulator circuit is generally required to limit the current HSD pulse width for CCM designs, and ~0.5 times the resonant injected into the PRIMARY BYPASS pin of the InnoSwitch4-CZ. period of the CCLAMP and LLKG equals the HSD pulse width in the case of DCM-only designs. Capacitance in the range of 10 nF to 100 nF may The bias current from the external circuit should be set to max of IS1 for be used depending on the design. At least 200 V, 1206 or larger size InnoSwitch4-CZ + max of IS1(I) for ClampZero to achieve lowest no-load power consumption when operating the power supply at 230 VAC rated X7R dielectric capacitors are recommended. input, (VBPP > 5 V). A glass passivated standard recovery rectifier

Rev. F 05/21 www.power.com InnoSwitch4-CZ

For CCM designs r HSDPulse Width ` LCLKGCLAMP 2 For DCM designs

HSDPulse WidthL+ r LKGCC LAMP

Components for InnoSwitch4-CZ Secondary-Side Circuit SECONDARY BYPASS Pin – Decoupling Capacitor S A 2.2 mF, 10 V / X7R or X5R / 0805 or larger size multi-layer ceramic capacitor should be used for decoupling the SECONDARY BYPASS pin of the InnoSwitch4-CZ IC. Since the SECONDARY BYPASS pin voltage needs to be 4.5 V before the output voltage reaches the regulation voltage level, a significantly higher BPS capacitor value could lead to 20511 output voltage overshoot during start-up. Values lower than 1.5 mF may not offer enough capacitance, and cause unpredictable operation. Figure 10. Unacceptable FORWARD Pin Waveform After Handshake with SR The capacitor must be located adjacent to the IC pins. At least 10 V Switch Conduction During Flyback Cycle. is recommended voltage rating to give enough margin from BPS voltage, and 0805 size is necessary to guarantee the actual value in operation since the capacitance of ceramic capacitors drops significantly with applied DC voltage especially with small package SMD such as 0603. 6.3 V / 0603 / X5U or Z5U type of MLCC is not recommended for this reason. The ceramic capacitor type designations, such as X7R, X5R from different manufacturers or different product families do not have the same voltage coefficients. It is recommended that capacitor datasheets be reviewed to ensure that the selected capacitor will not have more than 20% drop in capacitance at 4.5 V. Capacitors with X5R or X7R dielectrics should be used for best results. S When the output voltage of the power supply is 5 V or higher, the supply current for the secondary-side controller is provided by the OUTPUT VOLTAGE (VOUT) pin of the IC as the voltage at this pin is higher than the SECONDARY BYPASS pin voltage. During start-up and operating conditions where the output voltage of the power 0511 supply is below 5 V, the secondary-side controller is supplied by current from an internal current source connected to the FORWARD Figure 11. Acceptable FORWARD Pin Waveform After Handshake with SR Switch Conduction During Flyback Cycle. pin. If the output voltage of the power supply is below 5 V and the load at the output of the power supply is very light, the operating frequency can drop significantly and the current supplied to the secondary-side controller from the FORWARD pin may not be sufficient to maintain the SECONDARY BYPASS pin voltage at 4.5 V. For such applications, it is recommended that an additional active preload be used as shown in Figure 9. This load is turned on by the interface IC (or USB PD controller) when the output voltage of the power supply is below 5 V. S

VOUT

To USB PD Controller GP10 t t 0511 PI-8414-082317 Figure 12. Unacceptable FORWARD Pin Waveform Before Handshake with Body Diode Conduction During Flyback Cycle. Figure 9. Active Pre-Load Circuit. Note: If t + t = 1.5 ms ± 50 ns, the controller may fail the handshake and FORWARD Pin Resistor 1 2 trigger a primary bias winding OVP latch-off/auto-restart. A 47 W, 5% resistor is recommended to ensure sufficient IC supply current. A higher or lower resistor value should not be used as it can affect device operation such as the timing of the synchronous rectifier drive. Figures 10, 11, 12 and 13 below show examples of unacceptable and acceptable FORWARD pin voltage waveforms. VD is forward voltage drop across the SR.

www.power.com Rev. F 05/21 InnoSwitch4-CZ

the range of 10 W to 47 W may be used (higher resistance values lead to noticeable drop in efficiency). A capacitance value of 220 pF to 2.2 nF is adequate for most designs. Output Capacitor Low ESR aluminum electrolytic capacitors are suitable for use with most high frequency flyback switching power supplies though the use of aluminum-polymer solid capacitors have gained considerable S popularity due to their compact size, stable temperature characteristics, extremely low ESR and high RMS ripple current rating. These capacitors enable the design of ultra-compact chargers and adapters. Typically, 200 mF to 300 mF of aluminum-polymer capacitance per ampere of output current is adequate. The other factor that influences choice of the capacitance is the output ripple. Ensure that capacitors with a voltage rating higher than the highest output voltage plus 0511 sufficient margin be used. Output Voltage Feedback Circuit Figure 13. Acceptable FORWARD Pin Waveform Before Handshake with Body Diode Conduction During Flyback Cycle. The output voltage FEEDBACK pin voltage is 1.265 V [VFB]. A voltage divider network should be connected at the output of the power SR FET Operation and Selection supply to divide the output voltage such that the voltage at the Although a simple diode rectifier and filter works for the output, use FEEDBACK pin will be 1.265 V when the output is at its desired of an SR FET enables the significant improvement in operating voltage. The lower feedback divider resistor should be tied to the efficiency often necessary to meet the European CoC and the U.S. SECONDARY GROUND pin. A 300 pF (or smaller) decoupling DoE energy efficiency requirements. The secondary-side controller capacitor should be connected at the FEEDBACK pin to the turns on the SR FET once the flyback cycle begins. The SR FET gate SECONDARY GROUND pin of the InnoSwitch4-CZ IC. This capacitor should be tied directly to the SYNCHRONOUS RECTIFIER DRIVE pin should be placed close to the InnoSwitch4-CZ IC. of the InnoSwitch4-CZ IC (no additional resistors should be connected in the gate circuit of the SR FET). The SR FET is turned off once the

VDS of the SR FET reaches 0 V. + A FET with 18 mW RDS(ON) is appropriate for a 5 V, 2 A output, and a R1 1N4148 FET with 8 mW RDS(ON) is suitable for designs rated with a 12 V, 3 A output. The SR FET driver uses the SECONDARY BYPASS pin for its supply rail, and this voltage is typically 4.5 V. A FET with a high R2 threshold voltage is therefore not suitable; FETs with a threshold GND voltage of 1.5 V to 2.5 V are ideal although switches with a threshold D V FWD SR BPS FB voltage (absolute maximum) as high as 4 V may be used provided VOUT their data sheets specify RDS(ON) across temperature for a gate voltage of 4.5 V. S BPP IS A schottky diode is recommended across the SR FET. Since the SR InnoSwitch4-CZ FET gate turns off during the ClampZero switch conduction period, there will be energy transfer to secondary during this period typically (a) PI-8405c-121820 about 500 ns. In addition to this there is a slight delay between the commencement of the flyback cycle and the turn-on of the SR FET. During this time, the body diode of the SR FET conducts. If an + external parallel Schottky diode is used, this current mostly flows R1 through the Schottky diode. Once the InnoSwitch4-CZ IC detects end of the flyback cycle, voltage across SR FET RDS(ON) reaches 0 V, any remaining portion of the flyback cycle is completed with the R2 current commutating to the body diode of the SR FET or the external parallel Schottky diode. Use of the Schottky diode parallel to the SR GND D V FWD SR BPS FB FET may provide higher efficiency, and typically a 1 A surface mount 6.2 V Schottky diode is adequate. However, the gains are modest. An VOUT efficiency increase of 0.2% or higher is expected with the addition of Schottky diode for designing with an output current rating >2 A. S BPP IS The voltage rating of the Schottky diode and the SR FET should be at InnoSwitch4-CZ least 1.4 times the expected peak inverse voltage (PIV) based on the turns ratio used for the transformer. 60 V rated FETs and diodes are (b) PI-8406c-121820 suitable for most 5 V designs that use a VOR < 60 V, and 100 V rated FETs and diodes are suitable for 12 V designs. Figure 14. (a) Line OV Only; (b) Line UV Only. The interaction between the leakage reactance of the output windings and the SR FET capacitance (C ) leads to ringing on the Output Overload Protection OSS For output voltage below the V threshold, the InnoSwitch4-CZ IC voltage waveform at the instance of voltage reversal at the winding PK due to primary switch turn-on. This ringing can be suppressed using will limit the output current once the voltage across the IS and GND pins exceeds the current limit or I threshold. This provides an RC snubber connected across the SR FET. A snubber resistor in SV(TH)

Rev. F 05/21 www.power.com InnoSwitch4-CZ

VBUS

ClampZero

RTN SR BPS FB GND IS D V FW InnoSwitch4-CZ VOUT Primary Switch and Controller

S HSD BPP Secondary Control IC

PI-9266b-123020

Figure 15. Fast AC Reset Configuration. current limited or constant current operation. The current limit is set maximized for good heat sinking without compromising EMI by the programming resistor between the ISENSE and SECONDARY performance. Similarly for the output SR switch, maximize the PCB area connected to the pins on the package through which heat is GROUND pins. For any output voltage above the VPK threshold, InnoSwitch4-CZ IC will provide a constant power characteristic. An dissipated from the SR switch. increase in load current will result in a drop in output voltage such Sufficient copper area should be provided on the board to keep the that the product of output voltage and current equals the maximum IC temperature safely below the absolute maximum limits. It is power set by the product of V and set current limit. PK recommended that the copper area provided for the copper plane on Interfacing with USB PD and Rapid Charge Controllers which the SOURCE pin of the IC is soldered is sufficiently large to A micro controller can be used to alter the feedback voltage divider in keep the IC temperature below 110 °C when operating the power order to increase or decrease the output voltage. The interface IC supply at full rated load and at the lowest rated input AC supply voltage. can also use the signal from the InnoSwitch4-CZ ISENSE pin to sense Y Capacitor output current and provide current, power limiting or protection The Y capacitor should be placed directly between the primary input features. filter capacitor positive terminal and the output positive or return Recommendations for Circuit Board Layout terminal of the transformer secondary. This routes high amplitude common mode surge currents away from the IC. Note – if an input See Figure 16 and Figure 17 for a recommended circuit board layout pi-filter (C, L, C) EMI filter is used then the inductor in the filter should for an InnoSwitch4-CZ based power supply. be placed between the negative terminals of the input filter capacitors. Single-Point Grounding Output SR Switch Use a single-point ground connection from the input filter capacitor to For best performance, the area of the loop connecting the secondary the area of copper connected to the SOURCE pins. winding, the output SR switch and the output filter capacitor, should Bypass Capacitors be minimized. The PRIMARY BYPASS and SECONDARY BYPASS pin capacitor must ESD be located directly adjacent to the PRIMARY BYPASS-SOURCE and Sufficient clearance should be maintained (>8 mm) between the SECONDARY BYPASS-SECONDARY GROUND pins respectively and primary-side and secondary-side circuits to enable easy compliance connections to these capacitors should be routed with short traces. with any ESD / HIPOT requirements. Primary Loop Area The spark gap is best placed directly between output positive rail and The area of the primary loop that connects the input filter capacitor, one of the AC inputs. In this configuration a 6.2 mm spark gap is transformer primary and IC should be kept as small as possible. often sufficient to meet the creepage and clearance requirements of Primary Clamp Circuit many applicable safety standards. This is less than the primary to Active clamp is used to achieve the ZVS turn-on on the primary secondary spacing because the voltage across spark gap does not switch and to limit the peak voltage on the drain pin at turn-off. exceed the peak of the AC input. ClampZero IC is used along with clamp capacitor to achieve this. To Drain Node reduce EMI, minimize the loop from the clamp components to the The drain switching node is the dominant noise generator. As such transformer and Innoswitch4-CZ. the components connected the drain node should be placed close to Thermal Considerations the IC and away from sensitive feedback circuits. The clamp circuit The SOURCE pin is internally connected to the IC lead frame and components should be located physically away from the PRIMARY provides the main path to remove heat from the device. Therefore BYPASS pin and trace lengths minimized. the SOURCE pin should be connected to a copper area underneath The loop area of the loop comprising of the input rectifier filter the IC to act not only as a single point ground, but also as a heat capacitor, the primary winding and the IC primary-side switch should sink. As this area is connected to the quiet source node, it can be be kept as small as possible.

www.power.com Rev. F 05/21 InnoSwitch4-CZ

Layout Example

Y capacitor connection to the plus bulk rail on the primary-side for surge protection.

Maximize source copper area for good heat sinking.

Figure 16. PCB Layout Top Side.

Place clamp components close to Keep InnoSwitch4 switching Bulk capacitor, Transformer and loop area and ClampZero Place BPP and BPS InnoSwitch4 drain. switching loop area short. capacitors near the 6.2 mm Spark Gap for ESD. InnoSwitch4 IC.

Keep IS-GND pin sense resistor close to output capacitor and output connector full stop.

Keep IS-GND pin decoupling capacitor close to the Innoswitch4 IC.

Keep FEEDBACK pin decoupling capacitor close to the InnoSwitch4 IC.

Keep output SF FET and output filter capacitor loop short.

Maximize drain area of SR FET for good heat sinking.

Place BP1 and BP2 Maximize source copper In order to increase ESD Place Vpin sense resistors decoupling caps close area for good heat sinking. immunity and to meet isolation close to the InnoSwitch4 IC. to the ClampZero IC. requirements, no traces are routed beneath the IC.

Figure 17. PCB Layout Bottom Side.

Rev. F 05/21 www.power.com InnoSwitch4-CZ

Recommendations for EMI Reduction 3. Higher VOR increases leakage inductance which reduces power supply efficiency. 1. Appropriate component placement and small loop areas of the 4. Higher V increases peak and RMS current on the secondary-side primary and secondary power circuits help minimize radiated and OR which may increase secondary-side copper and diode losses. conducted EMI. Care should be taken to achieve a compact loop area. There are some exceptions to this. For very high output currents the

2. A small capacitor in parallel to the clamp diode on the primary- VOR should be reduced to get highest efficiency. For output voltages

side can help reduce radiated EMI. above 15 V, VOR should be higher to maintain an acceptable PIV across 3. A resistor in series with the bias winding helps reduce radiated EMI. the output synchronous rectifier. 4. Common mode chokes are typically required at the input of the Ripple to Peak Current Ratio, K power supply to sufficiently attenuate common mode noise. P A KP below 1 indicates continuous conduction mode, where KP is the However, the same performance can be achieved by using shield ratio of ripple-current to peak-primary-current (Figure 19). windings on the transformer. Shield windings can also be used in

conjunction with common mode filter inductors at input to KP ≡ KRP = IR / IP improve conducted and radiated EMI margins. A value of K higher than 1, indicates discontinuous conduction mode 5. Adjusting SR switch RC snubber component values can help P (Figure 18) .In this case KP is the ratio of primary switch off-time to reduce high frequency radiated and conducted EMI. the secondary diode conduction-time. 6. A pi-filter comprising differential inductors and capacitors can be K K = (1 – D) x T/ t = V × (1 – D ) / ((V – V ) × D ) used in the input rectifier circuit to reduce low frequency P ≡ DP OR MAX MIN DS MAX differential EMI. It is recommended that a KP close to 0.7 at the minimum expected DC 7. A 1 mF ceramic capacitor connected at the output of the power bus voltage should be used for most InnoSwitch4-CZ designs. Since supply helps to reduce radiated EMI. InnoSwitch4-CZ provides ZVS benefit a KP value of <1 results in lower Recommendations for Transformer Design primary-side switch losses and higher transformer efficiency by lowering the primary RMS current. Transformer design must ensure that the power supply delivers the For a typical USB PD and rapid charge designs which require a wide rated power at the lowest input voltage. The lowest voltage on the output voltage range, K will change significantly as the output rectified DC bus depends on the capacitance of the filter capacitor P voltage changes. K will be high for high output voltage conditions used. At least 2 mF/W is recommended to always keep the DC bus P and will drop as the output voltage is lowered. The PIXls spreadsheet voltage above 70 V, though 3 mF/W provides sufficient margin. The can be used to effectively optimize selection of K , inductance of the ripple on the DC bus should be measured to confirm the design P primary winding, transformer turns ratio, and the operating frequency calculations for transformer primary-winding inductance selection. while ensuring appropriate design margins. Switching Frequency (f ) SW Core Type It is a unique feature in InnoSwitch4-CZ that for full load, the designer Choice of a suitable core is dependent on the physical limits of the can set the switching frequency to between 50 kHz to 140 kHz. For power supply enclosure. It is recommended that only cores with low a smaller transformer, the full load switching frequency could be set loss be used to reduce thermal challenges. to 130 kHz. When setting the full load switching frequency it is important to consider primary inductance and peak current tolerances Safety Margin, M (mm) to ensure that average switching frequency does not exceed 140 kHz For designs that require safety isolation between primary and which may trigger auto-restart due to overload protection. secondary that are not using triple insulated wire, the width of the safety margin to be used on each side of the bobbin is important. Reflected Output Voltage, V (V) OR For universal input designs a total margin of 6.2 mm is typically This parameter describes the effect on the primary switch drain required − 3.1 mm being used on either side of the winding. For voltage of the secondary-winding voltage during diode/SR conduction vertical bobbins the margin may not be symmetrical. However if a which is reflected back to the primary through the turns ratio of the total margin of 6.2 mm is required then the physical margin can be transformer. To make full use of ZVS capability and ensure flattest placed on only one side of the bobbin. For designs using triple efficiency over line/load, set reflected output voltage (V ) to OR insulated wire it may still be necessary to add a small margin in order maintain K = 0.7 at minimum input voltage for universal input and P to meet required creepage distances. Many bobbins exist for each K = 1 for high-line-only conditions. P core size and each will have different mechanical spacing. Refer to Consider the following for design optimization: the bobbin data sheet or seek guidance to determine what specific margin is required. As the margin reduces the available area for the 1. Higher V allows increased power delivery at V , which OR MIN windings, the winding area will disproportionately reduce for small minimizes the value of the input capacitor and maximizes power core sizes. delivery from a given InnoSwitch4-CZ device.

2. Higher VOR reduces the voltage stress on the output diodes and It is recommended that for compact power supply designs using an SR switches. InnoSwitch4-CZ IC, triple insulated wire should be used.

www.power.com Rev. F 05/21 InnoSwitch4-CZ

Primary Layers, L for low power designs as this typically increases common mode noise Primary layers should be in the range of 1 ≤ L ≤ 3 and in general and adds cost to the input filtering. should be the lowest number that meets the primary current density Maximum Operating Flux Density, B (Gauss) limit (CMA). A value of ≥200 Cmils / Amp can be used as a starting M A maximum value of 3800 gauss at the peak device current limit point for most designs. Higher values may be required due to (at 180 kHz) is recommended to limit the peak flux density at start-up thermal constraints. For universal input designs minimum 2% leakage and under output short-circuit conditions. Under these conditions the inductance is required to achieve ZVS during CCM operation. However output voltage is low and little reset of the transformer occurs during for DCM only designs it is recommended to minimize leakage the switch off-time. This allows the transformer flux density to inductance. Designs with more than 3 layers are possible but the staircase beyond the normal operating level. A value of 3800 gauss increased leakage inductance and the physical fit of the windings at the peak current limit of the selected device together with the should be considered. A split primary construction may be helpful for built-in protection features of InnoSwitch4-CZ IC provide sufficient DCM only designs. In split primary construction, half of the primary margin to prevent core saturation under start-up or output short- winding is placed on either side of the secondary (and bias) winding circuit conditions. in a sandwich arrangement. This arrangement is often disadvantageous

]gID- # T PD==P KK t T = 1 fS

VDS_PRI(MAIN)

ID_PRI(MAIN)

D × T (I–D) × T

ISEC

tHLDL-DHSD(OFF)*

tHSD PI-9267a-122420

Figure 18. Discontinuous Conduction Mode Current Waveform at High-Line, KP > 1. *DHSD(OFF) is delay from HSD low to ClampZero OFF, please refer to ClampZero data sheet.

IR KKPR==P IP VDS_PRI(MAIN)

ID_PRI(MAIN) IP IR

ISEC

tLLDL-DHSD(OFF)*

tHSD PI-9268a-122420

Figure 19. Continuous Conduction Mode Current Waveform at Low-Line, KP < 1. *DHSD(OFF) is delay from HSD low to ClampZero OFF, please refer to ClampZero data sheet.

Rev. F 05/21 www.power.com InnoSwitch4-CZ

Transformer Primary Inductance, (LP) Design Considerations When Using PowiGaN Once the lowest operating input voltage, switching frequency at full Devices load, and required VOR are determined, the transformers primary inductance can be calculated. The PIXls design spreadsheet can be For a flyback converter configuration, typical voltage waveform at the used to assist in designing the transformer. DRAIN pin of the IC is shown in Figure 20.

Quick Design Checklist VOR is the reflected output voltage across the primary winding when

the secondary is conducting. VBUS is the DC voltage connected to one As with any power supply, the operation of all InnoSwitch4-CZ end of the transformer primary winding. designs should be verified on the bench to make sure that component limits are not exceeded under worst-case conditions. In addition to VBUS+VOR, the drain also sees a large voltage spike at turn off that is caused by the energy stored in the leakage inductance As a minimum, the following tests are strongly recommended: of the primary winding. To keep the drain voltage from exceeding the 1. Maximum Drain Voltage – Verify that V of InnoSwitch4-CZ and DS rated maximum continuous drain voltage, a clamp circuit is needed SR FET do not exceed 90% of breakdown voltages at the highest across the primary winding. The forward recovery of the clamp diode input voltage and peak (overload) output power in normal will add a spike at the instant of turn-OFF of the primary switch. VCLM operation and during start-up. in Figure 20 is the combined clamp voltage including the spike. The 2. Maximum Drain Current – At maximum ambient temperature, peak drain voltage of the primary switch is the total of V , V and V . maximum input voltage and peak output (overload) power. BUS OR CLM

Review drain current waveforms for any signs of transformer VOR and the clamp voltage VCLM should be selected such that the peak saturation or excessive leading-edge current spikes at start-up. drain voltage is lower than 650 V for all normal operating conditions. Repeat tests under steady-state conditions and verify that the This provides sufficient margin to ensure that occasional increase in voltage during line transients such as line surges will maintain the leading edge current spike is below ILIMIT(MIN) at the end of tLEB(MIN). Under all conditions, the maximum drain current for the primary peak drain voltage well below 750 V under abnormal transient switch should be below the specified absolute maximum ratings. operating conditions. This ensures excellent long term reliability and 3. Thermal Check – At specified maximum output power, minimum design margin. input voltage and maximum ambient temperature, verify that To make full use of ZVS capability and ensure flattest efficiency over temperature specification limits for InnoSwitch4-CZ IC, line/load, set reflected output voltage (VOR) to maintain K = 0.7 at transformer, output SR FET, and output capacitors are not P minimum input voltage for universal input and KP ≥ 1 for high-line- exceeded. Enough thermal margin should be allowed for only conditions.

part-to-part variation of the RDS(ON) of the InnoSwitch4-CZ IC. Under low-line, maximum power, a maximum InnoSwitch4-CZ Consider the following for design optimization: SOURCE pin temperature of 110 °C is recommended to allow for 1. Higher VOR allows increased power delivery at VMIN, which these variations. minimizes the value of the input capacitor and maximizes power delivery from a given PowiGaN device.

2. Higher VOR reduces the voltage stress on the output diodes and SR FETs.

3. Higher VOR increases leakage inductance which reduces power supply efficiency.

4. Higher VOR increases peak and RMS current on the secondary-side which may increase secondary-side copper and diode losses.

750 V = VMAX(NON-REPETITIVE) Safe Surge Voltage Typical margin (150 V) Region (SSVR) gives de-rating of >80% 650 V = VMAX(CONTINUOUS)

VCLM

VOR

380 VDC

VBUS

Primary Switch Voltage Stress (264 VAC) PI-8769d-120320

Figure 20. Peak Drain Voltage for 264 VAC Input Voltage.

www.power.com Rev. F 05/21 InnoSwitch4-CZ

There are some exceptions to this. For very high output currents the VOR should be reduced to get highest efficiency. For output voltages above 15 V, VOR should be maintained higher to maintain an acceptable PIV across the output synchronous rectifier.

VOR choice will affect the operating efficiency and should be selected carefully. Table below shows the typical range of VOR for optimal performance:

Output Voltage Optimal Range for VOR 5 V 45 - 70 12 V 80 - 120 15 V 100 - 135 20 V 120 - 160 24 V 135 - 180

Rev. F 05/21 www.power.com InnoSwitch4-CZ

Absolute Maximum Ratings1,2 DRAIN Pin Voltage...... -0.3 V to 750 V5 Notes: DRAIN Pin Peak Current: INN4073C...... 6.5 A7 1. All voltages referenced to SOURCE and Secondary GROUND, INN4074C...... 10 A7 TA = 25 °C. INN4075C...... 14 A7 2. Maximum ratings specified may be applied one at a time without BPP/BPS Pin Voltage ...... -0.3 to 6 V causing permanent damage to the product. Exposure to BPP/BPS Current ...... 100 mA Absolute Maximum Ratings conditions for extended periods of FWD Pin Voltage ...... -1.5 V to 150 V time may affect product reliability. FB Pin Voltage ...... -0.3 V to 6 V 3. Normally limited by internal circuitry. SR Pin Voltage ...... -0.3 V to 6 V 4. 1/16” from case for 5 seconds. VOUT Pin Voltage ...... -0.3 V to 27 V 5. Maximum drain voltage (non-repetive pulse) ...... -0.3 V to 750 V. V Pin Voltage ...... -0.3 V to 650 V Maximum continuous drain voltage ...... -0.3 V to 650 V. HSD Pin Voltage ...... -0.3 V to 6 V 6. Absolutely maximum voltage for less than 500 msec is 3 V. IS Pin Voltage6 ...... -0.3 V to 0.3 V 7. Please refer to Figure 24 about maximum voltage and current Storage Temperature ...... -65 to 150 °C combinations. Operating Junction Temperature3 ...... -40 to 150 °C Ambient Temperature ...... -40 to 105 °C Lead Temperature4 ...... 260 °C

Thermal Resistance Thermal Resistance: Notes: 1 2 1. Soldered to 0.36 sq. inch (232 mm2) 2 oz. (610 g/m2) copper clad. (qJA)...... 81 °C/W , 75 °C/W 1 2. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 g/m2) copper clad. (qJC)...... 18 °C/W 3. The case temperature is measured on the top of the package.

Parameter Conditions Rating Units

Ratings for UL1577 Primary-Side Current from pin (16-19) to pin 24 0.6 A Current Rating

Primary-Side T = 25 °C AMB 1.35 W Power Rating (device mounted in socket resulting in TCASE = 120 °C)

Secondary-Side T = 25 °C AMB 0.125 W Power Rating (device mounted in socket)

Package Characteristics Clearance 12.1 mm (typ)

Creepage 11.7 mm (typ)

Distance Through 0.4 mm (min) Insulation (DTI)

Transient Isolation 6 kV (min) Voltage

Comparative Tracking 600 - Index (CTI)

19 www.power.com Rev. F 05/21 InnoSwitch4-CZ

Conditions SOURCE = 0 V Parameter Symbol Min Typ Max Units TJ = -40 °C to 125 °C (Unless Otherwise Specified)

Control Functions Startup Switching f T = 25 °C 23 25 27 kHz Frequency SW J

Jitter Modulation f T = 25 °C, f = 100 kHz 0.80 1.25 1.70 kHz Frequency M J SW

Maximum On-Time tON(MAX) TJ = 25 °C 10.5 16.5 21.5 µs Minimum Primary

Feedback Block-Out tBLOCK tOFF(MIN) µs Timer

VBPP = VBPP + 0.1 V

IS1 (Switch not Switching) 145 300 425 µA

TJ = 25 °C BPP Supply Current INN4073C 1.7 2.1 2.7

VBPP = VBPP + 0.1 V

IS2 (Switch Switching at ƒSREQ) INN4074C 2.7 3.2 3.7 mA

TJ = 25 °C INN4075C 2.7 3.2 3.7

ICH1 VBP = 0 V, TJ = 25 °C -1.75 -1.35 -0.88 BPP Pin Charge Current mA

ICH2 VBP = 4 V, TJ = 25 °C -5.98 -4.65 -3.32

BPP Pin Voltage VBPP TJ = 25 °C 5 5.16 V BPP Pin Voltage V T = 25 °C 0.5 V Hysteresis BPP(H) J

BPP Shunt Voltage VSHUNT IBPP = 2 mA 5.16 5.36 5.7 V BPP Power-Up Reset V T = 25 °C 2.8 3.15 3.5 V Threshold Voltage BPP(RESET) J

UV/OV Pin Brown-In I T = 25 °C 23.1 25.2 27.5 µA Threshold UV+ J

UV/OV Pin Brown-Out I T = 25 °C 20.5 23 25 µA Threshold UV- J

Brown-Out Delay Time tUV- TJ = 25 °C 35 ms UV/OV Pin Line I T = 25 °C 106 115 118 µA Overvoltage Threshold OV+ J

UV/OV Pin Line I T = 25 °C 8 µA Overvoltage Hysteresis OV(H) J

UV/OV Pin Line

Overvoltage Recovery IOV- TJ = 25 °C 100 µA Theshold

Rev. F 05/21 www.power.com InnoSwitch4-CZ

Conditions SOURCE = 0 V Parameter Symbol Min Typ Max Units TJ = -40 °C to 125 °C (Unless Otherwise Specified)

Line Fault Protection VOLTAGE Pin Line Over- T = 25 °C t J 3 µs voltage Deglitch Filter OV+ See Note B

VOLTAGE Pin Voltage V T = 25 °C 650 V Rating V J Circuit Protection di/dt = 400 mA/ms INN4073C 1581 1700 1819 T = 25 °C I J Standard Current Limit LIMIT di/dt = 475 mA/ms (BPP) Capacitor = (Switch INN4074C 1953 2100 2247 mA switching at T = 25 °C 0.47 mF J 100 kHz) di/dt = 500 mA/ms INN4075C 2139 2300 2461 TJ = 25 °C di/dt = 400 mA/ms INN4073C 1748 1900 2052 T = 25 °C I J Increased Current Limit LIMIT+1 (Switch di/dt = 475 mA/ms (BPP) Capacitor = INN4074C 2162 2350 2538 mA switching at T = 25 °C 4.7 mF J 100 kHz) di/dt = 500 mA/ms INN4075C 2374 2576 2786 TJ = 25 °C Overload Detection f T = 25 °C 130 140 151 kHz Frequency OVL J

BYPASS Pin Latching

Shutdown Threshold ISD TJ = 25 °C 6.0 7.5 11.3 mA Current

Auto-Restart On-Time tAR TJ = 25 °C 75 82 89 ms Auto-Restart Trigger T = 25 °C t J 1.3 sec Skip Time AR(SK) See Note A

Auto-Restart Off-Time tAR(OFF) TJ = 25 °C 1.70 2.00 2.11 sec Short Auto-Restart t T = 25 °C 0.20 sec Off-Time AR(OFF)SH J

HSD On-Time tHSD TJ = 25 °C 440 500 560 ns

21 www.power.com Rev. F 05/21 InnoSwitch4-CZ

Conditions SOURCE = 0 V Parameter Symbol Min Typ Max Units TJ = -40 °C to 125 °C (Unless Otherwise Specified)

Output T = 25 °C 0.52 0.68 INN4073C J

ID = ILIMIT+1 TJ = 100 °C 0.78 1.02

T = 25 °C 0.35 0.44 INN4074C J ON-State Resistance RDS(ON) W ID = ILIMIT+1 TJ = 100 °C 0.49 0.62

T = 25 °C 0.29 0.39 INN4075C J

ID = ILIMIT+1 TJ = 100 °C 0.41 0.54

VBPP = VBPP + 0.1 V

IDSS1 VDS = 80% Peak Drain Voltage 200 mA T = 125 °C OFF-State Drain J Leakage Current VBPP = VBPP + 0.1 V

IDSS2 VDS = 325 V 15 mA

TJ = 25 °C

Thermal Shutdown TSD See Note A 135 142 150 °C Thermal Shutdown T See Note A 70 °C Hysteresis SD(H)

Drain Supply Voltage 50 V

Rev. F 05/21 www.power.com InnoSwitch4-CZ

Conditions SOURCE = 0 V Parameter Symbol Min Typ Max Units TJ = -40 °C to 125 °C (Unless Otherwise Specified)

Secondary

Feedback Pin Voltage VFB TJ = 25 °C 1.250 1.265 1.280 V Maximum Switching f T = 25 °C 164 180 194 kHz Frequency SREQ J

Auto-Restart Threshold VVO(AR) TJ = 25 °C 3.45 V t Output Voltage Pin FB(AR) t T = 25 °C 50 ms Auto-Restart Timer VOUT(AR) J tIS(AR) BPS Pin Current at I T = 25 °C 380 485 mA No-Load SNL J

BPS Pin Voltage VBPS 4.3 4.5 4.7 V BPS Pin Undervoltage V 3.60 3.80 4.00 V Threshold BPS(UVLO)(TH)

BPS Pin Undervoltage V 0.7 V Hysteresis BPS(UVLO)(H)

Current Limit Set by External Resistor ISV(TH) 35.17 36 36.62 mV Voltage Threshold TJ = 25 °C

FWD Pin Voltage VFWD 150 V

Minimum Off-Time tOFF(MIN) 1.76 1.9 2.03 ms BPS Pin Latch Command

Shutdown Threshold IBPS(SD) 5.2 8.9 12 mA Current

Feedback Pin V T = 25 °C 100 mV Short-Circuit FB(OFF) J

23 www.power.com Rev. F 05/21 InnoSwitch4-CZ

Conditions SOURCE = 0 V Parameter Symbol Min Typ Max Units TJ = -40 °C to 125 °C (Unless Otherwise Specified)

Synchronous Rectifier @ TJ = 25 °C

SR Pin Drive Voltage VSR 4.3 4.5 4.7 V SR Pin Voltage V -6 0 mV Threshold SR(TH)

TJ = 25 °C SR Pin Pull-Up Current ISR(PU) 125 165 195 mA CLOAD = 2 nF, fSW = 100 kHz

SR Pin Pull-Down TJ = 25 °C ISR(PD) 315 365 415 mA Current CLOAD = 2 nF, fSW = 100 kHz

TJ = 25 °C Rise Time tR 10-90% 50 ns CLOAD = 2 nF

TJ = 25 °C Fall Time tF 90-10% 25 ns CLOAD = 2 nF

T = 25 °C Output Pull-Up J R V = 4.4 V 6 8.9 10.5 W Resistance PU BPS ISR = 10 mA

T = 25 °C Output Pull-Down J R V = 4.4 V 2.4 3.3 5 W Resistance PD BPS ISR = 10 mA

NOTES: A. This parameter is derived from characterization. B. This parameter is guaranteed by design. C. To ensure correct current limit it is recommended that nominal 0.47 mF / 4.7 mF capacitors are used. In addition, the BPP capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization.

Nominal BPP Pin Capacitor Value BPP Capacitor Minimum Value Tolerance Maximum

0.47 mF -60% +100%

4.7 mF -50% N/A

Recommended to use at least 10 V / 0805 / X7R SMD MLCC.

Rev. F 05/21 www.power.com InnoSwitch4-CZ

Typical Performance Curves

25 10000 Scaling Factors: Scaling Factors: INN4073C 0.62 INN4073C 0.62 20 INN4074C 1.0 INN4074C 1.0 INN4075C 1.4 INN4075C 1.4 PI-8852q-120420 PI-8853q-120420 (A) 1000 DS 15

10 100

Drain Current I 5 TCASE = 25 °C Drain Capacitance (pF) TCASE = 100 °C

0 10 0 2 4 6 8 10 0 50 150 250 350 450 550

Drain Voltage VDS (V) Drain Voltage (V)

Figure 21. Output Characteristics. Figure 22. COSS vs. Drain Voltage.

250 100 Scaling Factors: INN4073C 0.62 200 INN4074C 1.0 10

INN4075C 1.4 PI-8851s-120420 PI-8854p-120420 Scaling Factors: INN4073C 0.65 150 1 INN4074C 1.0 INN4075C 1.4

100 0.1 Power (mW) Drian Current (A) Drian Current 50 0.01

0 0.001 0 100 200 300 400 500 10 100 1000 Drain Voltage (V) Drain Voltage (V) Figure 23. Drain Capacitance Power. Figure 24. Maximum Allowable Drain Current vs. Drain Voltage.

VSR(t) 1.

-0.0 1.2 I-4- -0.3 PI-7474-011215 1.0

0. e e F e / 1 e e 0. ve e e e ee e Pin Voltage Limits (V) Pin Voltage Limits 0.2

oi Cnt iit Cnt oi e / . 0

SYNCHRONOUS RECTIFIER DRIVE SYNCHRONOUS -1.8 1 2 500 ns Time (ns) oi it Figure 25. SYNCHRONOUS RECTIFIER DRIVE Pin Negative Voltage. Figure 26. Standard Current Limit vs. di/dt.

25 www.power.com Rev. F 05/21 InnoSwitch4-CZ Re. 0.5 0.01 0.5 10001 2 Rev Rev 2 0.25 0.010 0.25 0.00 0.10 ee 1. e e e e 1. 1.5 e eee e e e 2. e eee e e e eve ee . e e eee e. e 0.00 0.1 e. ve e e e . . ee e e . e. ee e 5. . eee e . 0.25 0.010 0.25 0 0.1 0.02 0.1 0.020 0.51 e e

2 0.20 0.00 Re. 0.00 0.20 1 0.0 0.012 0.0 0.00 0.1 0.10 0.00 0.00 0.10 .0 0.0 .0 e e 2 2.1 0.10 2.1 0.102 2.5 InS-4

1.2 0.052 Re. 0.052 1.2 0.15 0.00 0.00 0.15 0.15 0.00 0.00 0.15 1

e e 5 e e 5 12 e e 12 1. 0.52 1.

12 0.0 0.012 0.0 0.00 0.20 1 0.25 0.010 0.010 0.25 0.10 0.00 0.10 1 e 1 1 0.50 0.020 Re. 0.020 0.50 2

0.5 0.00 0.5 2 1.0 0. . 0. 1.0 e .5 0.12 Re. 0.12 .5 2 1 .. 1 0.10 0.00 0.00 0.10 e 1.5 0.05 1.5 0.0 1.25 10.0 0.25 10.0

Rev. F 05/21 www.power.com InnoSwitch4-CZ

PACKAGE MARKING

InSOP-24D

INN4073 C M6J542A D A 1738 B 1 Hxxx E

A. Power Integrations Registered Trademark B. Assembly Date Code (last two digits of year followed by 2-digit work week) C. Product Identification (Part #/Package Type) D. Lot Identification Code E. Test Sublot and Feature Code PI-8727k-123020

27 www.power.com Rev. F 05/21 InnoSwitch4-CZ

Feature Code Table

Secondary Feature AR OTP AR and OVL Output Line V OVP Fault Code Threshold Response Response Profile OUT OV/UV Response H181 63% Hysteretic AR Fixed CC Enable AR Enabled / Enable H182 3.45 V Latch-Off AR Fixed CC ‒ Latch-Off Enabled / Enable H183 63% Latch-Off Latch-Off Fixed CC ‒ Latch-Off Enabled / Enable H185 OL Hysteretic AR CV only Enable AR Enabled / Enable H186 OL Hysteretic AR CV only Enable Latch-Off Disabled / Enabled

MSL Table

Part Number MSL Rating

INN4073C - INN4075C 3

ESD and Latch-Up Table

Test Conditions Results

Latch-up at 125 °C JESD78D > ±100 mA or > 1.5 × VMAX on all pins Human Body Model ESD ANSI/ESDA/JEDEC JS-001-2014 > ±2000 V on all pins

ANSI/ESDA/JEDEC Charge Device Model ESD > ±500 V on all pins JS-002-2014

Part Ordering Information • InnoSwitch4-CZ Product Family • CZ Series Number • Package Identifier C InSOP-24D • Features Code • Tape & Reel and Other Options INN 4073 C - H181 - TL TL Tape & Reel, 2 k pcs per reel.

Rev. F 05/21 www.power.com InnoSwitch4-CZ

Notes

29 www.power.com Rev. F 05/21 Revision Notes Date B Code A release. 12/20

C Corrected Typ value for ISR(PD). 02/21 D Updated Figure 8. 03/21 E Updated per DSC-21151 Primary-Side Current Rating on page 19. 04/21 F Removed H184 Feature Code from Feature Code Table on page 28. 05/21

For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at www.power.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperPLC, HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2020, Power Integrations, Inc.

Power Integrations Worldwide Sales Support Locations

World Headquarters Germany (AC-DC/LED Sales) Italy Singapore 5245 Hellyer Avenue Einsteinring 24 Via Milanese 20, 3rd. Fl. 51 Newton Road San Jose, CA 95138, USA 85609 Dornach/Aschheim 20099 Sesto San Giovanni (MI) Italy #19-01/05 Goldhill Plaza Main: +1-408-414-9200 Germany Phone: +39-024-550-8701 Singapore, 308900 Customer Service: Tel: +49-89-5527-39100 e-mail: [email protected] Phone: +65-6358-2160 Worldwide: +1-65-635-64480 e-mail: [email protected] e-mail: [email protected] Japan Americas: +1-408-414-9621 Germany (Gate Driver Sales) Yusen Shin-Yokohama 1-chome Bldg. Taiwan e-mail: [email protected] HellwegForum 3 1-7-9, Shin-Yokohama, Kohoku-ku 5F, No. 318, Nei Hu Rd., Sec. 1 China (Shanghai) 59469 Ense Yokohama-shi, Nei Hu Dist. Rm 2410, Charity Plaza, No. 88 Germany Kanagawa 222-0033 Japan Taipei 11493, Taiwan R.O.C. North Caoxi Road Tel: +49-2938-64-39990 Phone: +81-45-471-1021 Phone: +886-2-2659-4570 Shanghai, PRC 200030 e-mail: [email protected] e-mail: [email protected] e-mail: [email protected] Phone: +86-21-6354-6323 India Korea UK e-mail: [email protected] #1, 14th Main Road RM 602, 6FL Building 5, Suite 21 China (Shenzhen) Vasanthanagar Korea City Air Terminal B/D, 159-6 The Westbrook Centre 17/F, Hivac Building, No. 2, Keji Nan Bangalore-560052 India Samsung-Dong, Kangnam-Gu, Milton Road 8th Road, Nanshan District, Phone: +91-80-4113-8020 Seoul, 135-728, Korea Cambridge Shenzhen, China, 518057 e-mail: [email protected] Phone: +82-2-2016-6610 CB4 1YG Phone: +86-755-8672-8689 e-mail: [email protected] Phone: +44 (0) 7823-557484 e-mail: [email protected] e-mail: [email protected]