Received June 3, 2020, accepted July 7, 2020, date of publication July 9, 2020, date of current version July 29, 2020. Digital Object Identifier 10.1109/ACCESS.2020.3008250 Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies PRATEEK SHANTHARAMA 1, (Graduate Student Member, IEEE), AKHILESH S. THYAGATURU 2, (Member, IEEE), AND MARTIN REISSLEIN 1, (Fellow, IEEE) 1School of Electrical, Computer, and Energy Engineering, Arizona State University (ASU), Tempe, AZ 85287, USA 2Programmable Solutions Group (PSG), Intel Corporation, Chandler, AZ 85226, USA Corresponding author: Martin Reisslein (
[email protected]) This work was supported by the National Science Foundation under Grant 1716121. ABSTRACT In order to facilitate flexible network service virtualization and migration, network func- tions (NFs) are increasingly executed by software modules as so-called ``softwarized NFs'' on General- Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardware-based accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards).