IAETSD JOURNAL FOR ADVANCED RESEARCH IN APPLIED SCIENCES. ISSN NO: 2394-8442

COMPRESSOR BASED 32-32 BIT VEDIC MULTIPLIER USING REVERSIBLE LOGIC

KAVALI USMAVATHI *, PROF. NAVEEN RATHEE** * PG SCHOLAR, Department of VLSI System Design, Bharat Institute of Engineering and Technology ** Professor, Department of Electronics and Communication Engineering at Bharat Institute of Engineering and Technology, TS, India.

ABSTRACT: Vedic arithmetic is the name arithmetic and algebraic operations which given to the antiquated Indian arrangement are accepted by worldwide. The origin of of arithmetic that was rediscovered in the Vedic mathematics is from Vedas and to early twentieth century from antiquated more specific Atharva Veda which deals Indian figures (Vedas). This paper proposes with Engineering branches, Mathematics, the plan of fast Vedic Multiplier utilizing the sculpture, Medicine and all other sciences procedures of Vedic Mathematics that have which are ruling today’s world. Vedic been altered to improve execution. A fast mathematics, which simplifies arithmetic depends enormously on the and algebraic operations, can be multiplier as it is one of the key equipment implemented both in decimal and binary obstructs in most computerized flag number systems. It is an ancient technique, preparing frameworks just as when all is which simplifies , division, said in done processors. Vedic Mathematics complex numbers, squares, cubes, square has an exceptional strategy of estimations roots and cube roots. Recurring decimals based on 16 Sutras. This paper presents and auxiliary fractions can be handled by think about on rapid 32x32 piece Vedic Vedic mathematics. This made possible to multiplier design which is very not quite the solve many Engineering applications, Signal same as the Traditional technique for processing Applications, DFT’s, FFT’s and augmentation like include and move. many more. Vedic mathematics consists of Further, the Verilog HDL coding of Urdhva 16 sutras (formulas) and 13 sub sutras. We tiryakbhyam Sutra for 32x32 vedic used Urdhva Tiryakbhyam method for multiplier. multiplication process.

Keywords: Architecture, Brent-Kung , Vedic mathematics is the ancient Vedic Mathematics, Vedic-Wallace (VW), Indian system of mathematics which mainly Urdhava Tiryakbhyam Sutra, Arithmetic deals with Vedic mathematical formulae and Logic Unit. their application to various branches of mathematics. Vedic mathematics was I.INTRODUCTION: Vedic reconstructed from the ancient Indian Mathematics is a system of reasoning and scriptures (Vedas) by Sri Bharati Krsna mathematical working based on ancient Tirtha after his research on Vedas. He Indian teachings called Veda. It is fast, constructed 16 sutras and 16 upa sutras after efficient and easy to learn and uses all

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extensive research in Atharva Veda. The proposes an implementation of Reversible most famous among these 16 are Nikhilam Urdhva Tiryakbhyam Multiplier which Sutram, Urdhva Tiryakbhyam, and consists of two cardinal features. One is the Anurupye. It has been found that Urdhva fast multiplication feature derived from Tiryakbhyam is the most efficient among Vedic algorithm Urdhva Tiryakbhyam and these. The beauty of Vedic mathematics lies another is the reduced heat dissipation by in the fact that it reduces otherwise the virtue of implementing the circuit using cumbersome looking calculations in reversible logic gates. conventional mathematics to very simple ones. This is so because the Vedic formulae The ancient system of Vedic are claimed to be based on the natural Mathematics was rediscovered from the principles on which the human mind works. Indian Sanskrit texts known as the Vedas, Hence in DSP blocks can be between 1911 and 1918 by Sri Bharati performed at faster rate. This is a very Krisna Tirthaji (1884-1960) from the interesting field and presents some effective Atharva Vedas. According to his research all algorithms which can be applied to various of mathematics is based on sixteen Sutras, or branches of engineering. Digital signal word-formulas. These formulae describe the processing (DSP) is the technology that is way the mind naturally works and are omnipresent in almost every engineering therefore a great help in directing the student discipline. Faster additions and to the appropriate method of solution. In the multiplications are the order of the day. Vedic system difficult problems or huge Multiplication is the most basic and sums can often be solved immediately by frequently used operations in a CPU. the Vedic method. These striking and beautiful methods are just a part of a Multiplication is an operation of complete system of mathematics which is scaling one number by another. far more systematic than the modern system. Multiplication operations also form the basis Vedic Mathematics manifests the coherent for other complex operations such as and unified structure of mathematics and the convolution, Discrete Fourier Transform, methods are complementary, direct and Fast Fourier Trans forms, etc. With ever easy. increasing need for faster c10ck frequency it becomes imperative to have faster arithmetic It’s a unique technique of unit. Hence Vedic mathematics can be aptly calculations based on simple principles and employed here to perform multiplication. rules, with which any mathematical problem Reversible logic is one of the promising - be it arithmetic, algebra, geometry fields for future low power design trigonometry, or even calculus can be solved technologies. Since one of the requirements mentally. In this paper a simple 16 bit digital of all DSP processors and other hand held multiplier is proposed which is based on devices is to minimize power dissipation Urdhva Tiryakbhyam (Vertically Crosswise) multipliers with high speed and lower Sutra of the Vedic Math. Two binary dissipations are critical. This project numbers (16-bit each) are multiplied with

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this Sutra. The potential of this method is Due to the importance of digital that the power dissipation of this circuit is multipliers in DSP, it has always been an 0.17 mW. & propagation delay of the active area of research. Vedic mathematics proposed architecture is 27.15ns. These is the name given to the ancient system of results are improvements over power mathematics, which was rediscovered from dissipations and delays reported in literature the ancient Indian scriptures between 1911 for Vedic and Booth Multiplier. Array and 1918 by Jagadguru Swami Sri Bharati multiplier, Booth Multiplier and Wallace Krisna Tirthaji (1884-1960), a scholar of Tree multipliers are some of the standard Sanskrit, mathematics, history and approaches used in implementation of philosophy. The whole of Vedic binary multiplier which are suitable for mathematics is based on 16 Vedic sutras, VLSI implementation. which are actually word formulae describing natural ways of solving a whole range of Multipliers are extensively used in mathematical problems. , DSP and Communication applications. For higher order In this project a simple 16 bit digital multiplications, a huge number of adders are multiplier is proposed which is based on to be used to perform the partial product Urdhva Tiryakbhyam (Vertically & addition. The need of high speed multiplier Crosswise) Sutra of the Vedic Math’s. Two is increasing as the need of high speed binary numbers (16-bit each) are multiplied processors are increasing. Higher throughput with this Sutra. The main concept of this arithmetic operations are important to paper is that the power consumption of the achieve the desired performance in many circuit & propagation delay of the proposed real time signal and image processing architecture. applications. One of the key arithmetic operations in such applications is A mathematical process of splitting a multiplication and the development of fast number into equal parts or groups, it is the multiplier circuit has been a subject of process of being separated called division. interest over decades. Reducing the time Divider is basic hardware employs in high delay and power consumption are very speed and advanced digital signal processing essential requirements for many (DSP) units. Its most important role in high applications. precision radar technology, cryptography and linear predictive coding (LPC) for In the past multiplication was speech processing. As the technology implemented generally with a sequence of shrink, dividers perform an important role in addition, subtraction and shift operations. every field like cloud data storage, speech Two most common multiplication processing, payment through NFC. Digital algorithms followed in the digital hardware signal processing is the area where fast are array and Booth processing of bits required, so faster multiplication algorithm. algorithms are introduced. In comparison to other mathematical operations, division is

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the sequentional type of operation that exists when compare to conventional results in complex hardware Multipliers. In conventional multipliers we implementation. The highly accurate use AND gates to generate Partial Products, division algorithms are the basic Binary adders for summation of Partial requirement in real-time signal and image Products and Carry Save Adders for Final processing applications. The different Product Summation. But in case of Vedic division architectures are developed to Multiplier to reduce complexity the same reduce the computational difficulties. The 16x16 bit Vedic multiplier can be SRT (Sweeny Robertson and Tocher) implemented using 8 bit multipliers. division, Newton Rap son Method and Long Division Method are the most widely used High-speed parallel multipliers are division techniques.SRT division is the digit one of the keys in RISCs (Reduced recurrence algorithm, where input operands Instruction Set ), DSPs (Digital are the floating point n bit with sign-and- Signal Processors), and graphics magnitude representation. Newton Raphson accelerators and so on. Array multiplier, method is applied when a series of equations Booth Multiplier and Wallace Tree in the damping infinitesimal steps take multipliers are some of the standard place. Another most common technique is approaches used in implementation of restoring division in which repetitive digit binary multiplier which are suitable for method is used by which digits are added VLSI implementation. A simple digital back or restored to remainder adder. This multiplier (henceforth referred to as Vedic design approach accurately speeds up Multiplier in short VM) architecture based operation and faster to implement. on the Urdhva Tiryakbhyam (Vertically and Cross wise) Sutra of Vedic Mathematics is II.EXISTING METHOD: presented. An improved technique for low Conventional Multiplier Vs Vedic power and high speed multiplier of two binary numbers (16 bit each) is developed. Multiplier An algorithm is proposed and implemented on 16nm CMOS technology. The designed In Conventional Multipliers Final 16x16 bit multiplier dissipates a power of Product is obtained by adding partial 0.17 mW. The propagation delay time of the products along with its previous stage carry proposed architecture is 27.15ns. These outs. With this great amount of delay exists. results are many improvements over power As number of bits increases Hardware dissipations and delays reported in literature complexity increases, Delay increases and for Vedic and Booth Multiplier. power increases. But in case of Vedic Multiplier Large modules can be divided 2.2 Design Factor Of Multiplication into sub modules and any arithmetic Latency, throughput, area, and design operations can be performed in parallel. complexity are the important factors to Most suitable for Large number of bits choose a suitable design for the requirement. where Parallelism, Regularity, Concurrency Latency is a measure of how long the inputs

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to a device are stable until the final result slowly as compared to other conventional available on outputs. Throughput is the multipliers. measure of how many multiplications can be performed in a given period of time. This is the general formula applicable to all cases of multiplication. 2.2.1 Urdhva Tiryakbhyam Sutra Urdhva Tiryakbhyam means “Vertically and Cross wise”, which is the method of The proposed Vedic multiplier is multiplication followed. based on the “Urdhva Tiryakbhyam” sutra (algorithm). These Sutras have been traditionally used for the multiplication of two numbers in the decimal number system. In this work, we apply the same ideas to the system to make the proposed algorithm compatible with the digital hardware. It is a general multiplication formula applicable to all cases of multiplication. It literally means “Vertically and Cross wise”. It is based on a novel concept through which the generation of all partial products can be done with the concurrent addition of these partial products.

The algorithm can be generalized for n x n bit number. Since the partial products and their sums are calculated in parallel, the multiplier is independent of the clock frequency of the processor. Due to its Thus, integrating Vedic mathematics for the regular structure, it can be easily layout in multiplier design will enhance the speed of microprocessors and designers can easily multiplication operation. The multiplier circumvent these problems to avoid architecture is based on Urdhva catastrophic device failures. The processing Tiryagbhyam (vertical and cross-wise power of multiplier can easily be increased algorithm) sutra. An illustration of Urdhva by increasing the input and output data bus Tiryagbhyam sutra is shown in Figure. widths since it has a quite a regular structure. Due to its regular structure, it can be easily layout in a silicon chip. The Multiplier based on this sutra has the advantage that as the number of bits increases, gate delay and area increases very

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III.PRPOSED METHOD: Vedic multiplicand is multiplied with the next higher bit of the multiplier and added to, the Mathematical Formulae: product of LSB of the multiplier and the next higher bit of the multiplicand What we call VEDIC (crosswise). The sum gives the second bit of MATHEMATICS is a mathematical the final product and the carry is added to elaboration of 'Sixteen Simple Mathematical the partial product obtained by multiplying formulae from the Vedas' as brought out by the most significant bits to give the sum and Sri Bharati Krishna Tirthaji. In the text carry. The sum is the third corresponding bit authored by the Swamiji, nowhere has the and the carry becomes the fourth bit of the list of the Mathematical formulae (Sutras) final product. been given. But the Editor of the text has compiled the list of the formulae from stray references in the text. The list so compiled contains Sixteen Sutras and Thirteen Sub Sutras as stated hereunder. The final result will be c2s2s1s0. This The hardware architecture of 2x2, 4x4, 8x8, multiplication method is applicable for all 16x16, 32x32 bit Vedic Wallace multiplier the cases. The 2x2 bit Vedic Wallace (VW) modules are displayed in below multiplier is implemented by using four sections. Here, “Urdhva-Tiryakbhyam” input AND gates along with two half- (Vertically and crosswise) sutra is used to adders. In the same way, 4, 8, 16, 32 and N propose such an architecture for the bit multipliers are designed with a little multiplication of two binary numbers. The modification. beauty of Vedic Wallace multiplier is that, here partial product generation and additions are done concurrently. Hence, it is a well adapted parallel processing. The features make it more attractive for binary multiplications. This reduces delay and this is the primary motivation behind this work.

3.1 Vedic Wallace Multiplier for 2x2 Bit Module

The method is explained for two, 2-bit numbers A and B where A=a a and B=b b as shown in Figure 4. Firstly, the 1 0 1 0 least significant bits are multiplied which gives the least significant bit of the final product 16x16 vedic multiplier (Vertical). Then, the LSB of the

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, 32-bit arithmetic unit, logical unit and 32-bit ALU has been done.

IV.RESULTS DISCURSION:

Proposed Schematic Diagram of 32x32 bit Vedic Wallace based Multiplier

The 32x32 Vedic Wallace Multiplier Schematic of 32-bit RTL Implementation modules are realized using four 16x16 using Vedic Wallace Multiplier multiplier modules. The processing of 32x32 multiplier based on Vedic Wallace methodology is depicted in above Figure. Demonstrating with an example of two digits consisting of 32 bits, the output is obtained in 64 bits length.

ALU was designed to perform the arithmetic and logical operations for the controller. Arithmetic operations performed are the 32- bit addition, subtraction, and multiplication. Simulation Results of 32-bit Multiplier Logical operations performed are AND, OR, based on Vedic Wallace XOR, NAND, NOR, XNOR, NOT and Data Buffer. For designing the ALU, the authors V.CONCLUSION: Compressor based had followed a flexible design that consists Vedic Multiplier has been designed using of smaller, but more manageable blocks, Reversible logics and the functional some of which can be re-used [2]. Designing correctness of the proposed Vedic of half-adder, 2-bit multiplier, 4-bit Brent- multiplier. We have proposed novel high Kung, 4-bit multiplier, 8-bit Brent-Kung speed architecture for multiplication of two adder, 8-bit multiplier, 8-bit full adder, 8-bit 8 bit numbers, combining the advantages of subtractor, 32-bit Brent-Kung adder, 32-bit compressor based reverse logic adders and multiplier, 32-bit full adder, 32-bit also the ancient Vedic math’s methodology.

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A new 4:2 compressor designed with 2 S. F. Hsiao, M.R. Jiang and J.S. Yeh, reversible gates architecture was also "Design of high-speed low-power 3-2 discussed. Upon comparison of the area counter and 4-2 compressor for fast occupied by the multiplier and also its multipliers," Electronics Letters, vol. 34, no. speed, with two other popular multipliers. 4, pp. 341-342, Feb. 1998. We can conclude that the compressor based 3. M.Margala and N.G. Durdle, "Low- reverse Vedic math’s multiplier proves to be Power Low-Voltage 4-2 Compressors for a better option over conventional multipliers VLSI Applications," Proc. Workshop on used in several expeditious and complex Low Power Design, 1999. VLSI circuits. 4 S.Veeramachanemi, K.Krishna, L.Avinash, S.R.Puppola, M.B.Srinivas, FUTURE SCOPE: In future, both “Novel architectures for high speed and measured and simulation results have shown lowpower 3-2, 4-2 and 5-2 compressors”, that systematic design of Vedic multiplier IEEE Proc .Of VLSID’07,pp.324- with bit size increment of 32 bit and 64 bit 329,2007. with less complexity. If use FPGA for this in 5 HimanshuThapliyal and M.B Srinivas future and we will include addition, “Novel Reversible Multiplier Architecture subtraction and multiplication then it will act Using Reversible TSG Gate” as Vedic ALU. We can use this in Systems & Applications, 2006 IEEE computers. It will decrease power and area. International Conference, pages 100-103. REFRENCES: 6 Md. M. H Azad Khan, “Design of Full- adder With Reversible Gates”, International 1.D. Radhakrishnan A.P. PreethySingapore Conference on Computer and Information “Low Power CMOS Pass Logic 4-2 Technology, Dhaka, Bangladesh, 2002, pp. Compressor for High-Speed 515-519. Multiplication”,circuits and systems, 2000,

Proceedings of the 43rd IEEE Midwest Symposium, pages 1296-1298. Author profiles:

Student details:

KAVALI USMAVATHI pursing M.tech in vlsi system design [email protected]

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Guide profile:

Prof. Naveen Rathee With B.E (E&T), M.Tech (ECE), PhD (ECE) and hardcore Industrial experience of 08 years working as Project Manager in Bottling plant and Power Cable Industries and rich Academic experience of 15 years to his credit, presently spearheading the post of Professor and Project Incharge in the Department of Electronics and Communication Engineering at Bharat Institute of Engineering and Technology from 2017 onwards. His area of Interest includes Digital System Design, Embedded Systems Design, Reconfigurable FPGAs, and OFDM-MIMO Systems. [email protected]

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