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Design of a Binary Multiplier for Unsigned Numbers

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Design of a Binary Multiplier for Unsigned Numbers WESTERN UNIVERSTT FACULTY OF ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING ES434a: Advanced Digital Systems Lab 3 Binary Multiplier for Unsigned Numbers In class a serial-parallel multiplier and an array multiplier were described (sections 4.8 and 4.9, pg 210-219 “Digital Systems Design Using VHDL (Second Edition)”). Comparing these two designs reveals the following: The serial-parallel multiplier requires fewer components to implement then the array multiplier. For an N-bit by N-bit multiplier the circuit complexity increases linearly with N for a serial-parallel multiplier, whereas the circuit complexity increases by N2 for array multiplier. An array multiplier is significantly faster than a serial-parallel multiplier. This is due to the fact that many clock cycles are required to manipulate the control unit of the serial-parallel multiplier. The goal of this assignment is to design 9-bit by 9-bit multiplier for unsigned numbers. The proposed design will encompass the attributes of both the serial-parallel multiplier and the array multiplier. Your design will have the following components: 1. Three array multipliers capable of multiplying two 3-bit numbers (see figure 4.29, pg 217 of textbook). 2. One adder capable of adding two N-bit by N-bit numbers including a carry in. The output of the adder has N-bits for the sum and a carry out bit. Determine the minimum number of N required by the adder for the overall circuit to work. 3. 21-bit shift register. Before starting the multiplication, bits 0 to 8 will be used to hold the multiplier and bits 9 to 17 are used as the accumulator. Bits 19 to 21 can be used to store carry bits. When the multiplication is done bits 0 to 17 will hold the product. This setup is similar to the design in figure 4.25, pg 211 of textbook. 4. Control unit. The control unit outputs appropriate signals to perform multiplication. The multiplication circuit performs the following steps. Consider the following example 546 (octal) 348 (decimal) 123 (octal) 83 (decimal) 22 (3*6) 29714 (decimal) step1 14 (3*4) 17 __ (3*5) 2062 14 (2*6) step2 10 (2*4) 12___ (2*5) 15222 6 (1*6) step3 4 (1*4) 5 _ (1*5) 72022 (octal) Each step requires 3 multiplications and 3 additions. The multiplications are preformed in parallel using the 3 array multipliers. Next, 3 clock cycle is required to perform 3 additions. For each addition, the control unit must output appropriate signals so that the results of the adder are stored at the appropriate register location. An additional clock cycle is required to shift the registers by 3 to the right. For the example described the register should contain the following values after each multiply/add and shift command 21 bit shift register (20-18) (17-15) (14-12) (11-9) (8-6) (5-3) (2-0) load 0 0 0 0 1 2 3 mult/add 2 0 6 2 1 2 3 shift 3 0 2 0 6 2 1 2 mult/add 1 5 2 2 2 1 2 shift 3 0 1 5 2 2 2 1 mult/add 0 7 2 0 2 2 1 shift 3 0 0 7 2 0 2 2 Implement the above circuit in VHDL using any VHDL simulator (i.e. Modelsim). Show the VHDL code for each component (i.e. Control Unit, Adder, Shift Registers, Array Multipliers) and the interconnection of each component to realize overall circuit. Deliverables Report presentation should follow the format of the sample lab report. Include: Derivation of state tables or state graphs of the control unit. Circuit diagram Create a test bench that multiplies the following numbers. Case 1: 546 (octal) * 123 (octal) Case 2: Let x6 to x1 be the 6 lower digits of your student number. If the digits are greater that 7 replace with 7. Multiply: x6 x5 x4 (octal) * x3 x2 x1 (octal). For example if the 6 lower digits of your student number are 986532 then multiply 776 (octal) * 532 (octal) Case 3: 777 (octal) * 000 (octal) Case 4: 000 (octal) * 777 (octal) Show simulation results. Show VHDL code for each component (i.e. Control Unit, Adder, Shift Registers, Array Multipliers) and the interconnection of each component to realize overall circuit. .
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