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Arithmetic Functions and Circuits Chapter 5 Arithmetic Functions and Circuits J.J. Shann Arithmetic ckt: — a combinational ckt that performs arithmetic ops w/ binary numbers or w/ decimal numbers in a binary code ¾ E.g.: addition, subtraction, multiplication, and division Develop arithmetic ckts by means of hierarchical, iterative design J.J. Shann 5-2 Chapter Overview 5-1 Iterative Combinational Circuits 5-2 Binary Adders 5-3 Binary Subtraction 5-4 Binary Adder-Subtractors 5-5 Binary Multiplication 5-6 Other Arithmetic Functions 5-7 HDL Representations – VHDL (×) 5-8 HDL Representations – Verilog (×) 5-9 Chapter Summary J.J. Shann 5-3 5-1 Iterative Combinational Circuits Arithmetic block: — is typically designed to operate on binary input vectors and produce binary output vectors. — The function implemented often requires that the same subfunction be applied to each bit position. ⇒ A function block can be designed for the subfunction and then used repetitively for each bit positions of the overall arithmetic block. cell: a subfunction block — the overall implementation is an array of cell → iterative array J.J. Shann 5-4 Iterative array Iterative array: — a special case of hierarchical ckts — is useful in handling vectors of bits — has the repetitive nature of the ckt & the association of a vector index w/ each of the ckt cells. — The cell in the array are often, but not always, identical. — E.g.: Block diagram of an iterative ckt J.J. Shann 5-5 5-2 Binary Adders Half adder: add 2 bits Full adder: add 2 input bits and a carry-in bit Binary ripple carry adder: add two n-bit binary numbers Carry-lookahead adder J.J. Shann 5-6 A. Half Adder Half adder (HA): adds 2 bits <Design Procedure> Step 1: Specification The basic rule for binary addition: 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 1 0 Input variables: 2; augend and addend bits; X, Y Output variables: 2; sum and carry bits; S, C J.J. Shann 5-7 Step2: Formulation Step 3: Optimization S = x′y + xy′ = x ⊕ y C = xy Step 4: Technology mapping J.J. Shann 5-8 B. Full Adder Full adder (FA): add 3 bits <Design Procedure> Step 1 Input variables: 3; 2 significant bits X, Y & a carry-in bit Z Output variables: 2; sum and carry bits S, C Step 2 J.J. Shann 5-9 Step3 Step 4 J.J. Shann 5-10 C. Binary Ripple Carry Adder Parallel adder: — a digital ckt that produces the arithmetic sum of 2 binary numbers using only combinational logic — uses n full adders in parallel, w/ all input bits applied simultaneously to produce the sum — Design method: hierarchical, iterative design J.J. Shann 5-11 Binary addition: — E.g.: 1011 + 0011 ¾ Truth table: 9 inputs; 2 4-bit numbers & a carry-in bit ⇒ 512 entries (impractical) J.J. Shann 5-12 Implementation of binary ripple carry adder: — The FAs are connected in cascade, w/ the carry output from one FA connected to the carry input of the next FA. — E.g.: 4-bit adder Si = Ai ⊕ Bi ⊕ Ci C = A B + C (A ⊕ B ) i+1 i i i i i J.J. Shann 5-13 Carry Propagation Propagation time of a combinational ckt: (the propagation delay of a typical gate) × (the # of gate levels in the ckt) Propagation time of the binary adder: — the time it takes the carry to propagate through the full adders: 2n + 2 gate delays, n: # of bits of the input numbers ¾ Assumption: delay of XOR gate = 2 J.J. Shann 5-14 J.J. Shann 5-15 Methods of Speeding Addition Method 1: — employ faster gates w/ reduced delays Method 2: — increase the equipment complexity to reduce the carry delay time — most widely used technique: carry lookahead J.J. Shann 5-16 D. Carry Lookahead Adder Ripple carry adder (RCA): — simple — has a long ckt delay in the carry path from LSB to MSB Carry lookahead adder (CLA): — reduce delay at the price of more complex hardware J.J. Shann 5-17 Carry Lookahead Full adder: Si = Ai ⊕ Bi ⊕ Ci Ci+1 = Ai Bi + Ci(Ai ⊕ Bi) Carry lookahead: — Define 2 new binary variables: Pi = Ai ⊕ Bi … carry propagate function propagate the carry from Ci to C i+1 Gi = Ai Bi … carry generate function produce an output carry regardless of the input carry ⇒ Si = Pi ⊕ Ci Ci+1 = Gi + PiCi J.J. Shann 5-18 Ci+1 = Gi + PiCi , C0 = input carry ⇓ C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C = ? 4 = G3 + P3C3 = G +P G + P P G + P P P G + P P P P C 3 3 2 3 2 1 3 2 1 0 3 2 1 0 0 J.J. Shann 5-19 E.g.: 3-bit carry lookahead generator C1 = G0 + P0C0 C2 = G1 + P1G0 + P1P0C0 C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0 J.J. Shann 5-20 E.g.: 4-bit adder Ripple carry Carry lookahead * Propagation delay = 6 J.J. Shann 5-21 CLA Expansion Use the same method: single level CLA Ci+1 = Gi + PiCi , C0 = input carry ⇓ C1 = G0 + P0C0 C2 = G1 + P1G0 + P1P0C0 C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C4 = G3+P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 ⇒ max fan-in = 5 … ⇒ excessive fan-in Multi-level CLA J.J. Shann 5-22 Multi-Level CLA 4-bit groups: — Purpose: reuse the carry lookahead ckt for each group of 4 bits and for 4 4-bit groups as if they were individual bits. ⇒ produce the carries in positions 4, 8, and 12 as fast as possible w/o using excessive fan-in. C4 = G3+P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 Group propagation function: — propagate a carry from C0 to C4 P0−3 = P3P2 P1P0 C4 = G0-3 + P0-3C0 Group generate function: G0−3 = G3 + P3G2 + P3P2G1J.J.+ ShannP3P2 5-23P1G0 4-bit CLA w/ group functions: J.J. Shann 5-24 For 4-bit group: C4 = G0-3 + P0-3C0 C8 = G4-7 + P4-7C4 = G4-7 + P4-7G0-3 + P4-7P0-3C0 C12 = G8-11 + P8-11G4-7 + P8-11P4-7G0-3 + P8-11P4-7P0-3C0 C16 = G? 12-15 + P12-15 G8-11 + P12-15 P8-11 G4-7 + P12-15 P8-11 P4-7 G0-3 + P12-15 P8-11 P4-7 P0-3 C0 J.J. Shann 5-25 Delays: — Assumption: XOR = 2 gate delays 4-bit adder 16-bit adder 64-bit adder Ripple carry 10 34 130 adder (RCA) Carry 6 10 14 lookahead (5 copies in (21 copies in adder 2 levels of 3 levels of (CLA) lookahead) lookahead) J.J. Shann 5-26 5-3 Binary Subtraction (for Unsigned Numbers) Unsigned number subtraction: — Method 1: (§1-3) ¾ Compare the subtrahend w/ the minuend and subtract the smaller from the larger. ¾ Disadv.: The comparison op results in inefficient and costly ckt. — Method 2: by 2’s complement subtract (B.) — Method 3: by 2’s complement addition (C.) J.J. Shann 5-27 A. Complement Two types of complements for each base-r system: — radix complement: r’s complement ¾ e.g.: 2’s complement for binary numbers 10’s complement for decimal numbers — diminished radix complement: (r – 1)’s complement ¾ e.g.: 1’s complement for binary numbers 9’s complement for decimal numbers J.J. Shann 5-28 1’s Complement 1’s complement of an n-bit binary number N: (2n –1) –N 11 … 1 (n 1’s) ≡ subtracting each digit from 1 ≡ changing all 1’s to 0’s and all 0’s to 1’s (applying the NOT op to each of the bits) — E.g.s: 1011001 0001111 ↓ 1’s comp ↓ 1’s comp 0100110 1110000 — E.g.: the 9’s complement of a decimal number is obtained by subtracting each digit from 9 J.J. Shann 5-29 2’s Complement 2’s complement of an n-bit binary number N: 2n – N for N ≠ 0 & 0 for N = 0 ≡ adding 1 to the 1’s complement of N ≡ leaving all least significant 0’s and the 1st 1 unchanged and then replacing 1’s w/ 0’s and 0’s w/ 1’s in all other higher significant bits — E.g.s: 1101100 ↓ 2’s comp 0010100 — The complement of the complement restores the number to its original value. J.J. Shann 5-30 B. Unsigned Binary Subtraction by 2’s Complement Subtract Unsigned number subtraction by 2’s complement subtract : Subtract the subtrahend from the minuend directly: M – N If no end borrow occurs : M ≥ N the result (M – N) is positive and correct If an end borrow occurs: M < N the result (M – N + 2n) must then be negative and the magnitude needs to be corrected by 2’s complement 2n –(M – N + 2n ) = N – M − [2n –(M – N + 2n )] = − (N – M) J.J. Shann 5-31 — E.g.: 10011 − 11110 Borrows into: 11100 Minuend: 10011 Subtrahend: – 11110 Difference: 10101 Correct Difference: – 01011 J.J. Shann 5-32 Example 5-11: Perform the binary subtraction 01100100 – 10010110 <Ans.> Borrows into: 10011110 Minuend: 01100100 Subtrahend: – 10010110 Initial Result: 11001110 28 1 00000000 – Initial Result: – 11001110 Final Result – 00110010 J.J. Shann 5-33 Binary Adder/Subtractor Block diagram of binary adder-subtractor: Subtraction by 2’s complement subtract: Subtract the subtrahend N from the minuend M. If no end borrow occurs, the result is nonnegative and correct. If an end borrow occurs, the difference is subtracted from 2n, and a minus sign is appended to the result. * This ckt is more complex than necessary. ⇒ Share logic b/t adder & subtractor.
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