IAETSD JOURNAL FOR ADVANCED RESEARCH IN APPLIED SCIENCES. ISSN NO: 2394-8442 COMPRESSOR BASED 32-32 BIT VEDIC MULTIPLIER USING REVERSIBLE LOGIC KAVALI USMAVATHI *, PROF. NAVEEN RATHEE** * PG SCHOLAR, Department of VLSI System Design, Bharat Institute of Engineering and Technology ** Professor, Department of Electronics and Communication Engineering at Bharat Institute of Engineering and Technology, TS, India. ABSTRACT: Vedic arithmetic is the name arithmetic and algebraic operations which given to the antiquated Indian arrangement are accepted by worldwide. The origin of of arithmetic that was rediscovered in the Vedic mathematics is from Vedas and to early twentieth century from antiquated more specific Atharva Veda which deals Indian figures (Vedas). This paper proposes with Engineering branches, Mathematics, the plan of fast Vedic Multiplier utilizing the sculpture, Medicine and all other sciences procedures of Vedic Mathematics that have which are ruling today’s world. Vedic been altered to improve execution. A fast mathematics, which simplifies arithmetic processor depends enormously on the and algebraic operations, can be multiplier as it is one of the key equipment implemented both in decimal and binary obstructs in most computerized flag number systems. It is an ancient technique, preparing frameworks just as when all is which simplifies multiplication, division, said in done processors. Vedic Mathematics complex numbers, squares, cubes, square has an exceptional strategy of estimations roots and cube roots. Recurring decimals based on 16 Sutras. This paper presents and auxiliary fractions can be handled by think about on rapid 32x32 piece Vedic Vedic mathematics. This made possible to multiplier design which is very not quite the solve many Engineering applications, Signal same as the Traditional technique for processing Applications, DFT’s, FFT’s and augmentation like include and move. many more. Vedic mathematics consists of Further, the Verilog HDL coding of Urdhva 16 sutras (formulas) and 13 sub sutras. We tiryakbhyam Sutra for 32x32 vedic used Urdhva Tiryakbhyam method for multiplier. multiplication process. Keywords: Architecture, Brent-Kung Adder, Vedic mathematics is the ancient Vedic Mathematics, Vedic-Wallace (VW), Indian system of mathematics which mainly Urdhava Tiryakbhyam Sutra, Arithmetic deals with Vedic mathematical formulae and Logic Unit. their application to various branches of mathematics. Vedic mathematics was I.INTRODUCTION: Vedic reconstructed from the ancient Indian Mathematics is a system of reasoning and scriptures (Vedas) by Sri Bharati Krsna mathematical working based on ancient Tirtha after his research on Vedas. He Indian teachings called Veda. It is fast, constructed 16 sutras and 16 upa sutras after efficient and easy to learn and uses all VOLUME VI, ISSUE VII, JULY/2019 PAGE NO:317 IAETSD JOURNAL FOR ADVANCED RESEARCH IN APPLIED SCIENCES. ISSN NO: 2394-8442 extensive research in Atharva Veda. The proposes an implementation of Reversible most famous among these 16 are Nikhilam Urdhva Tiryakbhyam Multiplier which Sutram, Urdhva Tiryakbhyam, and consists of two cardinal features. One is the Anurupye. It has been found that Urdhva fast multiplication feature derived from Tiryakbhyam is the most efficient among Vedic algorithm Urdhva Tiryakbhyam and these. The beauty of Vedic mathematics lies another is the reduced heat dissipation by in the fact that it reduces otherwise the virtue of implementing the circuit using cumbersome looking calculations in reversible logic gates. conventional mathematics to very simple ones. This is so because the Vedic formulae The ancient system of Vedic are claimed to be based on the natural Mathematics was rediscovered from the principles on which the human mind works. Indian Sanskrit texts known as the Vedas, Hence multiplications in DSP blocks can be between 1911 and 1918 by Sri Bharati performed at faster rate. This is a very Krisna Tirthaji (1884-1960) from the interesting field and presents some effective Atharva Vedas. According to his research all algorithms which can be applied to various of mathematics is based on sixteen Sutras, or branches of engineering. Digital signal word-formulas. These formulae describe the processing (DSP) is the technology that is way the mind naturally works and are omnipresent in almost every engineering therefore a great help in directing the student discipline. Faster additions and to the appropriate method of solution. In the multiplications are the order of the day. Vedic system difficult problems or huge Multiplication is the most basic and sums can often be solved immediately by frequently used operations in a CPU. the Vedic method. These striking and beautiful methods are just a part of a Multiplication is an operation of complete system of mathematics which is scaling one number by another. far more systematic than the modern system. Multiplication operations also form the basis Vedic Mathematics manifests the coherent for other complex operations such as and unified structure of mathematics and the convolution, Discrete Fourier Transform, methods are complementary, direct and Fast Fourier Trans forms, etc. With ever easy. increasing need for faster c10ck frequency it becomes imperative to have faster arithmetic It’s a unique technique of unit. Hence Vedic mathematics can be aptly calculations based on simple principles and employed here to perform multiplication. rules, with which any mathematical problem Reversible logic is one of the promising - be it arithmetic, algebra, geometry fields for future low power design trigonometry, or even calculus can be solved technologies. Since one of the requirements mentally. In this paper a simple 16 bit digital of all DSP processors and other hand held multiplier is proposed which is based on devices is to minimize power dissipation Urdhva Tiryakbhyam (Vertically Crosswise) multipliers with high speed and lower Sutra of the Vedic Math. Two binary dissipations are critical. This project numbers (16-bit each) are multiplied with VOLUME VI, ISSUE VII, JULY/2019 PAGE NO:318 IAETSD JOURNAL FOR ADVANCED RESEARCH IN APPLIED SCIENCES. ISSN NO: 2394-8442 this Sutra. The potential of this method is Due to the importance of digital that the power dissipation of this circuit is multipliers in DSP, it has always been an 0.17 mW. & propagation delay of the active area of research. Vedic mathematics proposed architecture is 27.15ns. These is the name given to the ancient system of results are improvements over power mathematics, which was rediscovered from dissipations and delays reported in literature the ancient Indian scriptures between 1911 for Vedic and Booth Multiplier. Array and 1918 by Jagadguru Swami Sri Bharati multiplier, Booth Multiplier and Wallace Krisna Tirthaji (1884-1960), a scholar of Tree multipliers are some of the standard Sanskrit, mathematics, history and approaches used in implementation of philosophy. The whole of Vedic binary multiplier which are suitable for mathematics is based on 16 Vedic sutras, VLSI implementation. which are actually word formulae describing natural ways of solving a whole range of Multipliers are extensively used in mathematical problems. Microprocessors, DSP and Communication applications. For higher order In this project a simple 16 bit digital multiplications, a huge number of adders are multiplier is proposed which is based on to be used to perform the partial product Urdhva Tiryakbhyam (Vertically & addition. The need of high speed multiplier Crosswise) Sutra of the Vedic Math’s. Two is increasing as the need of high speed binary numbers (16-bit each) are multiplied processors are increasing. Higher throughput with this Sutra. The main concept of this arithmetic operations are important to paper is that the power consumption of the achieve the desired performance in many circuit & propagation delay of the proposed real time signal and image processing architecture. applications. One of the key arithmetic operations in such applications is A mathematical process of splitting a multiplication and the development of fast number into equal parts or groups, it is the multiplier circuit has been a subject of process of being separated called division. interest over decades. Reducing the time Divider is basic hardware employs in high delay and power consumption are very speed and advanced digital signal processing essential requirements for many (DSP) units. Its most important role in high applications. precision radar technology, cryptography and linear predictive coding (LPC) for In the past multiplication was speech processing. As the technology implemented generally with a sequence of shrink, dividers perform an important role in addition, subtraction and shift operations. every field like cloud data storage, speech Two most common multiplication processing, payment through NFC. Digital algorithms followed in the digital hardware signal processing is the area where fast are array multiplication algorithm and Booth processing of bits required, so faster multiplication algorithm. algorithms are introduced. In comparison to other mathematical operations, division is VOLUME VI, ISSUE VII, JULY/2019 PAGE NO:319 IAETSD JOURNAL FOR ADVANCED RESEARCH IN APPLIED SCIENCES. ISSN NO: 2394-8442 the sequentional type of operation that exists when compare to conventional results in complex hardware Multipliers. In conventional multipliers we implementation. The highly accurate use AND gates to generate Partial Products, division algorithms are